LTC3851AIUD-1#PBF - ANALOG DEVICES

LTC3851A-1

3851a1fa

Typical applicaTion

FeaTures

applicaTions

DescripTion

Synchronous

Step-Down Switching

Regulator Controller

The LTC

3851A-1 is a high performance synchronous

step-down switching regulator controller that drives

an all N-channel synchronous power MOSFET stage. A

con stant frequency current mode architecture allows a

phase-lockable frequency of up to 750kHz.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The LTC3851A-1 features a precision 0.8V

reference and a power good indicator. A wide 4V to 38V

(40V absolute maximum) input supply range encompasses

most battery conﬁgurations and intermediate bus voltages.

The TK/SS pin ramps the output voltage during start-up and

shutdown with coincident or ratiometric tracking. Current

foldback limits MOSFET heat dissipation during short-

circuit conditions. The MODE/PLLIN pin selects among

Burst Mode operation, pulse-skipping mode or continu-

ous inductor current mode at light loads and allows the IC

to be synchronized to an external clock. The LTC3851A-1

contains an improved PLL compared to the LTC3851-1.

The LTC3851A-1 is identical to the LTC3851A except that

the ILIM pin is replaced by PGOOD.

High Efﬁciency Synchronous Step-Down Converter

n Wide VIN Range: 4V to 38V Operation

n RSENSE or DCR Current Sensing

n ±1% Output Voltage Accuracy

n Power Good Output Voltage Monitor

n Phase-Lockable Fixed Frequency: 250kHz to 750kHz

n Dual N-Channel MOSFET Synchronous Drive

n Very Low Dropout Operation: 99% Duty Cycle

n Adjustable Output Voltage Soft-Start or Tracking

n Output Current Foldback Limiting

n Output Overvoltage Protection

n OPTI-LOOP

Compensation Minimizes COUT

n Selectable Continuous, Pulse-Skipping or

Burst Mode

Operation at Light Loads

n Low Shutdown IQ: 20µA

n VOUT Range: 0.8V to 5.5V

n Thermally Enhanced 16-Lead MSOP

or 3mm × 3mm QFN Package

n Automotive Systems

n Telecom Systems

n Industrial Equipment

n Distributed DC Power Systems

Efﬁciency and Power Loss

vs Load Current

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered

trademarks and No RSENSE, UltraFast are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131.

PGO0D

RUN

TK/SS

ITH

FREQ/PLLFLTR

VIN

INTVCC

MODE/PLLIN

SENSE+

SENSE–

VFB

GND

0.047µF

0.1µF

4.7µF

3.01k

LTC3851A-1

22µF

VIN

4.5V TO 38V

VOUT

3.3V

15A

3851A1 TA01a

0.68µH

330pF

2200pF

0.1µF

0.1µF 330µF

×2

BOOST

15k

154k

48.7k

30.1k

82.5k

100k

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100 1000 10000 100000

3851A1 TA01b

100

1000

100

10000

VIN = 12V

VOUT = 3.3V

EFFICIENCY

POWER LOSS

LTC3851A-1

3851a1fa

absoluTe MaxiMuM raTings

Input Supply Voltage (VIN) ......................... 40V to –0.3V

Topside Driver Voltage (BOOST) ................ 46V to –0.3V

Switch Voltage (SW) ..................................... 40V to –5V

INTVCC, (BOOST – SW), RUN, PGOOD ........ 6V to –0.3V

TK/SS ...................................................INTVCC to –0.3V

SENSE+, SENSE– .......................................... 6V to –0.3V

MODE/PLLIN, FREQ/PLLFLTR ..............INTVCC to –0.3V

ITH, VFB Voltages ......................................... 3V to –0.3V

(Note 1)

MODE/PLLIN

FREQ/PLLFLTR

RUN

TK/SS

ITH

SENSE–

SENSE+

BOOST

VIN

INTVCC

GND

PGOOD

TOP VIEW

GND

MSE PACKAGE

16-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 35°C/W TO 40°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

16 15 14 13

5678

TOP VIEW

GND

UD PACKAGE

16-LEAD (3mm

3mm) PLASTIC QFN

1RUN

TK/SS

ITH

BOOST

VIN

INTVCC

FREQ/PLLFLTR

MODE/PLLIN

SENSE–

SENSE+

PGOOD

GND

TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

pin conFiguraTion

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3851AEMSE-1#PBF LTC3851AEMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 125°C

LTC3851AIMSE-1#PBF LTC3851AIMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 125°C

LTC3851AHMSE-1#PBF LTC3851AHMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 150°C

LTC3851AMPMSE-1#PBF LTC3851AMPMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –55°C to 150°C

LTC3851AEUD-1#PBF LTC3851AEUD-1#TRPBF LFQB 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C

LTC3851AIUD-1#PBF LTC3851AIUD-1#TRPBF LFQB 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

INTVCC Peak Output Current ..................................50mA

Operating Junction Temperature Range (Notes 2, 3)

E-Grade, I-Grade ................................ –40°C to 125°C

H-Grade ............................................. –40°C to 150°C

MP-Grade .......................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MSE .................................................................. 300°C

LTC3851A-1

3851a1fa

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loops

VIN Input Operating Voltage Range 4 38 V

VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) 0°C to 85°C

ITH = 1.2V (Note 4) –40°C to 125°C

ITH = 1.2V (Note 4) –40°C to 150°C

ITH = 1.2V (Note 4) –55°C to 150°C

0.792

0.788

0.800 0.808

0.812

IFB Feedback Current (Note 4) –10 –50 nA

VREFLNREG Reference Voltage Line Regulation VIN = 6V to 38V (Note 4) 0.002 0.02 %/V

VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop,

∆ITH = 1.2V to 0.7V

(Note 4) Measured in Servo Loop,

∆ITH = 1.2V to 0.7V (H-Grade, MP-Grade)

0.01

0.1

0.2

(Note 4) Measured in Servo Loop,

∆ITH = 1.2V to 1.6V

(Note 4) Measured in Servo Loop,

∆ITH = 1.2V to 1.6V (H-Grade, MP-Grade)

–0.01

–0.1

–0.2

gmTransconductance Ampliﬁer gmITH = 1.2V, Sink/Source = 5µA (Note 4) 2 mmho

gm GBW Transconductance Amp Gain Bandwidth ITH = 1.2V (Note 8) 3 MHz

IQInput DC Supply Current

Normal Mode

Shutdown

(Note 5)

VRUN = 5V

VRUN = 0V

µA

UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down 3.25 V

UVLO Hys UVLO Hysteresis 0.4 V

ISENSE SENSE Pins Current ±1 ±2 µA

ITK/SS Soft-Start Charge Current VTK/SS = 0V 0.6 1 2 µA

VRUN RUN Pin On—Threshold VRUN Rising l1.10 1.22 1.35 V

VRUNHYS RUN Pin On—Hysteresis 120 mV

VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE = 3.3V

VFB = 0.7V, VSENSE = 3.3V (H-Grade, MP-Grade)

53 65

TG RUP TG Driver Pull-Up On-Resistance TG High 2.2 Ω

TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.2 Ω

BG RUP BG Driver Pull-Up On-Resistance BG High 2.1 Ω

BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.1 Ω

TG tr

TG tf

TG Transition Time

Rise Time

Fall Time

(Note 6)

CLOAD = 3300pF

BG tr

BG tf

BG Transition Time

Rise Time

Fall Time

(Note 6)

CLOAD = 3300pF

TG/BG t1D Top Gate Off to Bottom Gate On Delay

Bottom Switch-On Delay Time

CLOAD = 3300pF Each Driver

(Note 6)

30 ns

BG/TG t2D Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

CLOAD = 3300pF Each Driver

(Note 6)

30 ns

tON(MIN) Minimum On-Time (Note 7) 90 ns

INTVCC Linear Regulator

VINTVCC Internal VCC Voltage 6V < VIN < 38V 4.8 5 5.2 V

VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 %

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise noted.

LTC3851A-1

3851a1fa

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Oscillator and Phase-Locked Loop

fNOM Nominal Frequency RFREQ = 60k 460 500 540 kHz

fLOW Lowest Frequency RFREQ = 160k 205 235 265 kHz

fHIGH Highest Frequency RFREQ = 36k 690 750 810 kHz

RMODE/PLLIN MODE/PLLIN Input Resistance 100 kΩ

fMODE MODE/PLLIN Minimum Input Frequency

MODE/PLLIN Maximum Input Frequency

VMODE = External Clock

250

750

kHz

IFREQ Phase Detector Output Current

Sinking Capability

Sourcing Capability

fMODE > fOSC

fMODE < fOSC

–90

µA

PGOOD Output

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V

IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA

VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage

VFB Ramping Negative (UV)

VFB Ramping Positive (OV)

–12.5

7.5

–10

–7.5

12.5

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3851A-1 is tested under pulsed load conditions such that

TA ≈ TJ. The LTC3851AE-1 is guaranteed to meet performance

speciﬁcations from 0°C to 85°C junction temperature. Speciﬁcations over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3851AI-1 is guaranteed to meet speciﬁcations over the –40°C

to 125°C operating junction temperature range, the LTC3851AH-1 is

guaranteed over the –40°C to 150°C operating junction temperature range

and the LTC3851AMP-1 is tested and guaranteed over the –55°C to 150°C

operating junction temperature range. High junction temperatures degrade

operating lifetimes; operating lifetime is derated for junction temperatures

greater than 125°C. Note that the maximum ambient temperature

consistent with these speciﬁcations is determined by speciﬁc operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

Note 3: TJ is calculated from the ambient temperature TA and power

dissipation PD according to the following formulas:

LTC3851AMSE-1: TJ = TA + (PD • 40°C/W)

LTC3851AUD-1: TJ = TA + (PD • 68°C/W)

Note 4: The LTC3851A-1 is tested in a feedback loop that servos VITH to a

speciﬁed voltage and measures the resultant VFB.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels. Rise and fall times are assured by

design, characterization and correlation with statistical process controls.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ~40% of IMAX (see Minimum On-Time

Considerations in the Applications Information section).

Note 8: Guaranteed by design; not tested in production.

LTC3851A-1

3851a1fa

Typical perForMance characTerisTics

Load Step

(Burst Mode Operation)

Load Step

(Forced Continuous Mode)

Efﬁciency vs Output Current

and Mode

Efﬁciency vs Output Current

and Mode

Efﬁciency and Power Loss

vs Input Voltage

Efﬁciency vs Output Current

and Mode

ILOAD

5A/DIV

0.2A TO 7.5A

VOUT

100mV/DIV

AC-COUPLED

5A/DIV

100µs/DIVVOUT = 1.5V

VIN = 12V

FIGURE 11 CIRCUIT

3851A1 G05

ILOAD

5A/DIV

0.2A TO 7.5A

VOUT

100mV/DIV

AC-COUPLED

5A/DIV

100µs/DIVVOUT = 1.5V

VIN = 12V

FIGURE 11 CIRCUIT

3851A1 G06

LOAD CURRENT (mA)

EFFICIENCY (%)

100 1000 10000 100000

3851A1 G03

100

VIN = 12V

VOUT = 5V

BURST

CCM

PULSE

SKIP

INPUT VOLTAGE (V)

EFFICIENCY (%)

POWER LOSS (mW)

12 20 24 32

3851A1 G04

8 16 28

100

1000

10000

VIN = 12V

VOUT = 3.3V

FIGURE 11 CIRCUIT

POWER LOSS,

IOUT = 5A

POWER LOSS,

IOUT = 0.5A

EFFICIENCY,

IOUT = 0.5A

EFFICIENCY,

IOUT = 5A

LOAD CURRENT (mA)

EFFICIENCY(%)

100 1000 10000 100000

3851A1 G01

100 VIN = 12V

VOUT = 1.5V

BURST

CCM

PULSE

SKIP

LOAD CURRENT (mA)

EFFICIENCY(%)

100 1000 10000 100000

3851A1 G02

100

VIN = 12V

VOUT = 3.3V

FIGURE 11 CIRCUIT

BURST

CCM

PULSE

SKIP

LTC3851A-1

3851a1fa

Typical perForMance characTerisTics

Load Step

(Pulse-Skipping Mode) Inductor Current at Light Load

Start-Up with Prebiased Output

at 2V

Coincident Tracking with Master

Supply

Ratiometric Tracking with Master

Supply

Input DC Supply Current

vs Input Voltage

ILOAD

5A/DIV

0.2A TO 7.5A

VOUT

100mV/DIV

AC-COUPLED

5A/DIV

100µs/DIVVOUT = 1.5V

VIN = 12V

FIGURE 11 CIRCUIT

3851A1 G07

FORCED

CONTINOUS

MODE

5A/DIV

PULSE SKIP

MODE

5A/DIV

Burst Mode

OPERATION

5A/DIV

1µs/DIVVOUT = 1.5V

VIN = 12V

ILOAD = 1mA

FIGURE 11 CIRCUIT

3851A1 G08

VOUT

2V/DIV

VFB

0.5V/DIV

20ms/DIV 3851A1 G09

TK/SS

0.5V/DIV

10ms/DIV 3851A1 G10

VMASTER

0.5V/DIV VOUT

2A LOAD

0.5V/DIV

VMASTER

0.5V/DIV

VOUT

2A LOAD

0.5V/DIV

10ms/DIV 3851A1 G11

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

12 20 24 40

3851A1 G12

8 16 28 32 36

3.0

2.5

2.0

1.5

1.0

0.5

LTC3851A-1

3851a1fa

Typical perForMance characTerisTics

Maximum Current Sense Threshold

vs Common Mode Voltage

Maximum Peak Current Sense

Threshold vs ITH Voltage

Burst Mode Peak Current Sense

Threshold vs ITH Voltage

Maximum Current Sense

Threshold vs Duty Cycle

Regulated Feedback Voltage

vs Temperature

INTVCC Line Regulation

Shutdown (RUN) Threshold

vs Temperature

Maximum Current Sense

Threshold vs Feedback Voltage

(Current Foldback)

TK/SS Pull-Up Current

vs Temperature

TEMPERATURE (°C)

–75 –50

0.5

TK/SS CURRENT (µA)

0.6

0.8

0.9

1.0

1.5

1.2

050 75

3851A1 G19

0.7

1.3

1.4

1.1

–25 25 100 125 150

TEMPERATURE (°C)

–75 –50 –25

0.9

RUN PIN VOLTAGE (V)

1.1

1.4

050 75

3851A1 G20

1.0

1.3

1.2

25 100 150125

RUN RISING THRESHOLD (ON)

RUN FALLING THRESHOLD (OFF)

TEMPERATURE (°C)

–75 –50

REGULATED FEEDBACK VOLTAGE (mV)

802

804

806

25 75

3851A1 G21

800

798

–25 0 50 100 150125

796

794

INPUT VOLTAGE (V)

4 8 12

3.5

INTVCC VOLTAGE (V)

3.7

4.1

4.3

4.5

28 32 36

5.3

3851A1 G13

3.9

16 20 24 40

4.7

4.9

5.1 ILOAD = 0mA

ILOAD = 25mA

VSENSE COMMON MODE VOLTAGE (V)

VSENSE THRESHOLD (mV)

3 3.5 4 4.5

3851A1 G14

0.5 1 1.5 2 2.5 5

VITH (V)

0 0.2 0.4 0.6

VSENSE (mV)

0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

3851A1 G15

2.4

–10

–20

DUTY CYCLE RANGE: 0% TO 100%

VITH (V)

VSENSE (mV)

0.8 1.2 1.6 2.0

3851A1 G16

2.40.60.4 1.0 1.4 1.8 2.2

BURST COMPARATOR FALLING THESHOLD:

VITH = 0.4V

MAXIMUIM

MINIMUIM

DUTY CYCLE (%)

CURRENT SENSE THRESHOLD (mV)

40 80 100

3851A1 G17

20 60

FEEDBACK VOLTAGE (V)

MAXIMUM VSENSE (mV)

0.8

3851A1 G18

0.2 0.4 0.6

0.1 0.3 0.5 0.7

LTC3851A-1

3851a1fa

Oscillator Frequency

vs Temperature

Undervoltage Lockout Threshold

(INTVCC) vs Temperature

Oscillator Frequency

vs Input Voltage

Typical perForMance characTerisTics

Shutdown Input DC Supply

Current vs Input Voltage

Shutdown Input DC Supply

Current vs Temperature

Input DC Supply Current

vs Temperature

INPUT VOLTAGE (V)

SHUTDOWN SUPPLY CURRENT (µA)

3851A1 G25

010 20 30

515 25 35

Maximum Current Sense

Threshold vs INTVCC Voltage

INTVCC VOLTAGE(V)

3.2 3.4 3.6

CURRENT SENSE THRESHOLD (mV)

4.4 4.6 4.8

3851A1 G28

3.8 4.0 4.2 5.0

TEMPERATURE (°C)

–75 –50

600

700

900

25 75

3851A1 G22

500

400

–25 0 50 100 150125

300

200

800

FREQUENCY (kHz)

RPLLLPF = 36k

RPLLLPF = 60k

RPLLLPF = 160k

TEMPERATURE (°C)

–75 –50 –25

INTVCC VOLTAGE AT UVLO THRESHOLD (V)

050 75

3851A1 G24

25 100 150125

INTVCC RAMPING UP

INTVCC RAMPING DOWN

TEMPERATURE (°C)

–75 –50

SHUTDOWN INPUT DC SUPPLY CURRENT (µA)

3851A1 G26

–25 0 50

75 100 150125

TEMPERATURE (°C)

–75 –50

INPUT DC SUPPLY CURRENT (mA)

2.0

2.5

3.0

25 75

3851A1 G27

1.5

1.0

–25 0 50 100 150125

0.5

INPUT VOLTAGE (V)

FREQUENCY (kHz)

415

3851A1 G23

400

390

10 15 25

385

380

420

410

405

395

30 35 40

RFREQ = 80k

LTC3851A-1

3851a1fa

pin FuncTions

(MSE/UD)

MODE/PLLIN (Pin 1/Pin 15): Forced Continuous Mode,

Burst Mode or Pulse-Skipping Mode Selection Pin and

External Synchronization Input to Phase Detector Pin.

Connect this pin to INTVCC to force continuous conduction

mode of operation. Connect to GND to enable pulse-skip-

ping mode of operation. To select Burst Mode operation,

tie this pin to INTVCC through a resistor no less than 50k,

but no greater than 250k. A clock on the pin will force the

controller into forced continuous mode of operation and

synchronize the internal oscillator.

FREQ/PLLFLTR (Pin 2/Pin 16): The phase-locked loop’s

lowpass ﬁlter is tied to this pin. Alternatively, a resistor

can be connected between this pin and GND to vary the

frequency of the internal oscillator.

RUN (Pin 3/Pin 1): Run Control Input. A voltage above

1.22V on this pin turns on the IC. However, forcing this

pin below 1.1V causes the IC to shut down the IC. There

is a 2μA pull-up current on this pin.

TK/SS (Pin 4/Pin 2): Output Voltage Tracking and Soft-Start

Input. A capacitor to ground at this pin sets the ramp rate

for the output voltage. An internal soft-start current of of

1μA charges this capacitor.

ITH (Pin 5/Pin 3): Current Control Threshold and Error

Ampliﬁer Compensation Point. The current comparator

tripping threshold increases with its ITH control voltage.

FB (Pin 6/Pin 4): Error Ampliﬁer Feedback Input. This pin

receives the remotely sensed feedback voltage from an

external resistive divider across the output.

SENSE– (Pin 7/Pin 5): Current Sense Comparator Inverting

Input. The (–) input to the current comparator is connected

to the output.

SENSE+ (Pin 8/Pin 6): Current Sense Comparator Non-

inverting Input. The (+) input to the current comparator

is normally connected to the DCR sensing network or

current sensing resistor.

PGOOD (Pin 9/Pin 7): Power Good Indicator Output. Open-

drain logic out that is pulled to ground when the output

voltage exceeds the ±10% regulation window, after the

internal 17µs power bad mask timer expires.

GND (Pin 10/Pin 8, Exposed Pad Pin 17): Ground. All

small-signal components and compensation components

should be Kelvin connected to this ground. The (–) terminal

of CVCC and the (–) terminal of CIN should be closely con-

nected to this pin. The exposed pad should be soldered

to ground for good thermal conductivity.

BG (Pin 11/Pin 9): Bottom Gate Driver Output. This pin

drives the gate of the bottom N-channel MOSFET between

GND and INTVCC.

INTVCC (Pin 12/Pin 10): Internal 5V Regulator Output. The

control circuit is powered from this voltage. Decouple this

pin to GND with a minimum 2.2μF low ESR tantalum or

ceramic capacitor.

VIN (Pin 13/Pin 11): Main Input Supply. Decouple this pin

to GND with a capacitor.

BOOST (Pin 14/Pin 12): Boosted Floating Driver Supply.

The (+) terminal of the boost-strap capacitor is connected

to this pin. This pin swings from a diode voltage drop

below INTVCC up to VIN + INTVCC.

TG (Pin 15/Pin 13): Top Gate Driver Output. This is the

output of a ﬂoating driver with a voltage swing equal to

INTVCC superimposed on the switch node voltage.

SW (Pin 16/Pin 14): Switch Node Connection to the In-

ductor. Voltage swing at this pin is from a Schottky diode

(external) voltage drop below ground to VIN.

LTC3851A-1

3851a1fa

FuncTional DiagraM

–

–+

–

VIN

2µA

SLOPE COMPENSATION

UVLO

OSC S

RUN

SWITCH

LOGIC

AND

ANTI-

SHOOT

THROUGH

PULSE SKIP

0.8V

100k

1.22V0.64V

ITH

INTVCC

ITHB

ICMP

CC1

0.88V

RUN

GND

INTVCC

IREV

TG CB

VIN

CIN

VIN SLEEP

BOOST

BURSTEN

–

CVCC

VOUT

COUT

MODE/PLLIN

100k

SENSE+

SENSE–

–+

0.8V

REF

TK/SSRUN

0.4V

–+

VFB

FREQ/PLLFLTR

PLL-SYNC

5V REG

MODE/SYNC

DETECT

1µA

CSS

PGOOD

–+

0.72V

3851A1 FD

LTC3851A-1

3851a1fa

operaTion

Main Control Loop

The LTC3851A-1 is a constant frequency, current mode

step-down controller. During normal operation, the top

MOSFET is turned on when the clock sets the RS latch,

and is turned off when the main current comparator, ICMP

resets the RS latch. The peak inductor current at which

ICMP resets the RS latch is controlled by the voltage on

the ITH pin, which is the output of the error ampli ﬁer, EA.

The VFB pin receives the voltage feedback signal, which is

compared to the internal reference voltage by the EA. When

the load current increases, it causes a slight decrease in

VFB relative to the 0.8V reference, which in turn causes the

ITH voltage to increase until the average inductor current

matches the new load current. After the top MOSFET has

turned off, the bottom MOSFET is turned on until either

the inductor current starts to reverse, as indicated by the

reverse current comparator, IREV, or the beginning of the

next cycle.

INTVCC Power

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTVCC pin. An

internal 5V low dropout linear regulator supplies INTVCC

power from VIN.

The top MOSFET driver is biased from the ﬂoating boot-

strap capacitor, CB, which normally recharges during each

off cycle through an external diode when the top MOSFET

turns off. If the input voltage, VIN, decreases to a voltage

close to VOUT, the loop may enter dropout and attempt

to turn on the top MOSFET continuously. The dropout

detec tor detects this and forces the top MOSFET off for

about 1/10 of the clock period every tenth cycle to allow

CB to recharge. However, it is recommended that there is

always a load present during the drop-out transition to

ensure CB is recharged.

Shutdown and Start-Up (RUN and TK/SS)

The LTC3851A-1 can be shut down using the RUN pin.

Pulling this pin below 1.1V disables the controller and

most of the internal circuitry, including the INTVCC regula-

tor. Releasing the RUN pin allows an internal 2µA current

to pull up the pin and enable that controller. Alternatively,

the RUN pin may be externally pulled up or driven directly

by logic. Be careful not to exceed the absolute maximum

rating of 6V on this pin.

The start-up of the controller’s output voltage, VOUT

, is

controlled by the voltage on the TK/SS pin. When the

voltage on the TK/SS pin is less than the 0.8V internal

reference, the LTC3851A-1 regulates the VFB voltage to

the TK/SS pin voltage instead of the 0.8V reference. This

allows the TK/SS pin to be used to program a soft-start

by connecting an external capacitor from the TK/SS pin to

GND. An internal 1µA pull-up current charges this capacitor

creating a voltage ramp on the TK/SS pin. As the TK/SS

voltage rises linearly from 0V to 0.8V (and beyond), the

output voltage VOUT rises smoothly from zero to its ﬁnal

value. Alternatively, the TK/SS pin can be used to cause

the start-up of VOUT to track another supply. Typically,

this requires connecting to the TK/SS pin an external

resistor divider from the other supply to ground (see the

Applica tions Information section). When the RUN pin

is pulled low to disable the controller, or when INTVCC

drops below its undervoltage lockout threshold of 3.2V,

the TK/SS pin is pulled low by an internal MOSFET. When

in undervoltage lockout, the controller is disabled and the

external MOSFETs are held off.

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Continuous Conduction)

The LTC3851A-1 can be enabled to enter high efﬁciency

Burst Mode operation, constant frequency pulse-skipping

mode or forced continuous conduction mode. To select

forced continuous operation, tie the MODE/PLLIN pin to

INTVCC. To select pulse-skipping mode of operation, ﬂoat

the MODE/PLLIN pin or tie it to GND. To select Burst Mode

operation, tie MODE/PLLIN to INTVCC through a resistor

no less than 50k, but no greater than 250k.

When the controller is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-forth of the maximum sense voltage even though

the voltage on the ITH pin indicates a lower value. If the

average inductor current is higher than the load current,

the error ampliﬁer, EA, will decrease the voltage on the ITH

pin. When the ITH voltage drops below 0.4V, the internal

sleep signal goes high (enabling “sleep” mode) and both

external MOSFETs are turned off.

LTC3851A-1

3851a1fa

operaTion

In sleep mode, the load current is supplied by the output

capacitor. As the output voltage decreases, the EA’s output

begins to rise. When the output voltage drops enough, the

sleep signal goes low, and the controller resumes normal

operation by turning on the top external MOSFET on the

next cycle of the internal oscillator. When a controller is

enabled for Burst Mode operation, the inductor current is

not allowed to reverse. The reverse current comparator,

IREV, turns off the bottom external MOSFET just before the

inductor current reaches zero, preventing it from revers-

ing and going negative. Thus, the controller operates in

discontinuous operation. In forced continuous operation,

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as in

normal operation. In this mode the efﬁciency at light loads

is lower than in Burst Mode operation. However, continu-

ous mode has the advantages of lower output ripple and

less interference to audio circuitry.

When the MODE/PLLIN pin is connected to GND, the

LTC3851A-1 operates in PWM pulse-skipping mode at

light loads. At very light loads the current comparator,

ICMP

, may remain tripped for several cycles and force the

external top MOSFET to stay off for the same number of

cycles (i.e., skipping pulses). The inductor current is not

allowed to reverse (discontinuous operation). This mode,

like forced continuous operation, exhibits low output ripple

as well as low audio noise and reduced RF interference

as compared to Burst Mode operation. It provides higher

low current efﬁciency than forced continuous mode, but

not nearly as high as Burst Mode operation.

Frequency Selection and Phase-Locked Loop

(FREQ/PLLFLTR and MODE/PLLIN Pins)

The selection of switching frequency is a trade-off between

efﬁciency and component size. Low frequency operation

increases efﬁciency by reducing MOSFET switching losses,

but requires larger inductance and/or capacitance to main-

tain low output ripple voltage. The switching frequency of

the LTC3851A-1 can be selected using the FREQ/PLLFLTR

pin. If the MODE/PLLIN pin is not being driven by an ex-

ternal clock source, the FREQ/PLLFLTR pin can be used

to program the controller’s operating frequency from

250kHz to 750kHz.

A phase-locked loop (PLL) is available on the LTC3851A-1

to synchronize the internal oscillator to an external clock

source that is connected to the MODE/PLLIN pin. The

controller operates in forced continuous mode of operation

when it is synchronized. A series RC should be connected

between the FREQ/PLLFLTR pin and GND to serve as the

PLL’s loop ﬁlter.

It is suggested that the external clock be applied before

enabling the controller unless a second resistor is con-

nected in parallel with the series RC loop ﬁlter network.

The second resistor prevents low switching frequency

operation if the controller is enabled before the clock.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious con-

ditions that may overvoltage the output. In such cases,

the top MOSFET is turned off and the bottom MOSFET is

turned on until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD pin low when the VFB pin voltage is not within

±10% of the 0.8V reference voltage. The PGOOD pin is

also pulled low when the RUN pin is low (shut down) or

when the LTC3851A-1 is in the soft-start or tracking phase.

When the VFB pin voltage is within the ±10% requirement,

the MOSFET is turned off and the pin is allowed to be

pulled up by an external resistor to a source of up to 6V.

The PGOOD pin will ﬂag power good immediately when

the VFB pin is within the ±10% window. However, there is

an internal 17µs power bad mask when VFB goes out of

the ±10% window.

LTC3851A-1

3851a1fa

applicaTions inForMaTion

The Typical Application on the ﬁrst page of this data sheet

is a basic LTC3851A-1 application circuit. The LTC3851A-1

can be conﬁgured to use either DCR (inductor resistance)

sensing or low value resistor sensing. The choice of the

two current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resis tors and is more power efﬁcient,

especially in high current applications. However, current

sensing resistors provide the most accurate current limits

for the controller. Other external component selection

is driven by the load require ment, and begins with the

selection of RSENSE (if RSENSE is used) and the inductor

value. Next, the power MOSFETs and Schottky diodes are

selected. Finally, input and output capacitors are selected.

The circuit shown on the ﬁrst page can be conﬁgured for

operation up to 38V at VIN.

SENSE+ and SENSE– Pins

The SENSE+ and SENSE– pins are the inputs to the current

comparators. The common mode input voltage range of

the current comparators is 0V to 5.5V. Both SENSE pins

are high impedance inputs with small base currents of

less than 1μA. When the SENSE pins ramp up from 0V

to 1.4V, the small base currents ﬂow out of the SENSE

pins. When the SENSE pins ramp down from 5V to 1.1V,

the small base currents ﬂow into the SENSE pins. The

high impedance inputs to the current comparators allow

accurate DCR sensing. However, care must be taken not

to ﬂoat these pins during normal operation.

Low Value Resistors Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 1. RSENSE is chosen based on the required output

current.

The current comparator has a maximum threshold,

VMAX = 53mV. The current comparator threshold sets the

maximum peak of the inductor current, yielding a maximum

average output current, IMAX, equal to the peak value less

half the peak-to-peak ripple current, ∆IL. Allowing a margin

of 20% for variations in the IC and external component

values yields:

RSENSE =0.8 •

MAX

IMAX +∆IL/2

Inductor DCR Sensing

For applications requiring the highest possible efﬁciency,

the LTC3851A-1 is capable of sensing the voltage drop

across the inductor DCR, as shown in Figure 2. The

DCR of the inductor represents the small amount of

DC winding resis tance of the copper, which can be less

than 1mΩ for today’s low value, high current inductors.

If the external R1||R2 • C1 time constant is chosen to

be exactly equal to the L/DCR time constant, the voltage

drop across the external capacitor is equal to the voltage

drop across the inductor DCR multiplied by R2/(R1 + R2).

Therefore, R2 may be used to scale the voltage across the

sense terminals when the DCR is greater than the target

sense resistance. Check the manufacturer’s data sheet

for speciﬁcations regarding the inductor DCR, in order

to properly dimension the external ﬁlter components.

The DCR of the inductor can also be measured using a

good RLC meter.

Figure 1. Using a Resistor to Sense Current with the LTC3851A-1

VIN VIN

INTVCC

BOOST

GND

FILTER COMPONENTS

PLACED NEAR SENSE PINS

SENSE+

SENSE–

LTC3851A-1

VOUT

RSENSE

3851A1 F01

LTC3851A-1

3851a1fa

applicaTions inForMaTion

Figure 2. Current Mode Control Using the Inductor DCR

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant fre-

quency architectures by preventing sub-harmonic oscil-

lations at high duty cycles. It is accomplished inter nally

by adding a compensating ramp to the inductor current

signal. Normally, this results in a reduction of maximum

inductor peak cur rent for duty cycles >40%. However, the

LTC3851A-1 uses a novel scheme that allows the maximum

inductor peak current to remain unaffected throughout all

duty cycles.

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use of

smaller inductor and capacitor values. A higher frequency

generally results in lower efﬁciency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆IL decreases with higher

inductance or frequency and increases with higher VIN:

∆IL=1

f•LVOUT 1– VOUT

VIN

⎛

⎝

⎜⎞

⎠

⎟

Accepting larger values of ∆IL allows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ∆IL = 0.3(IMAX). The maximum

∆IL occurs at the maximum input voltage.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

≈10% of the current limit determined by RSENSE. Lower

inductor values (higher ∆IL) will cause this to occur at

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to increase.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

afford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite or molypermalloy

cores. Actual core loss is independent of core size for a

ﬁxed inductor value, but it is very dependent on inductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Power MOSFET and Schottky Diode (Optional)

Selection

Two external power MOSFETs must be selected for the

LTC3851A-1 controller: one N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

VIN VIN

INTVCC

BOOST

GND

INDUCTOR

DCRL

SENSE+

SENSE–

LTC3851A-1 VOUT

3851A1 F02

*PLACE C1 NEAR SENSE+, SENSE– PINS

C1*

R1||R2 • C1 =

RSENSE(EQ) = DCR

DCR

R1 + R2

LTC3851A-1

3851a1fa

The peak-to-peak drive levels are set by the INTVCC voltage.

This voltage is typically 5V during start-up. Consequently,

logic-level threshold MOSFETs must be used in most ap-

plications. The only exception is if low input voltage is ex-

pected (VIN < 5V); then, sub-logic level threshold MOSFETs

(VGS(TH) < 3V) should be used. Pay close attention to the

BVDSS speciﬁcation for the MOSFETs as well; most of the

logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, RDS(ON), Miller capacitance, CMILLER, input

voltage and maximum output current. Miller capacitance,

CMILLER, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. CMILLER is equal to the increase in gate charge

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in VDS. This result is

then multiplied by the ratio of the application applied VDS

to the gate charge curve speciﬁed VDS. When the IC is

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

Main Switch Duty Cycle = VOUT

VIN

Synchronous Switch Duty Cycle = V

IN – VOUT

The MOSFET power dissipations at maximum output

current are given by:

MAIN =VOUT

IMAX

( )

21+ δ

( )

RDS(ON) +

( )

2IMAX

⎛

⎝

⎜⎞

⎠

⎟RDR

( )

CMILLER

( )

•

INTVCC – VTH(MIN)

VTH(MIN)

⎡

⎣

⎢

⎤

⎦

⎥

⎥(f)

SYNC =V

IN – VOUT

IMAX

( )

21+ δ

( )

RDS(ON)

where δ is the temperature dependency of RDS(ON) and

RDR (approximately 2Ω) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. VTH(MIN) is the

typical MOSFET minimum threshold voltage.

Both MOSFETs have I2R losses while the topside N-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For VIN < 20V,

the high current efﬁciency generally improves with larger

MOSFETs, while for VIN > 20V, the transition losses rapidly

increase to the point that the use of a higher RDS(ON) device

with lower CMILLER actually provides higher efﬁciency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

The optional Schottky diode conducts during the dead time

between the conduction of the two power MOSFETs. This

prevents the body diode of the bottom MOSFET from turn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

in efﬁciency at high VIN. A 1A to 3A Schottky is generally

a good size due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

Soft-Start and Tracking

The LTC3851A-1 has the ability to either soft-start by itself

with a capacitor or track the output of another channel

or external supply. When the LTC3851A-1 is conﬁgured

to soft-start by itself, a capacitor should be connected to

the TK/SS pin. The LTC3851A-1 is in the shutdown state if

the RUN pin voltage is below 1.10V. TK/SS pin is actively

pulled to ground in this shutdown state.

Once the RUN pin voltage is above 1.22V, the LTC3851A-1

powers up. A soft-start current of 1μA then starts to charge

its soft-start capacitor. Note that soft-start or tracking is

achieved not by limiting the maximum output current of

the controller but by controlling the output ramp voltage

according to the ramp rate on the TK/SS pin. Current

foldback is disabled during this phase to ensure smooth

soft-start or tracking. The soft-start or tracking range is

applicaTions inForMaTion

LTC3851A-1

3851a1fa

0V to 0.8V on the TK/SS pin. The total soft-start time can

be calculated as:

tSOFT-START =0.8 •CSS

1.0µA

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator will always start in pulse-skipping mode up

to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it

will operate in forced continuous mode and revert to the

selected mode once TK/SS > 0.72V. The output ripple

is minimized during the 80mV forced continuous mode

window.

When the regulator is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated by a

resistor divider and applied to the TK/SS pin. Therefore, the

voltage ramp rate on this pin is determined by the ramp rate

of the other supply’s voltage. Note that the small soft-start

capacitor charging current is always ﬂowing, producing a

small offset error. To minimize this error, one can select

the tracking resistive divider value to be small enough to

make this error negligible.

In order to track down another supply after the soft-start

phase expires, the LTC3851A-1 must be conﬁgured for

forced continuous operation by connecting MODE/PLLIN

to INTVCC.

Output Voltage Tracking

The LTC3851A-1 allows the user to program how its

output ramps up and down by means of the TK/SS pins.

Through this pin, the output can be set up to either co-

incidentally or ratiometrically track with another supply’s

output, as shown in Figure 3. In the following discussions,

VMASTER refers to a master supply and VOUT refers to the

LTC3851A-1’s output as a slave supply. To implement the

coincident tracking in Figure 3a, connect a resistor divider

to VMASTER and connect its midpoint to the TK/SS pin of

the LTC3851A-1. The ratio of this divider should be selected

the same as that of the LTC3851A-1’s feedback divider as

shown in Figure 4a. In this tracking mode, VMASTER must

be higher than VOUT. To implement ratiometric tracking,

the ratio of the resistor divider connected to VMASTER is

determined by:

VOUT

VMASTER

=R2

R3 +R4

R1+R2

⎛

⎝

⎜⎞

⎠

⎟

So which mode should be programmed? While either

mode in Figure 4 satisﬁes most practical applications,

the coincident mode offers better output regulation.

This concept can be better understood with the help of

Figure 5. At the input stage of the LTC3851A-1’s error

ampliﬁer, two common anode diodes are used to clamp

applicaTions inForMaTion

Figure 3. Two Different Modes of Output Voltage Tracking

TIME

(3a) Coincident Tracking

VMASTER

VOUT

OUTPUT VOLTAGE

VMASTER

VOUT

TIME 3851A1 F03

(3b) Ratiometric Tracking

OUTPUT VOLTAGE

3851A13851A1

LTC3851A-1

3851a1fa

applicaTions inForMaTion

the equivalent reference voltage and an additional diode

is used to match the shifted common mode voltage. The

top two current sources are of the same amplitude. In the

coincident mode, the TK/SS voltage is substantially higher

than 0.8V at steady state and effectively turns off D1. D2

and D3 will therefore conduct the same current and offer

tight matching between VFB and the internal precision

0.8V reference. In the ratiometric mode, however, TK/SS

equals 0.8V at steady state. D1 will divert part of the bias

current to make VFB slightly lower than 0.8V.

Although this error is minimized by the exponential I-V

characteristic of the diode, it does impose a ﬁnite amount

of output voltage deviation. Furthermore, when the master

supply’s output experiences dynamic excursion (under

load transient, for example), the slave channel output will

be affected as well. For better output regulation, use the

coincident tracking mode instead of ratiometric.

INTVCC Regulator

The LTC3851A-1 features a PMOS low dropout linear

regula tor (LDO) that supplies power to INTVCC from the

VIN supply. INTVCC powers the gate drivers and much of

the LTC3851A-1 ’s internal circuitry. The LDO regulates

the voltage at the INTVCC pin to 5V.

The LDO can supply a peak current of 50mA and must

be bypassed to ground with a minimum of 2.2μF ceramic

capacitor or low ESR electrolytic capacitor. No matter

what type of bulk capaci tor is used, an additional 0.1μF

ceramic capacitor placed directly adjacent to the INTVCC

and GND pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3851A-1 to

be exceeded. The INTVCC current, which is dominated by

the gate charge current, is supplied by the 5V LDO.

Power dissipation for the IC in this case is highest and

is approximately equal to VIN • IINTVCC. The gate charge

current is dependent on operating frequency as discussed

in the Efﬁciency Considerations section. The junction tem-

perature can be estimated by using the equa tions given in

Note 3 of the Electrical Characteristics. For example, the

LTC3851A-1 INTVCC current is limited to less than 17mA

from a 36V supply in the GN package:

TJ = 70°C + (17mA)(36V)(90°C/W) = 125°C

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (MODE/PLLIN

= INTVCC) at maximum VIN.

Topside MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor, CB, connected to the

BOOST pin supplies the gate drive voltage for the topside

MOSFET. Capacitor CB in the Functional Diagram is charged

though external diode DB from INTVCC when the SW pin

Figure 4. Setup for Coincident and Ratiometric Tracking

Figure 5. Equivalent Input Circuit of Error Ampliﬁer

VOUT

(4a) Coincident Tracking Setup

VFB

VMASTER

TK/SS

R1 R3

VOUT

R4R2

3851A1 F04

(4b) Ratiometric Tracking Setup

VFB

TK/SS

VMASTER

–

I I

TK/SS

0.8V

VFB

3851A1 F05

LTC3851A-1

3851a1fa

applicaTions inForMaTion

is low. When the topside MOSFET is to be turned on, the

driver places the CB voltage across the gate source of the

MOSFET. This enhances the MOSFET and turns on the

topside switch. The switch node voltage, SW, rises to VIN

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply:

VBOOST = VIN + VINTVCC

The value of the boost capacitor, CB, needs to be 100 times

that of the total input capa citance of the topside MOSFET.

The reverse break down of the external Schottky diode

must be greater than VIN(MAX).

Undervoltage Lockout

The LTC3851A-1 has two functions that help protect the

controller in case of undervoltage conditions. A precision

UVLO comparator constantly monitors the INTVCC voltage

to ensure that an adequate gate-drive voltage is present.

It locks out the switching action when INTVCC is below

3.2V. To prevent oscillation when there is a disturbance

on the INTVCC, the UVLO comparator has 400mV of preci-

sion hysteresis.

Another way to detect an undervoltage condition is to moni-

tor the VIN supply. Because the RUN pin has a precision

turn-on reference of 1.22V, one can use a resistor divider

to VIN to turn on the IC when VIN is high enough.

CIN Selection

In continuous mode, the source current of the top N-chan-

nel MOSFET is a square wave of duty cycle VOUT/VIN. To

prevent large voltage transients, a low ESR input capacitor

sized for the maximum RMS current must be used. The

maximum RMS capacitor current is given by:

IRMS ≅IO(MAX)

VOUT

VIN

VOUT

– 1

⎛

⎝

⎜⎞

⎠

⎟

1/2

This formula has a maximum at VIN = 2VOUT, where IRMS =

IO(MAX)/2. This simple worst-case condition is com monly

used for design because even signiﬁcant deviations do not

offer much relief. Note that capacitor manufacturers’ ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

size or height requirements in the design. Always consult

the manufacturer if there is any question.

COUT Selection

The selection of COUT is primarily determined by the effec-

tive series resistance, ESR, to minimize voltage ripple. The

output ripple, ∆VOUT, in continuous mode is determined by:

∆VOUT ≈∆ILESR +1

8fCOUT

⎛

⎝

⎜⎞

⎠

⎟

where f = operating frequency, COUT = output capaci tance

and ∆IL = ripple current in the inductor. The output ripple

is highest at maximum input voltage since ∆IL increases

with input voltage. Typically, once the ESR requirement

for COUT has been met, the RMS current rating gener-

ally far exceeds the IRIPPLE(P-P) requirement. With ∆IL =

0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to

ESR, the output ripple will be less than 50mV at maximum

VIN and:

COUT Required ESR < 2.2RSENSE

COUT >1

8fRSENSE

The ﬁrst condition relates to the ripple current into the ESR

of the output capacitance while the second term guaran tees

that the output capacitance does not signiﬁcantly discharge

during the operating frequency period due to ripple current.

The choice of using smaller output capaci tance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

maintain the ripple voltage at or below 50mV. The ITH pin

OPTI-LOOP compensation compo nents can be optimized

to provide stable, high perfor mance transient response

regardless of the output capaci tors selected.

The selection of output capacitors for applications with

large load current transients is primarily determined by the

voltage tolerance speciﬁcations of the load. The resistive

component of the capacitor, ESR, multiplied by the load

current change, plus any output voltage ripple must be

within the voltage tolerance of the load.

LTC3851A-1

3851a1fa

applicaTions inForMaTion

The required ESR due to a load current step is:

RESR ≤∆V

∆I

where

∆

I is the change in current from full load to zero load

(or minimum load) and

∆

V is the allowed voltage devia-

tion (not including any droop due to ﬁnite capacitance).

The amount of capacitance needed is determined by the

maximum energy stored in the inductor. The capacitance

must be sufﬁcient to absorb the change in inductor

current when a high current to low current transition

occurs. The opposite load current transition is generally

determined by the control loop OPTI-LOOP components,

so make sure not to over compensate and slow down

the response. The minimum capacitance to assure the

inductors’ energy is adequately absorbed is:

COUT >L ∆I

( )

2 ∆V

( )

VOUT

where ∆I is the change in load current.

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

In surface mount applications, ESR, RMS current han dling

and load step speciﬁcations may require multiple capaci-

tors in parallel. Aluminum electrolytic, dry tantalum and

special polymer capacitors are available in surface mount

packages. Special polymer surface mount capaci tors offer

very low ESR but have much lower capacitive density per

unit volume than other capacitor types. These capacitors

offer a very cost-effective output capacitor solution and are

an ideal choice when combined with a controller having

high loop bandwidth. Tantalum capaci tors offer the highest

capacitance density and are often used as output capaci-

tors for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights rang ing from 1.5mm

to 4.1mm. Aluminum electrolytic capaci tors can be used

in cost-driven applications, provided that consideration is

given to ripple current ratings, tempera ture and long-term

reliability. A typical application will require several to many

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capaci tors will often result

in maximizing performance and minimizing overall cost.

Other capacitor types include Nichicon PL series, NEC

Neocap, Panasonic SP and Sprague 595D series. Consult

manufacturers for other speciﬁc recommendations.

Like all components, capacitors are not ideal. Each

ca pacitor has its own beneﬁts and limitations. Combina-

tions of different capacitor types have proven to be a very

cost effective solution. Remember also to include high

frequency decoupling capacitors. They should be placed

as close as possible to the power pins of the load. Any

inductance present in the circuit board traces negates

their usefulness.

Setting Output Voltage

The LTC3851A-1 output voltage is set by an external feed-

back resistive divider carefully placed across the output,

as shown in Figure 6. The regulated output volt age is

determined by:

VOUT =0.8V 1+RB

⎛

⎝

⎜⎞

⎠

⎟

To improve the transient response, a feed-forward

ca pacitor, CFF

, may be used. Great care should be taken

to route the VFB line away from noise sources, such as

the inductor or the SW line.

Figure 6. Settling Output Voltage

LTC3851A-1

VFB

VOUT

RBCFF

3851A1 F06

LTC3851A-1

3851a1fa

applicaTions inForMaTion

Fault Conditions: Current Limit and Current Foldback

The LTC3851A-1 includes current foldback to help limit

load current when the output is shorted to ground. If the

output falls below 40% of its nominal output level, the

maximum sense voltage is progressively lowered from

its maximum programmed value to about 25% of the

that value. Foldback current limiting is disabled during

soft-start or tracking. Under short-circuit conditions

with very low duty cycles, the LTC3851A-1 will begin

cycle skipping in order to limit the short-circuit current.

In this situation the bottom MOSFET will be dissipating

most of the power but less than in normal operation. The

short-circuit ripple current is determined by the minimum

on-time, tON(MIN), of the LTC3851A-1 (≈90ns), the input

voltage and inductor value:

∆IL(SC) =tON(MIN) •V

The resulting short-circuit current is:

ISC =

1/4MaxV

SENSE

RSENSE

–1

2∆IL(SC)

Programming Switching Frequency

To set the switching frequency of the LTC3851A-1, connect

a resistor, RFREQ, between FREQ/PLLFLTR and GND. The

relationship between the oscillator frequency and RFREQ

is shown in Figure 7. A 0.1µF bypass capacitor should be

connected in parallel with RFREQ.

Phase-Locked Loop and Frequency Synchronization

The LTC3851A-1 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. This phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the external

ﬁlter network connected to the FREQ/PLLFLTR pin. Note

that the LTC3851A-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3851A-1’s internal VCO.This is guaranteed to be be-

tween 250kHz and 750kHz. A simpliﬁed block diagram is

shown in Figure 8.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC , then current is sunk con-

tinuously from the phase detector output, pulling down the

FREQ/PLLFLTR pin. When the external clock frequency is

less than fOSC , current is sourced continuously, pulling up

the FREQ/PLLFLTR pin. If the external and internal frequen-

cies are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to the

phase difference. The voltage on the FREQ/PLLFLTR pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the ﬁlter capacitor CLP holds the voltage.

Figure 7. Relationship Between Oscillator Frequency

and Resistor Connected Between FREQ/PLLFLTR and GND Figure 8. Phase-Locked Loop Block Diagram

RFREQ (kΩ)

250

OSCILLATOR FREQUENCY (kHz)

300

400

450

500

750

600

60 100 120

3851A1 F07

350

650

700

550

40 80 140 160

DIGITAL

PHASE/

FREQUENCY

DETECTOR VCO

2.7V RLP

CLP

3851A1 F08

FREQ/PLLFLTR

EXTERNAL

OSCILLATOR

MODE/

PLLIN

LTC3851A-1

3851a1fa

applicaTions inForMaTion

The loop ﬁlter components, CLP and RLP

, smooth out

the current pulses from the phase detector and provide

a stable input to the voltage-controlled oscillator. The

ﬁlter components CLP and RLP determine how fast the

loop acquires lock. Typically RLP is 1k to 10k and CLP is

2200pF to 0.01μF.

When the external oscillator is active before the LTC3851

is enabled, the internal oscillator frequency will track the

external oscillator frequency as described in the preceding

paragraphs. In situations where the LTC3851 is enabled

before the external oscillator is active, a low free-running

oscillator frequency of approximately 50kHz will result. It is

possible to increase the free-running, pre-synchronization

frequency by adding a second resistor, RFREQ, in parallel

with RLP and CLP

. RFREQ will also cause a phase difference

between the internal and external oscillator signals. The

magnitude of the phase difference is inversely proportional

to the value RFREQ. The free-running frequency may be

programmed by using Figure 7 to determine the appropri-

ate value of RFREQ. In order to maintain adequate phase

margin for the PLL, the typical value for CLP is 0.01µF and

the typical value for RLP is 1k.

The external clock (on MODE/PLLIN pin) input high

threshold is nominally 1.6V, while the input low thres hold

is nominally 1.2V.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time dura-

tion that the LTC3851A-1 is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

tON(MIN) <VOUT

IN(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC3851A-1 is approximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a signiﬁcant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC3851A-1 circuits: 1) IC VIN current, 2)

INTVCC regulator current, 3) I2R losses, 4) topside MOSFET

transition losses.

1. The VIN current is the DC supply current given in the

Electrical Characteristics table, which excludes MOSFET

driver current. VIN current typi cally results in a small

(<0.1%) loss.

INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTVCC to ground. The resulting dQ/dt is a cur rent

out of INTVCC that is typically much larger than the

control circuit current. In continuous mode, IGATECHG

= f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.

3. I2R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor and current sense

resistor. In continuous mode, the average output current

ﬂows through L and RSENSE, but is chopped between

the topside MOSFET and the synchronous MOSFET.

LTC3851A-1

3851a1fa

applicaTions inForMaTion

If the two MOSFETs have approximately the same

RDS(ON), then the resistance of one MOSFET can simply

be summed with the resistances of L and RSENSE to

obtain I2R losses. For example, if each RDS(ON) = 10mΩ,

DCR = 10mΩ and RSENSE = 5mΩ, then the total resis-

tance is 25mΩ. This results in losses ranging from 2%

to 8% as the output current increases from 3A to 15A

for a 5V output, or a 3% to 12% loss for a 3.3V output.

Efﬁciency varies as the inverse square of VOUT for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f

Other hidden losses such as copper trace and the battery

internal resistance can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that CIN has ad-

equate charge storage and very low ESR at the switch ing

frequency. A 25W supply will typically require a minimum of

20μF to 40μF of capacitance having a maximum of 20mΩ

to 50mΩ of ESR. Other losses including Schottky con-

duction losses during dead time and inductor core losses

generally account for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ∆ILOAD (ESR), where ESR is the effective

series resistance of COUT. ∆ILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the ITH pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-ﬁltered closed-loop response test point. The DC step,

rise time and settling at this test point truly reﬂects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The ITH external components shown

in the Typical Application circuit will provide an adequate

starting point for most applications.

The ITH series RC-CC ﬁlter sets the dominant pole-zero

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without break ing

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the ITH pin signal which is in

the feedback loop and is the ﬁltered and compensated

control loop response. The midband gain of the loop will

be in creased by increasing RC and the bandwidth of the

loop will be increased by decreasing CC. If RC is increased

by the same factor that CC is decreased, the zero frequency

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

LTC3851A-1

3851a1fa

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • CLOAD. Thus a 10μF capacitor would

require a 250μs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3851A-1. These items are also illustrated graphically

in the layout diagram of Figure 9. Check the following in

your layout:

1. Are the board signal and power grounds segregated?

The LTC3851A-1 GND pin should tie to the ground plane

close to the input capacitor(s). The low current or signal

ground lines should make a single point tie directly to

the GND pin. The synchronous MOSFET source pins

should connect to the input capacitor(s) ground.

applicaTions inForMaTion

Figure 9. LTC3851A-1 Layout Diagram

MODE/PLLIN

FREQ/PLLFLTR

RUN

TK/SS

ITH

VFB

SENSE–

SENSE+

BOOST

VIN

INTVCC

GND

PGOOD

LTC3851A-1

47pF

CSS

0.1mF

CC2

RFREQ

RPGOOD

1000pF

COUT

RSENSE

4.7µF

VPULL-UP

CIN

–

VIN

VOUT

3851A1 F09

LTC3851A-1

3851a1fa

applicaTions inForMaTion

2. Does the VFB pin connect directly to the feedback resis-

tors? The resistive divider R1, R2 must be connected

between the (+) plate of COUT and signal ground. The

47pF to 100pF capacitor should be as close as possible

to the LTC3851A-1. Be careful locating the feedback

resistors too far away from the LTC3851A-1. The VFB

line should not be routed close to any other nodes with

high slew rates.

3. Are the SENSE– and SENSE+ leads routed together

with minimum PC trace spacing? The ﬁlter capacitor

between SENSE+ and SENSE– should be as close as

possible to the LTC3851A-1. Ensure accurate current

sensing with Kelvin connections as shown in Figure 10.

Series resistance can be added to the SENSE lines to

increase noise rejection and to compensate for the ESL

of RSENSE.

4. Does the (+) terminal of CIN connect to the drain of

the topside MOSFET(s) as closely as possible? This

capacitor provides the AC current to the MOSFET(s).

5. Is the INTVCC decoupling capacitor connected closely

between INTVCC and GND? This capacitor carries the

MOSFET driver peak currents. An addi tional 1μF ceramic

capacitor placed immediately next to the INTVCC and

GND pins can help improve noise performance.

6. Keep the switching node (SW), top gate node (TG) and

boost node (BOOST) away from sensitive small-signal

nodes, especially from the voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the “output side” (Pin 9 to Pin 16) of the LTC3851A-1

and occupy minimum PC trace area.

PC Board Layout Debugging

It is helpful to use a DC-50MHz current probe to monitor

the current in the inductor while testing the circuit. Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

output voltage as well. Check for proper performance over

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% of the maximum designed

cur rent level in Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well designed, low noise PCB imple mentation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pick-up at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

Reduce VIN from its nominal level to verify operation

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

for inductive coupling between CIN, the Schottky and the

top MOSFET to the sensitive current and voltage sens-

ing traces. In addition, investigate common ground path

voltage pickup between these components and the GND

pin of the IC.

Figure 10. Kelvin Sensing RSENSE

SENSE+SENSE–

HIGH CURRENT PATH

3851A1 F10

CURRENT SENSE

RESISTOR

(RSENSE)

LTC3851A-1

3851a1fa

Design Example

As a design example, assume VIN = 12V (nominal), VIN =

22V (maximum), VOUT = 1.8V, IMAX = 5A, and f = 250kHz

(refer to Figure 12).

The inductance value is chosen ﬁrst based on a 30%

ripple current assumption. The highest value of ripple

current occurs at the maximum input voltage. Connect a

160k resistor between the FREQ/PLLFLTR and GND pins,

generating 250kHz op eration. The minimum inductance

for 30% ripple current is:

∆IL=1

( )

VOUT 1−VOUT

VIN

⎛

⎝

⎜⎞

⎠

⎟

A 4.7µH inductor will produce 28% ripple current and

a 3.3µH will result in 40%. The peak inductor current

will be the maximum DC value plus one-half the ripple

current, or 6A, for the 3.3µH value. Increasing the ripple

current will also help ensure that the minimum on-time

of 90ns is not violated. The minimum on-time occurs at

maximum VIN:

tON(MIN) =

OUT

VIN(MAX) f

( )

1.8V

22V 250kHz

( )

=327ns

The RSENSE resistor value can be calculated by using the

maximum current sense voltage speciﬁcation with some

accommodation for tolerances.

RSENSE ≤50mV

=0.0083Ω

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

applicaTions inForMaTion

The power dissipation on the topside MOSFET can be easily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.

At maximum input voltage with T (estimated) = 50°C:

MAIN =1.8V

22V 5

( )

21+0.005

( )

50°C−25°C

( )

⎡

⎣⎤

⎦•

0.035Ω

( )

+22V

( )

25A

⎛

⎝

⎜⎞

⎠

⎟2Ω

( )

215pF

( )

•

5−2.3 +1

2.3

⎡

⎣

⎢⎤

⎦

⎥250kHz

( )

=185mW

A short-circuit to ground will result in a folded back cur-

rent of:

ISC =29mV

0.0125Ω–1

90ns 22V

( )

3.3µH

⎛

⎝

⎜⎞

⎠

⎟=2.02A

with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

SYNC =

22V

2.02A

( )

21.125

( )

0.022Ω

( )

=101.0mW

which is less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 3A at

temperature. COUT is chosen with an ESR of 0.02Ω for

low output ripple. The output ripple in continuous mode

will be highest at the maximum input voltage. The output

voltage ripple due to ESR is approximately:

VORIPPLE = RESR (∆IL) = 0.02Ω (2A) = 40mVP-P

LTC3851A-1

3851a1fa

Typical applicaTions

Figure 12. 1.8V/5A Converter from Design Example with Pulse Skip Operation

Figure 11. High Efﬁciency 3.3V/15A Step-Down Converter

MODE/PLLIN

FREQ/PLLFLTR

RUN

TK/SS

ITH

VFB

SENSE–

SENSE+

VIN

BOOST

INTVCC

GND

PGOOD

LTC3851A-1

CSS

0.1µF

0.047µF

0.1µF

CC2

330pF

2200pF

RFREQ

82.5k

15k

30.1k

VOUT

3.3V

15A

C15

47pF

4.7µF

VPULL-UP

+COUT

330µF

×2

CIN

22µF

HAT2170H

COUT: SANYO 6TPE330MIL

CIN: SANYO 63HVH22M

L1: VISHAY IHLP5050-EZERR68M01

3851A1 F11

CMDSH05-4 R2

154k

48.7k

VIN

4.5V TO 32V

0.68µH

R27

3.01k

RPG

C20

0.1µF

MODE/PLLIN

FREQ/PLLFLTR

RUN

TK/SS

ITH

VFB

SENSE–

SENSE+

VIN

BOOST

INTVCC

GND

PGOOD

LTC3851A-1

CSS

0.1µF

CC2

220pF

470pF

0.1µF

RFREQ

160k

RPG

33k

RSENSE

0.01Ω VOUT

1.8V

1000pF

4.7µF

VPULL-UP

+COUT

150µF

6.3V

×2

PANASONIC SP

CIN

22µF

25V

FDS6982S

COUT: PANASONIC EEFUEOG151R

CIN: MARCON THCR70LE1H226ZT

L1: PANASONIC ETQP6F3R3HFA

RSENSE: IRC LR 2010-01-R010F

3851A1 F12

CMDSH-3

32.4k

25.5k

VIN

4.5V TO 22V

3.3µH

LTC3851A-1

3851a1fa

UD Package

16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1691)

package DescripTion

3.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 × 45° CHAMFER

15 16

0.50 BSC

0.200 REF

0.00 – 0.05

(UD16) QFN 0904

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.45 ± 0.05

(4 SIDES)

2.10 ± 0.05

3.50 ± 0.05

0.70 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE

OUTLINE

LTC3851A-1

3851a1fa

package DescripTion

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev C)

MSOP (MSE16) 0910 REV C

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1615 1413 1211 10

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

0.50

(.0197)

BSC

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ± 0.102

(.112 ± .004)

2.845 ± 0.102

(.112 ± .004)

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

1.651 ± 0.102

(.065 ± .004)

1.651 ± 0.102

(.065 ± .004)

0.1016 ± 0.0508

(.004 ± .002)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.280 ± 0.076

(.011 ± .003)

REF

4.90 ± 0.152

(.193 ± .006)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.12 REF

0.35

REF

LTC3851A-1

3851a1fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 5/11 Added H-Grade and MP-Grade parts. Reﬂected througout the data sheet. 1-30

LTC3851A-1

3851a1fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0511 REV A • PRINTED IN USA

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down

DC/DC Controller

Fixed 400kHz Operating Frequency, 4.5V≤ VIN ≤ 38V,

0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12

LTC3878 No RSENSE™ Constant On-Time Synchronous Step-Down

DC/DC Controller

Very Fast Transient Response, tON(MIN) = 43ns, 4V≤ VIN ≤ 38V,

0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16

LTC3879 No RSENSE Constant On-Time Synchronous Step-Down

DC/DC Controller

Very Fast Transient Response, tON(MIN) = 43ns, 4V≤ VIN ≤ 38V,

0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16

LTC3850/LTC3850-1

LTC3850-2

Dual 2-Phase, High Efﬁciency Synchronous Step-Down

DC/DC Controllers, RSENSE or DCR Current Sensing and

Tracking

Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,

4V≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V

LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC

Controller, RSENSE or DCR Current Sensing and Tracking

Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,

4V≤ VIN ≤ 24V, VOUT Up to 13.5V

LTC3834/LTC3834-1 Low IQ, Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,

4V≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, IQ = 30µA,

3845A Low IQ , High Voltage Synchronous Step-Down DC/DC

Controller

Adjustable Fixed Operating Frequency 100kHz to 500kHz,

4V≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, IQ = 30µA, TSSOP-16

LTC3775 High Frequency Synchronous Voltage Mode Step-Down

DC/DC Controller

Synchronizable Fixed Frequency 250kHz to 1MHz, tON(MIN) = 30ns,

4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm

QFN-16

Typical applicaTion

1.5V/15A Synchronized at 350kHz

MODE/PLLIN

FREQ/PLLFLTR

RUN

TK/SS

ITH

VFB

SENSE–

SENSE+

VIN

BOOST

INTVCC

GND

PGOOD

LTC3851A-1

CSS

0.1µF

1000pF

0.1µF

CC2

100pF

1000pF

0.01µF

PLLIN

350kHz

7.5k

R22 10Ω

R20 10Ω

RSENSE

0.002Ω VOUT

1.5V

15A

1000pF RPG

VPULL-UP

+COUT

330µF

×2

CIN

180µF

RJK0305DPB

RJK0301DPB

COUT: SANYO 2R5TPE330M9

L1: SUMIDA CEP125-OR6MC

3851A1 TA03

CMDSH-3

4.7µF

43.2k

20k

VIN

6V TO 14V

0.68µH

C10

33pF