HY5DU28822
4 Banks x 4M x 8Bit Double Data Rate SDRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.1.2/Mar.00
DESCRIPTION
The Hyundai HY5DU28822 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited
for the main memory applications which require large memory density and high bandwidth. HY5DU28822 is organized
as 4 banks of 4,194,304x8.
HY5DU28822 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all
addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data
strobes(DQS) and Write data masks(DM) inputs are sampled on both rising and falling edges of it. The data paths are
internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compat-
ible with SSTL_2.
Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or
interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled
through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved
than that of traditional (single data rate) Synchronous DRAM.
FEATURES
•2.5V VDD and VDDQ power suppliy
•All inputs and outputs are compatible with SSTL_2
interface
•JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
•Fully differential clock operations(CLK & CLK) with
100MHz/125MHz/133MHz
•All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•Data(DQ) and Write masks(DM) latched on both ris-
ing and falling edges of the Data Stobe
•Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•Delay Locked Loop(DLL) installed with DLL reset
mode
•Write mask byte controlled by DM
•Programmable CAS Latency 2 and 2.5 supported
•Write Operations with 1 Clock Write Latency
•/QFC & Half Strength Driver controlled by EMRS
•Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•Internal four bank operations with single pulsed RAS
•Auto refresh and self refresh supported
•4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No. Power Suppy Clock Frequency Organization Interface Package
HY5DU28822(L)T-K VDD=2.5V
VDDQ=2.5V
143MHz (*PC266A) 4Banks
x 4Mbit x 8 SSTL_2 400mil 66pin
TSOP II
HY5DU28822(L)T-H 133MHz (*PC266B)
HY5DU28822(L)T-L 125MHz (*PC200)
PRELIMINARY
* JEDEC Defined Specifications compliant* (L) Low Power Part
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HY5DU28822
Rev.1.2/Mar.00 2
400mil X 875mil
66 Pin TSOP-II
0.65mm Pin Pitch
TOP VIEW
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
/QFC, NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN CONFIGURATION
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK, CLK Differential Clock Input The system clock input. All of the inputs are latched on the rising edges of the
clock except DQi, DQS and DM that are sampled on the both.
CKE Clock Enable Controls internal clock signal and when deactivated, the DDR SDRAM will be
one of the states among power down, suspend or self refresh.
CS Chip Select Enables or disables all inputs except CLK/CLK, CKE, DQS and DM.
BA0, BA1 Bank Select Address Selects bank to be activated during either RAS or CAS activity.
Selects bank to be read/written during either RAS or CAS activity.
A0 ~ A11 Address Row Address : A0 ~ A11, Column Address : A0 ~ A9, AP Flag : A10
RAS, CAS, WE Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operations.
Refer function truth table for details.
DM Write Mask Masks input data in write mode.
DQS Data Input/Output Strobe Active on the both edges for Data Input and Output.
DQ0 ~ DQ7 Data Input/Output Multiplexed data input / output pin.
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers for Noise immunity.
VREF Reference Voltage Reference voltage for inputs for SSTL interface.
/QFC (optional) DQ FET Switch Control Controls FET Switches on DQs used for reduction of Impedance.
NC No Connection No connection.
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HY5DU28822
Rev.1.2/Mar.00 3
FUNCTIONAL BLOCK DIAGRAM
4banks x 4Mbit x 8 I/O Double data rate Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability.
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 oC
Storage Temperature TSTG -55 ~ 125 oC
Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V
Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V
Output Short Circuit Current IOS 50 mA
Power Dissipation PD1W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 oC ⋅ Sec
Command
Decoder
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
DM
Address
Buffer
ADD
Bank
Control 4Mx8/Bank0
Column Decoder
Column Address
Counter
Sense AMP
2-bit Prefetch Unit
4Mx8/Bank1
4Mx8/Bank2
4Mx8/Bank3
Mode
Register Row
Decoder
Input Buffer Output Buffer
DLL
Block
Mode
Register
Data Strobe
Transmitter
Data Strobe
Receiver
DQS
CLK
DS
Write Data Register
2-bit Prefetch Unit DS
DQ[0:7]
16 8
8
16
CLK_DLL
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HY5DU28822
Rev.1.2/Mar.00 4
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD 2.3 2.5 2.7 V
Power Supply Voltage VDDQ 2.3 2.5 2.7 V1
Input High Voltage VIH VREF + 0.15 -VDDQ + 0.3 V
Input Low Voltage VIL -0.3 -VREF - 0.15 V2
Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V
Reference Voltage VREF 1.15 1.25 1.35 V3
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V1
Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V2
Parameter Value Unit
Reference Voltage VDDQ x 0.5 V
Termination Voltage VDDQ x 0.5 V
AC Input High Level Voltage (VIH, min) VREF + 0.31 V
AC Input Low Level Voltage (VIL, max) VREF - 0.31 V
Input Timing Measurement Reference Level Voltage VREF V
Output Timing Measurement Reference Level Voltage VTT V
Input Signal maximum peak swing 1.5 V
Input minimum Signal Slew Rate 1V/ns
Termination Resistor (RT)50 Ω
Series Resistor (RS)25 Ω
Output Load Capacitance for Access Time Measurement (CL)30 pF
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HY5DU28822
Rev.1.2/Mar.00 5
CAPACITANCE (TA=25oC, f=100MHz )
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Parameter Pin Symbol Min Max Unit
Input Capacitance A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE CIN 2.0 3.0 pF
Clock Capacitance CLK, CLK CCLK 2.0 3.0 pF
Data Input / Output Capacitance DQ0 ~ DQ7, DQS, DM CIO 4.0 5.0 pF
VREF
VTT VTT
RT=50ΩRT=50Ω
RS=25ΩZo=50Ω
CL=30pF
Output
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HY5DU28822
Rev.1.2/Mar.00 6
DC CHARACTERISTICS I (TA=0 to 70°C, Voltage referenced to VSS = 0V)
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 2.7V
DC CHARACTERISTICS II (TA=0 to 70°C, Voltage referenced to VSS = 0V)
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC Characteristics.
3. HY5DU28822T
4. HY5DU28822LT, Self refresh low power
Parameter Symbol Min. Max Unit Note
Input Leakage Current ILI -5 5uA 1
Output Leakage Current ILO -5 5uA 2
Output High Voltage VOH VTT + 0.76 -VIOH = -15.2mA
Output Low Voltage VOL -VTT - 0.76 VIOL = +15.2mA
Parameter Symbol Test Condition Speed Unit Note
-K -H -L
Operating Current IDD1 Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA 150 140 130 mA 1
Precharge Standby Current in
Power Down Mode IDD2P CKE ≤ VIL(max), tCK = min 20 mA
Precharge Standby Current in
Non Power Down Mode IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during 2clks 40 mA
Active Standby Current in
Power Down Mode IDD3P CKE ≤ VIL(max), tCK = min 25 mA
Active Standby Current in Non
Power Down Mode IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during 2clks 50 mA
Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active
CL=2.5 270 260 250 mA 1
CL=2 230 210 190
Auto Refresh Current IDD5 tRC ≥ tRFC(min), All banks active 320 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V 2mA 3
TBD mA 4
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HY5DU28822
Rev.1.2/Mar.00 7
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol -K(PC266A) -H(PC266B) -L(PC200) Unit Note
Min Max Min Max Min Max
Row Cycle Time tRC 65 -65 -70 -ns
Auto Refresh Row Cycle Time tRFC 75 -75 -80 -ns
Row Active Time tRAS 45 120K 48 120K 50 120K ns
Row Address to Column Address Delay tRCD 20 -20 -20 -ns
Row Active to Row Active Delay tRRD 15 -15 -15 -ns
Column Address to Column Address Delay tCCD 1-1-1-CLK
Row Precharge Time tRP 20 -20 -20 -ns
Write Recovery Time tWR 15 -15 -15 -ns
Last Data-In to Read Command tDRL 1-1-1-CLK
Auto Precharge Write Recovery + Precharge Time tDAL 35 -35 -35 -ns
System Clock Cycle Time CAS Latency = 2.5 tCK 715 7.5 15 815 ns
CAS Latency = 2 7.5 15 10 15 10 15 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CLK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CLK
Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns
DQS-Out edge to Data-Out edge Skew tDQSQ -0.5 -0.5 -0.6 ns
Data-Out hold time from DQS tQH tHPmin
-0.75ns -tHPmin
-0.75ns -tHPmin
-0.75ns -ns 1
Clock Half Period tHP tCH/L
min -tCH/L
min -tCH/L
min -ns 1
Input Setup Time (fast slew rate) tIS 0.9 -0.9 -1.0 -ns 2,3,5,6
Input Hold Time (fast slew rate) tIH 0.9 -0.9 -1.0 -ns 2,3,5,6
Input Setup Time (slow slew rate) tIS 1.1 -1.1 -1.1 -ns 2,4,5,6
Input Hold Time (slow slew rate) tIH 1.1 -1.1 -1.1 -ns 2,4,5,6
Input Pulse Width tIPW 2.2 2.2 -6
Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK
CLK to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK
Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 -0.5 -0.6 -ns 7
Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 -0.5 -0.6 -ns 7
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HY5DU28822
Rev.1.2/Mar.00 8
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) - continued -
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self
Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
WRITE MASK TRUTH TABLE
Note :
1. Write Mask command masks burst write data with reference to DQS(Data Strobes) and it is not related with read data.
Parameter Symbol -K(PC266A) -H(PC266B) -L(PC200) Unit Note
Min Max Min Max Min Max
DQ & DM Input Pulse Width tDIPW 1.75 -1.75 -2-ns
Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CLK
Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Write DQS Preamble Setup Time tWPRES 0-0- -0-CLK
Write DQS Preamble Hold Time tWPREH 0.25 -0.25 -0.25 -CLK
Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK
Mode Register Set Delay tMRD 2-2-2-CLK
Power Down Exit Time tPDEX 10 -10 -10 -ns
Exit Self Refresh to Non-Read Command tXSNR 75 -75 -80 -ns
Exit Self Refresh to Read Cimmand tXSRD 200 -200 -200 -CLK 8
Average Periodic Refresh Interval tREFI -15.6 -15.6 -15.6 us
Function CKEn-1 CKEn CS, RAS, CAS, WE DM ADDR A10/
AP BA Note
Data Write HX X LX1
Data-In Mask HX X HX1
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HY5DU28822
Rev.1.2/Mar.00 9
SIMPLIFIED COMMAND TRUTH TABLE
Note :
1. DM states are “Don’t Care”. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no command presented
to activated bank until CLK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CLK(n), then there will be no command presented
to activated bank until CLK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is “High” when Row Precharge command being issued, BA 0/BA1 are ignored and all banks are selected to be
precharged.
Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/
AP BA Note
Extended Mode Register Set HXL L L L OP code 1,2
Mode Register Set HXL L L L OP code 1,2
Device Deselect HXHX X X X1
No Operation LHHH
Bank Active HXL L H H RA V1
Read HXLHLHCA LV1
Read with Autoprecharge H1,3
Write HXLHL L CA LV1
Write with Autoprecharge H1,4
Precharge All Banks HXL L HLXHX1,5
Precharge selected Bank LV1
Read Burst Stop HXLH H LX1
Auto Refresh H H L L L H X1
Self Refresh
Entry HL L L L H
X
1
Exit LHHX X X 1
LHHH
Precharge
Power Down
Mode
Entry HLHX X X
X
1
LHHH 1
Exit LHHX X X 1
LHHH 1
Active Power
Down Mode
Entry HLHX X X
X
1
LV V V 1
Exit LHX1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
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HY5DU28822
Rev.1.2/Mar.00 10
10.26 (0.404)
10.05 (0.396)
11.94 (0.470)
11.79 (0.462)
22.33 (0.879)
22.12 (0.871)
1.194 (0.0470)
0.991 (0.0390)
0.65 (0.0256) BSC 0.35 (0.0138)
0.25 (0.0098)
0.15 (0.0059)
0.05 (0.0020)
BASE PLANE
SEATING PLANE
0.597 (0.0235)
0.406 (0.0160) 0.210 (0.0083)
0.120 (0.0047)
0 ~ 5 Deg.
Unit : mm(Inch)
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
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