L9390 Twelve channel valve driver Data Brief Features Four low side switched output drivers with 0.1 Rds,ON at 25C Possibly configurable as PWM controlled adding external freewheeling diodes Two low side PWM controlled output drivers with 0.1 Rds,ON at 25C and integrated active freewheeling diodes Six low side current controlled output drivers with 0.16 Rds,ON at 25C and integrated active freewheeling diodes TQFP100 (Exposed pad down) Current accuracy: - 10% (Iload < 800mA) - 6% (Iload > 800mA) All outputs with integrated 35V zener clamp Five pin SPI port (four standard pins plus additional SPI enable input pin) Six serial high speed input for output control High level diagnostic, including Silent Valve Driver Test Direct disable of outputs with an external pin Programmable jitter frequency of PWM and current controlled outputs TQFP100 exposed pad package active freewheeling diodes for active rectification of the PWM controlled load. In order to minimize electromagnetic emissions during load actuation, the possibility to control output slopes is provided. Two separate communication interfaces are present: the SPI port is primarily designated to provide diagnostics and secondary control. The serial High End Timer Interface (HET) provides the primary output control functions from on/off switching to current level control commands. Diagnostic includes over current protection, under current detection, open load detection, loss of ground detection, loss of freewheeling diode, and over temperature detection, output integrity check, SVDT, leakage current test, PWM integrity and functionality check, valve resistance sense check, loss of freewheeling diode detection and more. Description The L9390 is a twelve output low side valve driver designed for use in an ABS/ESP vehicle system. All outputs are PWM configurable, while six out of twelve are current regulated. Each of the twelve outputs is open drain configured and has a built-in 35V clamp. Eight of the twelve have integrated Table 1. Power supply monitoring is also included. Device summary Part number Package Packing L9390 TQFP100 14x14x1.0mm (exposed pad down) Tray September 2013 Rev 2 For further information contact your local STMicroelectronics sales office. 1/8 www.st.com 8 Table 2. 83 D9 84 D9 85 D9 86 N.C. 87 OUT4 88 PGND4_8 89 OUT4 90 PGND4_8 91 PGND4_8 92 PGND4_8 93 82 81 80 79 78 77 76 OUT2 1 75 OUT9 OUT2 2 74 OUT9 OUT2 3 73 OUT9 N.C. 4 72 OUT9 PGND2_6 5 71 PGND9 PGND2_6 6 70 PGND9 PGND2_6 7 69 PGND9 PGND2_6 8 68 PGND9 PGND2_6 9 67 OUT11 OUT6 10 66 OUT11 OUT6 11 65 D11 D6 12 64 D11 PGND10_12 OUT5 22 54 OUT12 D5 23 53 OUT12 D5 24 52 D12 N.C. 25 51 D12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 N.C. 55 BUSY 21 MOSI PGND10_12 OUT5 CLK 56 MISO 20 CS PGND10_12 PGND1_5 CLKin 57 N.C. 19 N.C. PGND10_12 PGND1_5 AGND 58 DGND 18 OUT_EN PGND10_12 PGND1_5 VRS_Meas 59 LOGI 17 V3 OUT10 PGND1_5 HET1-6 60 HET1-6 16 HET1-6 OUT10 PGND1_5 HET1-6 61 HET1-6 15 HET1-6 D10 OUT1 N.C. D10 62 VCP 63 14 VS 13 N.C. D6 OUT1 AC00078 Pins description Pin # Name 1-3 OUT2 4 N.C. 5-9 PGND2_6 10-11 OUT6 12-13 D6 14-15 OUT1 16-20 PGND1_5 21-22 OUT5 23-24 D5 25-26 N.C. 27 Vs 2/8 D8 94 D8 95 OUT3 96 OUT3 97 PGND3_7 PGND3_7 98 PGND3_7 PGND3_7 100 99 N.C. OUT7 Pin connection (top view) OUT7 Figure 1. D7 Pin description D7 1 OUT8 L9390 OUT8 Pin description Description Valve Low Side Driver output, Switched or PWMmed Not Connected Dedicated Output Power Ground Valve Low Side Driver output, PWMmed or Current Regulated Freewheeling Diode Cathode Valve Low Side Driver output, Switched or PWMmed Dedicated Output Power Ground Valve Low Side Driver output, PWMmed or Current Regulated Freewheeling Diode Cathode Not Connected Battery level Supply input voltage L9390 Table 2. Pin description Pins description (continued) Pin # Name Description 28 VCP Charge Pump voltage input 29 N.C. Not Connected 30-35 HET1-6 Serial High End Timer inputs 36 V3 37 LOGI 3.3V supply input 38 VRS_Meas 39 OUT_EN 40 DGND Circuit ground 41 AGND Signal Ground 42-43 N.C. Not Connected 44 CLKin Logic Supply Input, must be tied to V3 Switch connection to pin D5 for the purpose of diagnosing specific load resistances. Enables/ disables all outputs asynchronous to any other commands Clock input for IC 45 CS SPI Chip Select input 46 CLK SPI Clock input 47 MISO SPI Master in Slave out 48 MOSI SPI Master out Slave in 49 BUSY 50 N.C. Not Connected 51-52 D12 Freewheeling Diode Cathode 53-54 OUT12 55-59 PGND10_12 60-61 OUT10 62-63 D10 Freewheeling Diode Cathode 64-65 D11 Freewheeling Diode Cathode SPI Enable input Valve Low Side Driver output, Current Regulated Dedicated Output Power Ground Valve Low Side Driver output, Current Regulated 66-67 OUT11 Valve Low Side Driver output, PWMmed 68-71 PGND9 Dedicated Output Power Ground 72-75 OUT9 76-78 D9 79 N.C. 80-81 OUT4 82-85 PGND4_8 86-87 OUT8 88-89 D8 90-91 OUT3 92-95 PGND3_7 96-97 OUT7 98-99 D7 100 N.C. Valve Low Side Driver output, PWMmed Freewheeling Diode Cathode Not Connected Valve Low Side Driver output, Switched or PWMmed Dedicated Output Power Ground Valve Low Side Driver output, PWMmed or Current Regulated Freewheeling Diode Cathode Valve Low Side Driver output, Switched or PWMmed Dedicated Output Power Ground Valve Low Side Driver output, PWMmed or Current Regulated Freewheeling Diode Cathode Not Connected 3/8 Block diagram 2 L9390 Block diagram Figure 2. Block diagram VCP Vs V3 Logic R LIMIT Power Supply From D5 Valve Driver Control Ckt PWM/Switch Control & Diagnostics Monitoring UV, OV SWITCH/PWM VRS Switch VRS_Meas Output Stage x4 Drivers V3 CS CLKin CLKin Monitor OUT_EN HET1 HET2 HET3 HET4 HET5 HET6 Serial Valve Driver Control Ckt Current Control Control & Diagnostics PGND3_7 OUT2 PGND2_6 OUT1 PGND1_5 OUT8 PGND4_8 D7 OUT7 PGND3_7 D6 OUT6 PGND2_6 D5 OUT5 PGND1_5 High End Valve Driver Control Ckt Timer Current Control Interface SWITCH/PWM BUSY Output Stage w/Diodes x4 Drivers MISO Port Control & Diagnostics SWITCH/PWM Output Stage w/Diodes x2 Drivers MOSI PGND4_8 OUT3 D8 SPI CONTROL CIRCUIT Data and Comand Registers CLK OUT4 D12 OUT12 PGND10_12 D11 OUT9_11 DGND Valve Driver Control Ckt AGND PWM/Control & Diagnostics SWITCH/PWM Output Stage w/Diodes x2 Drivers PGND11 D10 OUT10 PGND10_12 D9 OUT9 PGND9_11 AC00079 4/8 L9390 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Warning: Table 3. The absolute maximum ratings are the values at which if exceeded the device may become damaged. Absolute maximum ratings Value PIN/Parameter Name Parameter Unit Min Max -0.3 +20 V Supply Voltage (t < 5 min) +27 V Supply Voltage < 400ms +35 V Maximum Voltage +3.6 V -0.3 +3.6 V Supply Voltage (Continuous) VS VS, VCP V3, VLOGIC CS, CLK, MOSI, MISO, Maximum Voltage EN, CLKin, HETx OUT_EN Maximum Voltage -0.3 +3.6 V VRS_Meas Maximum Voltage -0.3 +3.6 V OUTx, Dx Maximum Voltage -0.3 +35 V -40 (1) C +190(2) C +150 C TJ(Operating) TJ(Operating) TJ(Storage) Junction Temperature Junction Temperature (1h over life-time) Storage Temperature -65 1. Internally limited 2. Allowed only during switch-off 3.2 Thermal data Table 4. Thermal data Value Symbol Parameter TJ(Operating) Junction Temperature TA(Operating) Ambient Temperature Unit (3) Min Max -40 +150 C -40 +105 C Rth(j-a) Thermal resistance Junction to Ambient 20 C/W Rth(j-c) Thermal resistance Junction to case 2 C/W Maximum OUTx clamping energy, Single Pulse 50 mJ EOUT(MAX) 5/8 Package information 4 L9390 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. TQFP100 mechanical data & package dimensions DIM. mm MIN. TYP. A inch MAX. MIN. TYP. MAX. 1.200 0.0472 0.150 0.0020 0.0059 A1 0.050 A2 0.950 1.000 1.050 0.0374 0.0394 0.0413 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D2(1) 0.200 0.0035 2.000 D3 0.0079 0.0787 12.000 0.4724 E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E2(1) 2.000 0.0787 E3 12.000 e 0.500 L 0.450 0.600 L1 1.000 k 3.500 ccc OUTLINE AND MECHANICAL DATA 0.4724 0.0197 0.750 0.0177 0.0236 0.0295 0.0394 7.000 0.1378 0.2756 0.080 0.0031 (1) The size of exposed pad is variable depending of leadframe design pad size. End user should verify "D2" and "E2" dimensions for each device application. TQFP100 (14x14x1.40mm) Exposed pad down 7357321 C 6/8 L9390 5 Revision history Revision history Table 5. Document revision history Date Revision Changes 22-Mar-2007 1 Initial release. 17-Sep-2013 2 Updated Disclaimer 7/8 L9390 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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