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Document Number: 73026
S09-0394-Rev. D, 09-Mar-09
Vishay Siliconix
Si4816BDY
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ.aMax. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA Ch-1 1.0 3.0 V
Ch-2 1.0 3.0
Gate-Body Leakage IGSS VDS = 0 V, VGS = 20 V Ch-1 100 nA
Ch-2 100
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V Ch-1 1
µA
Ch-2 100
VDS = 30 V, VGS = 0 V, TJ = 85 °C Ch-1 15
Ch-2 2000
On-State Drain CurrentbID(on) V
DS = 5 V, VGS = 10 V Ch-1 20 A
Ch-2 30
Drain-Source On-State ResistancebRDS(on)
VGS = 10 V, ID = 6.8 A Ch-1 0.0155 0.0185
Ω
VGS = 10 V, ID = 11.4 A Ch-2 0.0093 0.0115
VGS = 4.5 V, ID = 6.0 A Ch-1 0.0185 0.0225
VGS = 4.5 V, ID = 9.5 A Ch-2 0.013 0.016
Forward Transconductancebgfs
VDS = 15 V, ID = 6.8 A Ch-1 30 S
VDS = 15 V, ID = 11.4 A Ch-2 31
Diode Forward VoltagebVSD
IS = 1 A, VGS = 0 V Ch-1 0.73 1.1 V
IS = 1 A, VGS = 0 V Ch-2 0.47 0.5
Dynamica
Total Gate Charge Qg Channel-1
VDS = 15 V, VGS = 5 V, ID = 6.8 A
Channel-2
VDS = 15 V, VGS = 5 V, ID = - 11.4 A
Ch-1 7.8 10
nC
Ch-2 11.6 18
Gate-Source Charge Qgs
Ch-1 2.9
Ch-2 4.8
Gate-Drain Charge Qgd Ch-1 2.3
Ch-2 3.7
Gate Resistance Rg
Ch-1 1.5 3.0 4.5 Ω
Ch-2 0.9 1.8 2.7
Tur n - O n D e l ay Time td(on) Channel-1
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Channel-2
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Ch-1 11 17
ns
Ch-2 13 20
Rise Time tr
Ch-1 9 15
Ch-2 9 15
Turn-Off Delay Time td(off) Ch-1 24 40
Ch-2 31 50
Fall Time tf
Ch-1 9 15
Ch-2 11 17
Source-Drain Reverse Recovery Time trr
IF = 1.3 A, dI/dt = 100 A/µs Ch-1 20 35
IF = 2.2 A, dI/dt = 100 µA/µs Ch-2 25 40