IDT70T631S8BF8 - Integrated Device Technology

JUNE 2012

DSC-5670/9



Functional Block Diagram

◆◆

◆Full hardware support of semaphore signaling between

ports on-chip

◆◆

◆Fully asynchronous operation from either port

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆◆

◆Sleep Mode Inputs on both ports

◆◆

◆Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

◆◆

◆Single 2.5V (±100mV) power supply for core

◆◆

◆LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

◆◆

◆Available in a 256-ball Ball Grid Array and 208-ball fine pitch

Ball Grid Array

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆◆

◆Green parts available, see ordering information

Features

◆◆

◆True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆◆

◆High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 10/12ns (max.)

◆◆

◆RapidWrite Mode simplifies high-speed consecutive write

cycles

◆◆

◆Dual chip enables allow for depth expansion without

external logic

◆◆

◆IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆◆

◆M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆◆

◆Busy and Interrupt Flags

◆◆

◆On-chip port arbitration logic

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

IDT70T633/1S

1. Address A18x is a NC for IDT70T631.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

512/256K x 18

MEMORY

ARRAY

Address

Decoder

18R

(1)

Address

Decoder

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

I/O

-I/O

17L

I/O

-I/O

17R

Din_L

ADDR_L

Din_R

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

M/S

R/W

5670 drw 01

18L

(1)

CONTROL

LOGIC

L(4)

R(4)

JTAG

TCK

TRST

TMS

TDI

TDO

INT

L(3)

SEM

BUSY

L(2,3)

BUSY

R(2,3)

SEM

IN T

R(3)

NOTES:

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous

Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a

stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-

TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T633/1 has a RapidWrite Mode which allows the designer

to perform back-to-back write operations without pulsing the R/W input

each cycle. This is especially significant at the 10ns cycle times of the

IDT70T633/1, easing design considerations at these high performance

levels.

The 70T633/1 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for

the core of the device (VDD) remains at 2.5V.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(1,2,3)

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

3. All VSS pins must be connected to ground supply.

4. A18X is a NC for IDT70T631.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

70T633/1BC

BC-256(5,6)

256-Pin BGA

Top View

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

C14

OPT

B14

A14

A12

B12

C11

BUSY

D12

DDQR

D11

DDQR

C10

SEM

B11

A11

INT

DDQR

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

18L

(4)

16L

TDO

I/O

TDI

I/O

10R

I/O

10L

DDQL

I/O

11L

I/O

11R

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L

I/O

14R

I/O

13R

DDQL

I/O

14L

DDQL

I/O

15L

I/O

15R

DDQR

I/O

16R

I/O

16L

DDQR

I/O

17R

I/O

17L

TMS

16R

TRST

18R

(4)

TCK

17R

13R

15R

P12

P10

SEM

T11

INT

P11

BUSY

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

F15

R11

M/S

11R

11L

B10

R/W

C13

10R

R10

R/W

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

N5 N6

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5670 drw 02c

03/13/03

17L

DDQL

DDQR

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3)(con't.)

NOTES:

1. All VDD pins must be connected to 2.5V power supply.

2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

3. All VSS pins must be connected to ground.

4. A18X is a NC for IDT70T631.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

1716

1412 13

9876543

21 11

I/O

NC V

INT

SEM

NCA

12L

16L

OPT

NC V

BUSY

13L

17L

I/O

DDQR

DD QL

I/O

DDQR

10L

14 L

18L

(4)

I/O

11L

I/O

10L

NC V

I/O

11R

DDQR

I/O

10 R

DDQL

NC V

I/O

12L

NC V

DDQR

I/O

12R

DD QL

NC I/O

14L

DDQR

DD QL

NC I/O

15R

I/O

DDQL

I/O

15L

11L

I/O

NC V

I/O

NC V

DDQL

I/O

NC V

I/O

DDQR

I/O

DDQL

I/O

NC V

NC I/O

15 L

16R

12R

NC V

SEM

INT

DDQR

NC I/O

17R

13R

BUSY

DDQL

I/O

DD QR

NC I/O

17L

DDQL

18R

(4)

14R

10R

NCV

I/O

NC V

15R

11R

DDQL

I/O

OPT

NC I/O

70T633/1BF

BF-208

(5,6)

208-Ball BGA

Top View

(7)

5670 drw 02b

I/O

13L

I/O

14R

I/O

13R

I/O

16R

I/O

16L

DDQR

TDO

TDI

TCK

TMS

TRST

03/12/03

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port Right Port Names

, CE

Chip Enables (Input)

R/W

Read/Write Enable (Input)

Output Enable (Input)

- A

18L

(1)

- A

18R

(1)

Address (Input)

I/O

- I/O

17L

I/O

- I/O

17R

Data Input/Output

SEM

Semaphore Enable (Input)

INT

Interrupt Flag (Output)

BUSY

Busy Flag (Output)

Upper Byte Select (Input)

Lower Byte Select (Input)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(2)

(Input)

OPT

Option for selecting V

DDQX

(2,3)

(Input)

Sleep Mode Pin

(4)

(Input)

M/SMaster or Slave Select (Input)

(5)

Power (2.5V)

(2)

(Input)

Ground (0V) (Input)

TDI Test Data Input

TDO Test Data Output

TCK Test Logic Clock (10MHz) (Input)

TMS Test Mode Select (Input)

TRST Reset (Initialize TAP Controller) (Input)

5670 tbl 01

NOTES:

1. Address A18x is a NC for IDT70T631.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are

not affected during sleep mode. It is recommended that boundry scan not be

operated during sleep mode.

5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master

(M/S=VIH).

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTE:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

Truth Table I—Read/Write and Enable Control(1)

OE SEM CE

UB LB R/WZZ

Upper Byte

I/O

9-17

Lower Byte

I/O

0-8

MODE

X H H X X X X L High-Z High-Z Deselected–Power Down

X H X L X X X L High-Z High-Z Deselected–Power Down

X H L H H H X L High-Z High-Z Both Bytes Deselected

XHLHHLLLHigh-Z D

Write to Lower Byte

XHLHLHLL D

High-Z Write to Upper Byte

XHLHLLLL D

Write to Both Bytes

LHLHHLHLHigh-ZD

OUT

Read Lower Byte

LHLHLHHL D

OUT

High-Z Read Uppe r Byte

LHLHLLHL D

OUT

Read Both Bytes

H H L H L L X L High-Z High-Z Outputs Disabled

X X X X X X X H High-Z High-Z High-Z Sleep Mode

5670 tbl 02

Truth Table II – Semaphore Read/Write Control(1)

NOTES:

1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.

2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL.

Inputs

(1)

Outputs

Mode

(2)

R/WOE UB LB SEM I/O

1-17

I/O

HHL L L LDATA

OUT

DATA

OUT

Read Data in Semaphore Flag

(3)

H↑XXL L X DATA

Write I/O

into Semaphore Flag

LXXXX L

______ ______

Not Allowe d

5670 tbl 03

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage(1)

Recommended DC Operating

Conditions with VDDQ at 2.5V

Absolute Maximum Ratings(1)

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be

supplied as indicated above.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any Input or I/O pin cannot exceed VDDQ during power

supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade

Ambient

Temperature GND V

Commercial 0

C to +70

C0V2.5V

100mV

Industrial -40

C to +85

C0V2.5V

100mV

5670 tbl 04

Symbol Rating Commercial

& Industrial

Unit

TERM

)

Te rm inal Vo l tag e

with Respect to GND

-0.5 to 3.6 V

TERM

(2)

DDQ

)

DDQ

Terminal Voltage

with Respect to GND

-0.3 to V

DDQ

+ 0.3 V

TE RM

(2)

(INPUTS and I/O's)

Input and I/O Te rminal

Voltage with Respect to GND

-0.3 to V

DDQ

+ 0.3 V

BIAS

(3)

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

Junction Temperature +150

OUT

(For V

DDQ

3.3V) DC Output Current 50 mA

OUT

(For V

DDQ

2.5V) DC Output Current 40 mA

5670 tbl 07

Symbol Parameter Min. Typ. Max. Unit

Core Supply Voltage 2.4 2.5 2.6 V

DDQ

I/O Supply Voltage

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

Input High Voltage

(Address, Control &

Data I/O Inputs)

(3)

1.7

____

DDQ

+ 100mV

(2)

Input High Voltage

JTAG 1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, M/SV

- 0.2V

____

+ 100mV

(2)

Input Low Voltage -0.3

(1)

____

0.7 V

Input Low Voltage -

ZZ, OPT, M/S-0.3

(1)

____

0.2 V

5670 tbl 05

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) TQFP ONLY

Symbol Parameter Conditions

(2)

Max. Unit

Input Capacitance V

= 3dV 8 pF

OUT

(3)

Output Capacitance V

OUT

= 3dV 10.5 pF

5670 tbl 08

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is

less.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be

supplied as indicated above.

Symbol Parameter Min. Typ. Max. Unit

Core Supply Voltage 2.4 2.5 2.6 V

DDQ

I/O Supply Voltage

(3)

3.15 3.3 3.45 V

Ground 0 0 0 V

Input Hig h Voltage

(Address, Control

&Data I/O Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Input Hig h Voltage

JTAG 1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, M/SV

- 0.2V

____

+ 100mV

(2)

Input Low Voltage -0.3

(1)

____

0.8 V

Input Low Voltage -

ZZ, OPT, M/S-0.3

(1)

____

0.2 V

5670 tbl 06

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

Symbol Parameter Test Conditions

70T633/1S

UnitMin. Max.

| Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

10 µA

| JTAG & ZZ Input Leakage Current

(1,2)

DD =

Max.

= 0V to V

___

+30 µA

| Output Leakage Current

(1,3)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

10 µA

(3.3V) Output Low Voltage

(1)

= +4mA, V

DDQ

= Min.

___

0.4 V

(3.3V) Output High Voltage

(1)

= -4mA, V

DDQ

= Min. 2.4

___

(2.5V) Output Low Voltage

(1)

= +2mA, V

DDQ

= Min.

___

0.4 V

(2.5V) Output High Voltage

(1)

= -2mA, V

DDQ

= Min. 2.0

___

5670 tbl 09

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).

4. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V

CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

5. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 5 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

70T633/1S10

Com'l

& Ind

(6)

70T633/1S12

Com'l

& Ind

70T633/1S15

Com'l Only

Symbol Parameter Test Condition Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dynamic Operating

Current (Both

Ports Active)

and CE

= V

Outputs Disabled

f = f

MAX

(1)

COM'L S 300 405 300 355 225 305 mA

IND S 300 445 300 395

____ ____

SB1

(6)

Standby Current

(Both Ports - TTL

Leve l Inputs)

= CE

= V

f = f

MAX

(1)

COM'L S 90 120 75 105 60 85 mA

IND S 90 145 75 130

____ ____

SB2

(6)

Standby Current

(One Port - TTL

Leve l Inputs)

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,

f = f

MAX

(1)

COM'L S 200 265 180 230 150 200 mA

IND S 200 290 180 255

____ ____

SB3

Full Standby Current

(Both Ports - CMOS

Leve l Inputs)

Both Ports CE

and

> V

DDQ

- 0.2V,

> V

DDQ

- 0.2V or V

< 0.2V,

f = 0

(2)

COM'L S 2 10 2 10 2 10 mA

INDS220220

____ ____

SB4

(6)

Full Standby Current

(One Port - CMOS

Leve l Inputs)

"A"

< 0.2V and

"B"

> V

DDQ

- 0.2V

(5)

> V

DDQ

- 0.2V or V

< 0.2V,

Active Port, Outputs Disabled,

f = f

MAX

(1)

COM'L S 200 265 180 230 150 200 mA

IND S 200 290 180 255

____ ____

Sleep Mode Current

(Both Ports - TTL

Leve l Inputs)

L =

R =

f = f

MAX

(1)

COM'L S 2 10 2 10 2 10 mA

INDS220220

____ ____

5670 tbl 10

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ = 3.3V/2.5V)

Figure 1. AC Output Test load.

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V / GND to 2.5V

2ns Max.

1.5V/1.25V

Figure 1

5670 tbl 11

1.5V/1.25

50Ω

5670 drw 03

10pF

(Tester)

DATA

OUT

Figure 3. Typical Output Derating (Lumped Capacitive Load).

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when

CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(4)

Symbol Parameter

70T633/1S10

Com'l

& Ind

(5)

70T633/1S12

Com'l

& Ind

70T633/1S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max.

READ CYCLE

Read Cycle Time 10

____

Address Access Time

____

15 ns

ACE

Chip Enable Access Time

(3) ____

____

15 ns

ABE

Byte Enable Access Time

(3) ____

____

7ns

AOE

Output Enable Access Time

____

7ns

Output Hold from Address Change 3

____

Output Low-Z Time Chip Enable and Semaphore

(1,2)

____

LZOB

Output Low-Z Time Output Enable and Byte Enable

(1,2)

____

Output High-Z Time

(1,2)

040608ns

Chip Enable to Power Up Time

(2)

____

Chip Disable to Power Down Time

(2) ____

____

12 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)

____

8ns

SAA

Semaphore Address Access Time 2 10 2 12 2 15 ns

SOE

Semaphore Output Enable Access Time

____

7ns

5670 tbl 12

Symbol Parameter

70T633/1S10

Com'l

& Ind

(5)

70T633/1S12

Com'l

& Ind

70T633/1S15

Com'l Only

UnitMin. Max. Min. Max. Min. Max.

WRI T E CYCLE

Write Cycle Time 10

____

Chip Enable to End-of-Write

(3)

____

Address Valid to End-of-Write 7

____

Address Set-up Time

(3)

____

Write Pulse Width 7

____

Write Recovery Time 0

____

Data Valid to End-of-Write 5

____

Data Hold Time 0

____

Write Enable to Output in High-Z

(1,2)

____

8ns

Output Active from End-of-Write

(1,2)

____

SWRD

SEM Flag Write to Read Time 5

____

SPS

SEM Flag Contention Window 5

____

5670 tbl 13

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.

5. SEM = VIH.

6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.

R/W

ADDR

UB,LB

5670 drw 06

(4)

ACE

(4)

AOE

(4)

ABE

(4)

(2)

(3,4)

BDD

DATA

OUT

BUSY

OUT

VALID DATA(4)

(6)

(1)

LZOB

5670 drw 07

50% 50%

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or UB or LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

R/W

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4) (4)

(7)

UB,LB

5670 drw 10

(9)

CE or SEM

(9)

(7)

(3)

(7)

5670 drw 11

ADDRESS

DATA

R/W

UB,LB

(3)

(2)

(6)

CE or SEM

(9)

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T633/1 is capable of performing multiple back-to-back write

operations without having to pulse the R/W, CE, or BEn signals high

during address transitions. This RapidWrite Mode functionality allows the

system designer to achieve optimum back-to-back write cycle performance

without the difficult task of generating narrow reset pulses every cycle,

simplifying system design and reducing time to market.

During this new RapidWrite Mode, the end of the write cycle is now

defined by the ending address transition, instead of the R/W or CE or BEn

transition to the inactive state. R/W, CE, and BEn can be held active

throughout the address transition between write cycles.

Care must be taken to still meet the Write Cycle time (tWC), the time in

which the Address inputs must be stable. Input data setup and hold times

(tDW and tDH) will now be referenced to the ending address transition. In

this RapidWrite Mode the I/O will remain in the Input mode for the duration

of the operations due to R/W being held low. All standard Write Cycle

specifications must be adhered to. However, tAS and tWR are only

applicable when switching between read and write operations. Also,

there are two additional conditions on the Address Inputs that must also

be met to ensure correct address controlled writes. These specifications,

the Allowable Address Skew (tAAS) and the Address Rise/Fall time (tARF),

must be met to use the RapidWrite Mode. If these conditions are not met

there is the potential for inadvertent write operations at random intermediate

locations as the device transitions between the desired write addresses.

5670 drw 08

ADDRESS

CE or SEM

(6)

BEn

R/W

DATA

OUT

(2)

(5) (5)

(4)

Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)

NOTES:

1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

5670 drw 09

AAS

ARF

(1)

Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle

AC Electrical Characteristics over the Operating Temperature Range

and Supply Voltage Range for RapidWrite Mode Write Cycle(1)

NOTE:

1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.

NOTE:

1. A17 for IDT70T631.

Symbol Parameter Min Max Unit

AAS

Allowable Address Skew for RapidWrite Mode

____

1ns

ARF

Address Rise/Fall Time for RapidWrite Mode 1.5

____

V/ns

5670 tbl 14

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. DOR = DOL = VIL, CE0L = CE0R = VIH; CE1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for

appropriate UB/LB controls.

2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.

SEM

(1)

5670 drw 12

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA VALID

DATA

OUT

SWRD

Read Cycle

Write Cycle

-A

VALID

(2)

SOP

SOE

SEM

"A"

5670 drw 13

SPS

MATCH

R/W

"A"

MATCH

0"A"

-A

2"A"

SIDE "A"

(2)

SEM

"B"

R/W

"B"

0"B"

-A

2"B"

SIDE "B"

(2)

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

Symbol Parameter

70T633/1S10

Com'l

& Ind(6)

70T633/1S12

Com'l

& Ind

70T633/1S15

Com'l Only

Unit

Min. Max. Min. Max. Min. Max.

BUSY TIMING (M/S=V

)

BAA

BUSY Access Time from Address Match ____ 10 ____ 12 ____ 15 ns

BDA

BUSY Disable Time from Address Not Matched ____ 10 ____ 12 ____ 15 ns

BAC

BUSY Access Time from Chip Enable Low ____ 10 ____ 12 ____ 15 ns

BDC

BUSY Disable Time from Chip Enable High ____ 10 ____ 12 ____ 15 ns

APS

Arbitration Priority Se t-up Time(2) 2.5 ____ 2.5 ____ 2.5 ____ ns

BDD

BUSY Disable to Valid Data(3 ) ____ 10 ____ 12 ____ 15 ns

Write Hold After BUSY(5) 7____ 9____ 12 ____ ns

BUSY TIMING (M/S=V

)

BUSY Input to Write(4) 0____ 0____ 0____ ns

Write Hold After BUSY(5) 7____ 9____ 12 ____ ns

PORT-TO-PORT DELAY TIMING

WDD

Write Pulse to Data Delay(1) ____ 14 ____ 16 ____ 20 ns

DDD

Write Data Valid to Read Data Delay(1) ____ 14 ____ 16 ____ 20 ns

5670 tbl 15

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1,2,3)

Symbol Parameter

70T633/1S10

Com'l

& Ind

70T6331S12

Com'l

& Ind

70T633/1S15

Com'l Only

Min. Max. Min. Max. Min. Max.

SLEEP MODE TIMING (ZZx=V

)

ZZS

Sleep Mode Set Time 10

____

ZZR

Sleep Mode Reset Time 10

____

ZZPD

Sleep Mode Power Down Time

(4)

____

ZZPU

Sleep Mode Power Up Time

(4)

____

5670 tbl 15a

NOTES:

1. Timing is the same for both ports.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected

during sleep mode. It is recommended that boundary scan not be operated during sleep mode.

3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.

4. This parameter is guaranteed by device characterization, but is not production tested.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

Timing Waveform of Write with BUSY (M/S = VIL)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB only applies to the slave mode.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

5670 drw 14

APS

ADDR

"A"

DATA

OUT "B"

MATCH

R/W

"A"

DATA

IN "A"

ADDR

"B"

VALID

(1)

MATCH

BUSY

"B"

BDA

VALID

BDD

DDD

(3)

WDD

BAA

5670 drw 15

R/W

"A"

BUSY

"B"

(3)

R/W

"B"

(1)

(2)

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1,2)

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing (M/S = VIH)(1,3,4)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.

4. CE0X = OEX = LBX = UBX = VIL. CE1X = VIH.

5670 drw 16

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"(3)

"B"(3)

BUSY

"B"

APS

BAC

BDC

(2)

5670 drw 17

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

70T633/1S10

Com'l

& Ind

70T633/1S12

Com'l

& Ind

70T633/1S15

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

Address Set-up Time 0

____

Write Recovery Time 0

____

INS

Interrup t Set Time

____

15 ns

INR

Interrup t Reset Time

____

15 ns

5670 tbl 16

NOTES:

1. Timing is the same for both ports.

2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table III — Interrupt Flag(1,4)

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.

4. Timing depends on which enable signal (CE or R/W) is asserted last.

5. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.

5670 drw 18

ADDR

"A"

INTERRUPT SET ADDRESS

"A"(3)

R/W

"A"

(4) (5)

INS

(4)

INT

"B"

(2)

5670 drw 19

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"(3)

"B"

(4)

INR

(4)

INT

"B"

(2)

Left Port Right Port

FunctionR/W

18L

-A

(5)

INT

R/W

18R

-A

(5)

INT

LLX7FFFFXXXX X L

(2)

Set Right INT

Flag

XXX X XXLL7FFFFH

(3)

Reset Right INT

Flag

XXX X L

(3)

L L X 7FFFE X Set Left INT

Flag

X L L 7FFFE H

(2)

X X X X X Reset Left INT

Flag

5670 tb l 17

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70T633/1 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70T633/1 has an automatic power down

feature controlled by CE. The CE0 and CE1 control the on-chip power

down circuitry that permits the respective port to go into a standby mode

when not selected (CE = HIGH). When a port is enabled, access to the

entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

Truth Table. The left port clears the interrupt through access of

address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care".

Likewise, the right port interrupt flag (INTR) is asserted when the left

port writes to memory location 7FFFF (HEX) and to clear the interrupt

flag (INTR), the right port must read the memory location 7FFFF. The

message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T631)

is user-defined since it is an addressable SRAM location. If the interrupt

function is not used, address locations 7FFFE and 7FFFF are not used

as mail boxes, but as part of the random access memory. Refer to Truth

Table III for the interrupt operation.

Truth Table IV —

Address BUSY Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

4. A18 is a NC for IDT70T631. Address comparison will be for A0 - A17.

5. CEX = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.

Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.

3. CE0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Inputs Outputs

Function

L(5)

R(5)

-A

18L(4)

-A

18R

BUSY

L(1)

BUSY

R(1)

X X NO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

LL MATCH (2) (2) Write Inhibit

(3)

5670 tbl 18

Functions D

- D

Left D

- D

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

5670 tbl 19

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T633/1 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with the R/W signal. Failure to

observe this timing can result in a glitched internal write inhibit signal

and corrupted data in the slave.

Semaphores

The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18

CMOS Static RAM with an additional 8 address locations dedicated to

binary semaphore flags. These flags allow either processor on the left or

right side of the Dual-Port RAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an example,

the semaphore can be used by one processor to inhibit the

other from accessing a portion of the Dual-Port RAM or any other shared

resource.

The Dual-Port RAM features a fast access time, with both ports

being completely independent of each other. This means that the

activity on the left port in no way slows the access time of the right port.

Both ports are identical in function to standard CMOS Static RAM and

can be read from or written to at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic power-down

feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and

SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-

chip power down circuitry that permits the respective port to go into standby

mode when not selected.

Systems which can best use the IDT70T633/1 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the hardware

semaphores of the IDT70T633/1, which provide a lockout mechanism

without requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70T633/1 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port RAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that a

shared resource is in use. If the left processor wants to use this

resource, it requests the token by setting the latch. This processor then

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70T633/1 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAMs

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70T633/1 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The BUSY arbitration on a master is based on the chip enable and

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70T633/1 Dual-Port RAMs.

5670 drw 20

MASTER

Dual Port RAM

BUSYR

MASTER

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

BUSYLBUSYL

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

verifies its success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side processor

has set the latch first, has the token and is using the shared resource.

The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70T633/1 in a

separate memory space from the Dual-Port RAM array. This address

space is accessed by placing a low input on the SEM pin (which acts as

a chip select for the semaphore flags) and using the other control pins

(Address, CE0, CE1, R/W and LB/UB) as they would be used in accessing

a standard Static RAM. Each of the flags has a unique address which can

be accessed by either side through address pins A0 – A2. When accessing

the semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to

a zero on that side and a one on the other side (see Truth Table V).

That semaphore can now only be modified by the side showing the zero.

When a one is written into the same location from the same side, the

flag will be set to a one for both sides (unless a semaphore request

from the other side is pending) and then can be written to by both sides.

The fact that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what makes

semaphore flags useful in interprocessor communications. (A thor-

ough discussion on the use of this feature follows shortly.) A zero

written into the same location from the other side will be stored in the

semaphore request latch for that side until the semaphore is freed by

the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE

signals need to be active. (Please refer to Truth Table II). Furthermore,

the read value is latched into one side’s output register when that side's

semaphore select (SEM, BEn) and output enable (OE) signals go active.

This serves to disallow the semaphore from changing state in the middle

of a read cycle due to a write cycle from the other side.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Table V). As an example, assume a processor

writes a zero to the left port at a free semaphore location. On a

subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side

during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during

the gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the opposite side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

If the opposite side semaphore request latch has been written to

zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first request latch. The

opposite side flag will now stay LOW until its semaphore request latch

is written to a one. From this it is easy to understand that, if a

semaphore is requested and the processor which requested it no

longer needs the resource, the entire system can hang up until a one

is written into that semaphore request latch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one

side receives the token. If one side is earlier than the other in making

the request, the first side to make the request will receive the token. If

both requests arrive at the same time, the assignment will be arbitrarily

made to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is

secure. As with any powerful programming technique, if semaphores

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

handled via the initialization program at power-up. Since any sema-

phore request flag which contains a zero must be reset to a one,

all semaphores on both sides should have a one written into them

at initialization from both sides to assure that they will be free

when needed.

Figure 4. IDT70T633/1 Semaphore Logic

5670 drw 21

0DQ

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

5670drw22

ZZPD

DATA

VALIDAD

ESS

ZZR

NonewreadsorwritesallowedNorm

alO

peration

Norm

alOperationSleepM

odeNoreadsorw

ritesallowed

VALIDDATA

DRESS

ZZS

ZZPU

Timing Waveform of Sleep Mode(1,2)

NOTES:

1. CE1 = VIH.

2. All timing is same for Left and Right ports.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

5. JTAG cannot be tested in sleep mode.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5670 drw 23

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical

Characteristics(1,2,3,4,5)

70T633/1

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

JTAG Clock HIGH 40

____

JCL

JTAG Clock Low 40

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset 50

____

JRSR

JTAG Reset Recovery 50

____

JCD

JTAG Data Output

____

25 ns

JDC

JTAG Data Output Hold 0

____

JTAG Setup 15

____

JTAG Hold 15

____

5670 tbl 20

Sleep Mode

The IDT70T633/1 is equipped with an optional sleep or low power

mode on both ports. The sleep mode pin on both ports is active high. During

normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the

port will enter sleep mode where it will have the lowest possible power

consumption. The sleep mode timing diagram demonstrates the modes of

operation: Normal Operation, No Read/Write Allowed and Sleep Mode.

For a period of time prior to sleep mode and after recovering from sleep

mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read

operation occurs during these periods, the memory array may be

corrupted. Validity of data out from the RAM cannot be guaranteed

immediately after ZZ is asserted (prior to being in sleep).

During sleep mode the RAM automatically deselects itself and discon-

nects its internal buffer. All outputs will remain in high-Z state while in sleep

mode. All inputs are allowed to toggle, but the RAM will not be selected and

will not perform any reads or writes.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field Value Description

Revision Number (31:28) 0x0 Reserved for version number

IDT Device ID (27:12) 0x33B

(1)

Defines IDT part number 70T633

IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5670 tbl 21

System Interface Parameters

Instruction Code Description

EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs(1).

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs(2) and outputs(1) to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

RESERVED All other codes Several combinations are reserved. Do not use codes other than those

identified above.

5670 tbl 23

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

Scan Register Sizes

Instruction (IR) 4

Bypass (BYR) 1

Identific atio n (IDR) 32

Boundary Scan (BSR) Note (3)

5670 tbl 22

NOTE:

1. Device ID for IDT70T631 is 0x33C.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTES:

1. Green parts available. For specific speeds and packages contact your local sales office.

IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History:

04/25/03: Initial Datasheet

10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table

Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table

Page 9,11,15, Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only

17&25

Page 10 Added Capacitance Derating Drawing

Page 11,15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables

Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table

Page 12 Added tLZOB to the Waveform of Read Cycles Drawing

Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing

Page 1& 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information

Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms

10/20/03: Page 15 Corrected tARF to 1.5V/ns Min.

04/21/04: Removed Preliminary status from entire datasheet

01/05/06: Page 1 Added green availability to features

Page 27 Added green indicator to ordering information

07/25/08: Page 9 Corrected a typo in the DC Chars table

01/19/09: Page 27 Removed "IDT" from orderable part number

04/20/10: Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01

10/15/11: Page 2,13 Corrected 70T651/9 to 70T633/1

Page 26 Updated ordering information to include tube or tray and tape & reel.

6/18/12 Page 1,2,8,10, Removed 8ns from datasheet to match pricebook.

16,18,26

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

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