SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperate From 1.65 V to 3.6 V
DInputs Accept Voltages to 5.5 V
DSpecified From −40°C to 85°C,
−40°C to 125°C, and −55°C to 125°C
DMax tpd of 7 ns at 3.3 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LVC574A ...J OR W PACKAGE
SN74LVC574A . . . DB, DGV, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LVC574A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
CLK
VCC
SN74LVC574A . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
OE
CLK V
GND
CC
description/ordering information
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Reel of 1000 SN74LVC574ARGYR LC574A
−40°C to 85°CVFBGA − GQN
Reel of 1000
SN74LVC574AGQNR
LC574A
40 C
to
85 C
VFBGA − ZQN (Pb-free) Reel of 1000 SN74LVC574AZQNR LC574A
PDIP − N Tube of 20 SN74LVC574AN SN74LVC574AN
SOIC DW
Tube of 25 SN74LVC574ADW
LVC574A
SOIC − DW Reel of 2000 SN74LVC574ADWR LVC574A
SOP − NS Reel of 2000 SN74LVC574ANSR LVC574A
−40°C to 125°CSSOP − DB Reel of 2000 SN74LVC574ADBR LC574A
40 C
to
125 C
Tube of 70 SN74LVC574APW
TSSOP − PW Reel of 2000 SN74LVC574APWR LC574A
TSSOP
PW
Reel of 250 SN74LVC574APWT
LC574A
TVSOP − DGV Reel of 2000 SN74LVC574ADGVR LC574A
CDIP − J Tube of 20 SNJ54LVC574AJ SNJ54LVC574AJ
−55°C to 125°CCFP − W Tube of 85 SNJ54LVC574AW SNJ54LVC574AW
LCCC − FK Tube of 55 SNJ54LVC574AFK SNJ54LVC574AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
terminal assignments
1234
A1D OE VCC 1Q
B3D 3Q 2D 2Q
C5D 4D 5Q 4Q
D7D 7Q 6D 6Q
EGND 8D CLK 8Q
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D
OUTPUT
Q
L↑H H
L↑LL
LLX Q
0
H X X Z
GQN OR ZQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
C1
1
11
2
19
1D
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): GQN/ZQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation, Ptot (TA = −40°C to 125°C) (see Notes 5 and 6) 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
5. For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K.
6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K.
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 7)
SN54LVC574A
−55 TO 125°CUNIT
MIN MAX
UNIT
V
Supply voltage
Operating 2 3.6
V
VCC Supply voltage Data retention only 1.5 V
VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
VIInput voltage 0 5.5 V
V
Output voltage
High or low state 0 VCC
V
VOOutput voltage 3−state 0 5.5 V
I
High level output current
VCC = 2.7 V −12
mA
IOH High-level output current VCC = 3 V −24 mA
IO
Low level output current
VCC = 2.7 V 12
mA
IOL Low-level output current VCC = 3 V 24 mA
Δt/ΔvInput transition rise or fall rate 6 ns/V
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions (see Note 7)
SN74LVC574A
TA = 25°C−40 TO 85°C−40 TO 125°CUNIT
MIN MAX MIN MAX MIN MAX
UNIT
V
Supply voltage
Operating 1.65 3.6 1.65 3.6 1.65 3.6
V
VCC Supply voltage Data retention only 1.5 1.5 1.5 V
Hi h l l i t
VCC = 1.65 V to 1.95 V 0.65 ×VCC 0.65 ×VCC 0.65 ×VCC
VIH
High-level input
voltage
VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
VIH
vo
lt
age
VCC = 2.7 V to 3.6 V 2 2 2
V
Lllit
VCC = 1.65 V to 1.95 V 0.35 ×VCC 0.35 ×VCC 0.35 ×VCC
VIL
Low-level input
voltage
VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
VIL
vo
lt
age
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
V
VIInput voltage 0 5.5 0 5.5 0 5.5 V
V
Output voltage
High or low state 0 VCC 0 VCC 0 VCC
V
VOOutput voltage 3−state 0 5.5 0 5.5 0 5.5 V
VCC = 1.65 V −4 −4 −4
I
Hi
g
h-level VCC = 2.3 V −8 −8 −8
mA
IOH
High level
output current VCC = 2.7 V −12 −12 −12 mA
VCC = 3 V −24 −24 −24
VCC = 1.65 V 4 4 4
I
Low-level VCC = 2.3 V 8 8 8
mA
IOL
Low level
output current VCC = 2.7 V 12 12 12 mA
VCC = 3 V 24 24 24
Δt/ΔvInput transition rise or fall rate 6 6 6 ns/V
NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC574A
PARAMETER TEST CONDITIONS VCC −55 TO 125°CUNIT
TEST
CONDITIONS
VCC
MIN TYP†MAX
UNIT
IOH = −100 μA2.7 V to 3.6 V VCC − 0.2
I12 mA
2.7 V 2.2
V
VOH IOH = −12 mA 3 V 2.4 V
IOH = −24 mA 3 V 2.2
IOL = 100 μA2.7 V to 3.6 V 0.2
VOL IOL = 12 mA 2.7 V 0.4 V
IOL = 24 mA 3 V 0.55
V
IIVI = 5.5 V or GND 3.6 V ±5μA
IOZ VO = 0 to 5.5 V 3.6 V ±15 μA
VI = VCC or GND
I 0
36V
10
A
ICC 3.6 V ≤ VI ≤ 5.5 V‡IO = 0 3.6 V 10 μA
ΔICC One input atVCC − 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 μA
CiVI = VCC or GND 3.3 V 4 pF
CoVO = VCC or GND 3.3 V 5.5 pF
†TA = 25°C
‡This applies in the disabled state only.
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LVC574A
PARAMETER TEST CONDITIONS VCC TA = 25°C−40 TO 85°C−40 TO 125°CUNIT
TEST
CONDITIONS
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
IOH = −100 μA1.65 V to 3.6 V VCC − 0.2 VCC − 0.2 VCC − 0.2
IOH = −4 mA 1.65 V 1.29 1.2 1.2
IOH = −8 mA 2.3 V 1.9 1.7 1.7
V
VOH
I12 mA
2.7 V 2.2 2.2 2.2 V
IOH = −12 mA 3 V 2.4 2.4 2.4
IOH = −24 mA 3 V 2.3 2.2 2.2
IOL = 100 μA1.65 V to 3.6 V 0.1 0.2 0.2
IOL = 4 mA 1.65 V 0.24 0.45 0.45
VOL IOL = 8 mA 2.3 V 0.3 0.7 0.7 V
IOL = 12 mA 2.7 V 0.4 0.4 0.4
V
IOL = 24 mA 3 V 0.55 0.55 0.55
IIVI = 5.5 V or GND 3.6 V ±1±5±5μA
Ioff VI or VO = 5.5 V 0±4±10 ±10 μA
IOZ VI = 0 to 5.5 V 3.6 V ±1±10 ±10 μA
VI = VCC or GND
I 0
36V
1.5 10 10
A
ICC 3.6 V ≤ VI ≤ 5.5 V†IO = 0 3.6 V 1.5 10 10 μA
ΔICC
One input at VCC − 0.6 V,
Other inputs at VCC or
GND
2.7 V to 3.6 V 500 500 500 μA
CiVI = VCC or GND 3.3 V 4 pF
CoVO = VCC or GND 3.3 V 5.5 pF
†This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVC574A
VCC −55 TO 125°CUNIT
VCC
MIN MAX
UNIT
f
Clock frequency
2.7 V 150
MHz
fclock Clock frequency 3.3 V ± 0.3 V 150 MHz
t
Pulse duration CLK high or low
2.7 V 3.3
ns
twPulse duration, CLK high or low 3.3 V ± 0.3 V 3.3 ns
t
Setup time data before CLK↑
2.7 V 2
ns
tsu Setup time, data before CLK
↑
3.3 V ± 0.3 V 2ns
t
Hold time data after CLK↑
2.7 V 2
ns
thHold time, data after CLK
↑
3.3 V ± 0.3 V 2ns
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
TO
SN54LVC574A
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC −55 TO 125°CUNIT
PARAMETER
(INPUT)
(OUTPUT)
VCC
MIN MAX
UNIT
f
2.7 V 150
MHz
fmax 3.3 V ± 0.3 V 150 MHz
t
CLK
Q
2.7 V 8
ns
tpd CLK Q3.3 V ± 0.3 V 1 7 ns
t
OE
Q
2.7 V 9
ns
ten OE Q3.3 V ± 0.3 V 1 7.5 ns
t
OE
Q
2.7 V 7
ns
tdis OE Q3.3 V ± 0.3 V 0.5 6.4 ns
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN74LVC574A
VCC TA = 25°C−40 TO 85°C−40 TO 125°CUNIT
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
1.8 V ± 0.15 V 55 55 40
f
Clock frequency
2.5 V ± 0.2 V 95 95 80
MHz
fclock Clock frequency 2.7 V 150 150 150 MHz
3.3 V ± 0.3 V 150 150 150
1.8 V ± 0.15 V 9 9 9
t
Pulse duration CLK high or low
2.5 V ± 0.2 V 4 4 4
ns
twPulse duration, CLK high or low 2.7 V 3.3 3.3 3.3 ns
3.3 V ± 0.3 V 3.3 3.3 3.3
1.8 V ± 0.15 V 6 6 6
t
Setup time data before CLK↑
2.5 V ± 0.2 V 4 4 4
ns
tsu Setup time, data before CLK
↑
2.7 V 2 2 2 ns
3.3 V ± 0.3 V 2 2 2
1.8 V ± 0.15 V 4 4 4
t
Hold time data after CLK↑
2.5 V ± 0.2 V 2 2 2
ns
thHold time, data after CLK
↑
2.7 V 1.5 1.5 1.5 ns
3.3 V ± 0.3 V 1.5 1.5 1.5
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN74LVC574A
PARAMETER FROM
TO
VCC TA = 25°C−40 TO 85°C−40 TO 125°CUNIT
PARAMETER
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
1.8 V ± 0.15 V 55 55 40
f
2.5 V ± 02 V 95 95 80
MHz
fmax 2.7 V 150 150 150 MHz
3.3 V ± 0.3 V 150 150 150
1.8 V ± 0.15 V 1.0 7.1 21.5 1 21.6 1.0 21.6
t
2.5 V ± 0.2 V 1.0 4.9 10.0 1 10.5 1.0 10.5
ns
tpd CLK Q2.7 V 1.0 5.0 7.8 1 8 1.0 8.0 ns
3.3 V ± 0.3 V 2.2 4.6 6.8 2.2 7 2.2 7.0
1.8 V ± 0.15 V 1.0 6.6 19.0 1 19.5 1.0 19.5
t
2.5 V ± 0.2 V 1.0 4.8 10.0 1 10.5 1.0 10.5
ns
ten OE Q2.7 V 1.0 5.5 8.3 1 8.5 1.0 8.5 ns
3.3 V ± 0.3 V 1.5 4.4 7.3 1.5 7.5 1.5 7.5
1.8 V ± 0.15 V 1.0 5.4 18.3 1 18.8 1.0 18.8
t
2.5 V ± 0.2 V 1.0 3.0 7.3 1 7.8 1.0 7.8
ns
tdis OE Q2.7 V 1.0 4.0 6.8 1 7 1.0 7.3 ns
3.3 V ± 0.3 V 1.7 3.9 6.2 1.7 6.4 1.7 6.6
tsk(o) 3.3 V ± 0.3 V 1 1 ns
operating characteristics, TA = 25°C
PARAMETER TEST
CONDITIONS VCC TYP UNIT
1.8 V 25
Outputs enabled 2.5 V 29
Cd
Power dissipation capacitance per flip flop
p
f=10MHz
3.3 V 30
pF
C
pd Power dissipation capacitance per flip−flop f = 10 MHz 1.8 V 9pF
Outputs disabled 2.5 V 9
p
3.3 V 11
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + VΔ
VOH − VΔ
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
2.7 V
3.3 V ±0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
VΔ
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9757601Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9757601QRA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-9757601QSA ACTIVE CFP W 20 1 TBD Call TI Call TI
SN74LVC574ADBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74LVC574ADBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574AGQNR LIFEBUY BGA
MICROSTAR
JUNIOR
GQN 20 1000 TBD SNPB Level-1-240C-UNLIM
SN74LVC574AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LVC574ANE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVC574ANSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74LVC574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWT ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVC574AZQNR ACTIVE BGA
MICROSTAR
JUNIOR
ZQN 20 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
SNJ54LVC574AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVC574AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54LVC574AW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC574A, SN74LVC574A :
•Catalog: SN74LVC574A
•Automotive: SN74LVC574A-Q1, SN74LVC574A-Q1
•Enhanced Product: SN74LVC574A-EP, SN74LVC574A-EP
•Military: SN54LVC574A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 4
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC574ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVC574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LVC574AGQNR BGA MI
CROSTA
R JUNI
OR
GQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1
SN74LVC574ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74LVC574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC574APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC574APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVC574ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN74LVC574AZQNR BGA MI
CROSTA
R JUNI
OR
ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC574ADBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LVC574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0
SN74LVC574ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVC574AGQNR BGA MICROSTAR
JUNIOR GQN 20 1000 340.5 338.1 20.6
SN74LVC574ANSR SO NS 20 2000 367.0 367.0 45.0
SN74LVC574APWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74LVC574APWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74LVC574APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0
SN74LVC574APWT TSSOP PW 20 250 367.0 367.0 38.0
SN74LVC574ARGYR VQFN RGY 20 3000 367.0 367.0 35.0
SN74LVC574AZQNR BGA MICROSTAR
JUNIOR ZQN 20 1000 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated