Revised January 1999 CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs General Description The CD4094BC consists of an 8-bit shift register and a 3STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QS output is transferred to a second output, QS, on the following negative clock edge. The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH. Features Wide supply voltage range: High noise immunity: 3.0V to 18V 0.45 VDD (typ.) Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS 3-STATE outputs Ordering Code: Order Number Package Number Package Description CD4094BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View Truth Table Clock X = Don't Care = HIGH-to-LOW = LOW-to-HIGH Output Strobe Data Enable Parallel Outputs Q1 QN Serial Outputs QS (Note 1) Q No Change 0 X X Hi-Z Hi-Z Q7 0 X X Hi-Z Hi-Z No Change Q7 1 0 X Q7 No Change 1 1 0 0 QN-1 Q7 No Change 1 1 1 1 QN-1 Q7 No Change 1 1 1 No Change No Change No Change No Change No Change Q7 Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS. (c) 1999 Fairchild Semiconductor Corporation DS005983.prf www.fairchildsemi.com CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs October 1987 CD4094BC Block Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) -0.5 to +18 VDC Supply Voltage (VDD) Input Voltage (VIN) Input Voltage (VIN) -65C to +150C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0 to VDD VDC -40C to +85C Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line +3.0 to +15 VDC DC Supply Voltage (VDD) -0.5 to VDD +0.5 VDC Note 3: VSS = 0V unless otherwise specified. 260C DC Electrical Characteristics (Note 3) Symbol IDD VOL Parameter -40C Conditions Min IOL IOH IIN IOZ +85C Max Min Max Units VDD = 5.0V 20 20 150 A VDD = 10V 40 40 300 A VDD = 15V 80 80 600 A LOW Level VDD = 5.0V 0.05 0 0.05 0.05 V Output Voltage VDD = 10V 0.05 0 0.05 0.05 V 0.05 0 0.05 0.05 V HIGH Level VDD = 5.0V Output Voltage VDD = 10V LOW Level Input Voltage VIH Typ Quiescent |IO| 1.0 A |IO| 1 A VDD = 15V VIL Min Device Current VDD = 15V VOH +25C Max 4.95 4.95 5.0 4.95 V 9.95 9.95 10.0 9.95 V 14.95 14.95 15.0 14.95 VDD = 5.0V, VO = 0.5V or 4.5V 1.5 1.5 V 1.5 V VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V HIGH Level VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V LOW Level VDD = 5.0V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Output Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA (Note 4) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level VDD = 5.0V, VO = 4.6V -0.52 -0.44 0.88 -0.36 mA Output Current VDD = 10V, VO = 9.5V -1.3 -1.1 2.25 -0.9 mA (Note 4) VDD = 15V, VO = 13.5V -3.6 -3.0 8.8 Input Current VDD = 15V, VIN = 0V -0.3 -0.3 -1.0 A VDD = 15V, VIN = 15V 0.3 0.3 1.0 A 1 1 10 A 3-STATE Output VDD = 15V, VIN = 0V or 15V V -2.4 mA Leakage Current Note 4: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4094BC Absolute Maximum Ratings(Note 2) (Note 3) CD4094BC AC Electrical Characteristics (Note 5) TA = 25C, CL = 50 pF Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHZ tPLZ tPZH tPZL tTHL, tTLH Typ Max Units Propagation Delay Parameter VDD = 5.0V 300 600 ns Clock to QS VDD = 10V 125 250 ns VDD = 15V 95 190 ns Propagation Delay VDD = 5.0V 230 460 ns Clock to Q VDD = 10V 110 220 ns VDD = 15V 75 150 ns Propagation Delay Clock VDD = 5.0V 420 840 ns to Parallel Out VDD = 10V 195 390 ns VDD = 15V 135 270 ns Propagation Delay Strobe VDD = 5.0V 290 580 ns to Parallel Out VDD = 10V 145 290 ns VDD = 15V 100 200 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Level to HIGH Impedance VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay LOW VDD = 5.0V 140 280 ns Level to HIGH Impedance VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Impedance to HIGH Level VDD = 10V 75 150 ns VDD = 15V 55 110 ns Propagation Delay HIGH VDD = 5.0V 140 280 ns Impedance to LOW Level VDD = 10V 75 150 ns VDD = 15V 55 110 ns VDD = 5.0V 100 200 ns VDD = 10V 50 100 ns 40 80 ns Transition Time Conditions Min VDD = 15V tSU tr , tf Set-Up Time VDD = 5.0V 80 40 ns Data to Clock VDD = 10V 40 20 ns VDD = 15V 20 10 VDD = 5.0V 1 ms ms Maximum Clock Rise VDD = 10V 1 VDD = 15V 1 Minimum Clock VDD = 5.0V 200 100 ns Pulse Width VDD = 10V 100 50 ns VDD = 15V 83 40 ns Minimum Strobe VDD = 5.0V 200 100 ns Pulse Width VDD = 10V 80 40 ns VDD = 15V 70 35 ns Maximum Clock Frequency VDD = 5.0V 1.5 3.0 MHz VDD = 10V 3.0 6.0 MHz VDD = 15V 4.0 8.0 and Fall Time tPC tPS fmax CIN ns Input Capacitance Any Input 5.0 Note 5: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com ms 4 MHz 7.5 pF CD4094BC Timing Diagram Test Circuits and Timing Diagrams for 3-STATE 5 www.fairchildsemi.com CD4094BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M16B www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)