S-8204A Series
www.ablicinc.com
BATTERY PROTECTION IC
FOR 3-SERIES OR 4-SERIES CELL PACK
© ABLIC Inc., 2007-2016 Rev.3.5_01
1
The S-8204A Series includes high-accuracy voltage detection circuits and delay circuits, in single use, makes it
possible for users to monitor the status of 3-series or 4-series cell lithium-ion rechargeable battery. By switching
the voltage level which is applied to the SEL pin, users are able to use the S-8204A Series either for 3-series or
4-series cell pack.
By cascade connection using the S-8204A Series, it is also possible to protect 6-series or more cells*1
lithium-ion rechargeable battery pack.
*1. Refer to the application note for connection examples of protection circuit for 6-series or more cells.
In case of protecting 5-series cell lithium-ion rechargeable battery pack, contact our sales office.
Features
High-accuracy voltage detection function for each cell
Overcharge detection voltage n (n = 1 to 4) 3.8 V to 4.6 V (50 mV step) Accuracy 25 mV
Overcharge release voltage n (n = 1 to 4) 3.6 V to 4.6 V*1 Accuracy 50 mV
Overdischarge detection voltage n (n = 1 to 4) 2.0 V to 3.0 V (100 mV step) Accuracy 80 mV
Overdischarge release voltage n (n = 1 to 4) 2.0 V to 3.4 V*2 Accuracy 100 mV
Discharge overcurrent detection function in 3-step
Discharge overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV step) Accuracy 15 mV
Discharge overcurrent detection voltage 2 0.5 V (fixed) Accuracy 100 mV
Load short-circuit detection voltage 1.0 V (fixed) Accuracy 300 mV
Charge overcurrent detection function
Charge overcurrent detection voltage 0.25 V to 0.05 V (50 mV step) Accuracy 30 mV
Settable by external capacitor; overcharge detection delay time, overdischarge detection delay time,
discharge overcurrent detection delay time 1, discharge overcurrent detection delay time 2, charge
overcurrent detection delay time
(Load short-circuit detection delay time is internally fixed.)
Switchable between 3-series and 4-series cell by using the SEL pin
Independent charge and discharge control by the control pins
High-withstand voltage Absolute maximum rating: 24 V
Wide operation voltage range 2 V to 22 V
Wide operation temperature range Ta = 40C to 85C
Low current consumption
During operation 33 A max. (Ta = 25C)
During power-down 0.1 A max. (Ta = 25C)
Lead-free, Sn 100%, halogen-free*3
*1. Overcharge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.1 V to 0.4 V in 50 mV step.
(Overcharge hysteresis voltage = Overcharge detection voltage Overcharge release voltage)
*2.
Overdischarge hysteresis voltage n (n = 1 to 4) is selectable in 0 V, or in 0.2 V to 0.7 V in 100 mV step.
(Overdischarge hysteresis voltage = Overdischarge release voltage Overdischarge detection voltage)
*3. Refer to " Product Name Structure" for details.
Application
Rechargeable lithium-ion battery pack
Package
16-Pin TSSOP
www.ablic.com
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
2
Block Diagram
Discharge
overcurrent 2
Over-
charge 1
Ove
r
-
discharge
1
Ove
r
-
charge 2
Over-
discharge
2
Ove
r
-
charge 3
Ove
r
-
discharge 3
Over-
charge 4
Ove
r
-
discharge 4
Discharge
overcurrent 1
Short circuit
C
harge
overcurrent
COP
CIT
VMP
DOP
VINI
CDT
Control circuit
Delay circuit
Delay circuit
Delay circuit
R
VMD
R
VMS
CCT
SEL
Delay circuit
Delay circuit
Delay circuit
CTLC
CTLD
VDD
VC1
VC2
VC3
VC4
VSS
Remark Diodes in the figure are parasitic diodes.
Figure 1
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
3
Product Name Structure
1. Product name
S-8204A xx - xxxx x
Environmental code
U: Lead-free (Sn 100%), halogen-free
S: Lead-free, halogen-free
Package name (abbreviation) and packing specifications*1
TCT1: 16-Pin TSSOP, Tape
Serial code*2
Sequentially set from AA to ZZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Package
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel
16-Pin TSSOP Environmental code = S FT016-A-P-SD FT016-A-C-SD FT016-A-R-SD
Environmental code = U FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1
3. Product name list
Table 2
Product Name
Overcharge
Detection Voltage
[V
CU
]
Overcharge
Release Voltage
[V
CL
]
Overdischarge
Detection Voltage
[V
DL
]
Overdischarge
Release Voltage
[V
DU
]
Discharge
Overcurrent
Detection Voltage 1
[V
DIOV1
]
Charge
Overcurrent
Detection Voltage
[V
CIOV
]
0 V Battery
Charge Function
S-8204AAB-TCT1y 4.350
0.025 V 4.150
0.050 V 2.00
0.080 V 2.70
0.100 V 0.25
0.015 V
0.10
0.030 V Available
S-8204AAC-TCT1y 4.200
0.025 V 4.100
0.050 V 2.70
0.080 V 2.90
0.100 V 0.25
0.015 V
0.25
0.030 V Available
S-8204AAD-TCT1y 3.800
0.025 V 3.600
0.050 V 2.00
0.080 V 2.30
0.100 V 0.30
0.015 V
0.25
0.030 V Available
S-8204AAE-TCT1y 4.250
0.025 V 4.050
0.050 V 2.40
0.080 V 2.70
0.100 V 0.20
0.015 V
0.15
0.030 V Unavailable
S-8204AAF-TCT1y 4.200
0.025 V 4.100
0.050 V 2.70
0.080 V 2.90
0.100 V 0.10
0.015 V
0.10
0.030 V Available
S-8204AAG-TCT1y 3.800
0.025 V 3.650
0.050 V 2.20
0.080 V 2.50
0.100 V 0.10
0.015 V
0.10
0.030 V Available
S-8204AAH-TCT1y 3.800
0.025 V 3.600
0.050 V 2.00
0.080 V 2.30
0.100 V 0.10
0.015 V
0.05
0.030 V Available
S-8204AAI-TCT1y 3.800
0.025 V 3.600
0.050 V 2.00
0.080 V 2.30
0.100 V 0.05
0.015 V
0.05
0.030 V Available
S-8204AAJ-TCT1U 4.350
0.025 V 4.150
0.050 V 2.50
0.080 V 3.00
0.100 V 0.30
0.015 V
0.20
0.030 V Unavailable
S-8204AAK-TCT1U 4.300
0.025 V 4.100
0.050 V 2.30
0.080 V 2.60
0.100 V 0.15
0.015 V
0.15
0.030 V Unavailable
Remark 1. Please contact our sales office for products with detection voltage values other than those specified
above.
2. y: S or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
4
Pin Configuration
1. 16-Pin TSSOP
5
4
6
8
7
2
3
1
12
13
11
9
10
15
14
16
Top view
Figure 2
Table 3
Pin No. Symbol Description
1 COP Connection pin of charge control FET gate (Nch open-drain output)
2 VMP Voltage detection pin between VDD pin and VMP pin
3 DOP Connection pin of discharge control FET gate (CMOS output)
4 VINI
Voltage detection pin between VSS pin and VINI pin
Discharge overcurrent 1 / 2 detection pin, load short-circuit detection pin
Charge overcurrent detection pin
5 CDT Capacitor connection pin for delay for overdischarge detection
6 CCT Capacitor connection pin for delay for overcharge detection
7 CIT Capacitor connection pin for delay for discharge overcurrent 1 / 2,
capacitor connection pin for delay for charge overcurrent detection
8 SEL
Pin for switching 3-series or 4-series cell
VSS level: 3-series cell
VDD level: 4-series cell
9 VSS Input pin for negative power supply,
Connection pin for negative voltage of battery 4
10 VC4 Connection pin for negative voltage of battery 4
11 VC3 Connection pin for negative voltage of battery 3,
Connection pin for positive voltage of battery 4
12 VC2 Connection pin for negative voltage of battery 2,
Connection pin for positive voltage of battery 3
13 VC1 Connection pin for negative voltage of battery 1,
Connection pin for positive voltage of battery 2
14 VDD Input pin for positive power supply,
Connection pin for positive voltage of battery 1
15 CTLD Discharge FET control pin
16 CTLC Charge FET control pin
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
5
Absolute Maximum Ratings
Table 4
(Ta =
25C unless otherwise specified)
Item Symbol Applied Pin Absolute Maximum Rating Unit
Input voltage between VDD pin
and VSS pin VDS VSS 0.3 to VSS 24 V
Input pin voltage VIN
VC1, VC2, VC3, VC4,
CTLC, CTLD, SEL,
CCT, CDT, CIT, VINI
VSS 0.3 to VDD 0.3 V
VMP pin input voltage VVMP VMP VSS 0.3 to VSS 24 V
DOP pin output voltage VDOP DOP VSS 0.3 to VDD 0.3 V
COP pin output voltage VCOP COP VSS 0.3 to VSS 24 V
Power dissipation PD 400
(When not mounted on board)
mW
1100*1 mW
Operation ambient temperature Top
r
40 to 85 C
Storage temperature Tst
g
40 to 125 C
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Board name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
0 50 100
150
800
400
0
Power Dissipation (P
D
) [mW]
Ambient Temperature (Ta) [C]
1000
600
200
1200
Figure 3 Power Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
6
Electrical Characteristics
Table 5 (1 / 2)
(Ta =
25C unless otherwise specified)
Item
Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Detection Voltage
Overcharge detection voltage n
(n = 1, 2, 3, 4) V
CUn
3.8 V to 4.6 V, adjustable,
50 mV step
V
CUn
0.025 V
CUn
V
CUn
0.025 V 2
Overcharge release voltage n
(n = 1, 2, 3, 4) V
CLn
3.6 V to 4.6 V,
adjustable,
50 mV step
V
CL
V
CU
V
CLn
0.05 V
CLn
V
CLn
0.05 V 2
V
CL
= V
CU
V
CLn
0.025 V
CLn
V
CLn
0.025 V 2
Overdischarge detection voltage n
(n = 1, 2, 3, 4) V
DLn
2.0 V to 3.0 V, adjustable,
100 mV step
V
DLn
0.08 V
DLn
V
DLn
0.08 V 2
Overdischarge release voltage n
(n = 1, 2, 3, 4) V
DUn
2.0 V to 3.4 V,
adjustable,
100 mV step
V
DL
V
DU
V
DUn
0.10 V
DUn
V
DUn
0.10 V 2
V
DL
= V
DU
V
DUn
0.08 V
DUn
V
DUn
0.08 V 2
Discharge overcurrent detection
voltage 1 V
DIOV1
0.05 V to 0.30 V, adjustable V
DIOV1
0.015 V
DIOV1
V
DIOV1
0.015 V 2
Discharge overcurrent detection
voltage 2 V
DIOV2
0.4 0.5 0.6 V 2
Load short-circuit detection voltage
V
SHORT
0.7 1.0 1.3 V 2
Charge overcurrent detection
voltage V
CIOV
0.25 V to
0.05 V, adjustable V
CIOV
0.03 V
CIOV
V
CIOV
0.03 V 2
Temperature coefficient 1
*1
T
COE1
Ta = 0°C to 50°C
*
3
1.0 0 1.0 mV/°C 2
Temperature coefficient 2
*2
T
COE2
Ta = 0°C to 50°C
*
3
0.5 0 0.5 mV/°C 2
Delay Time Function
*
4
CCT pin internal resistance R
INC
V1 = 4.7 V, V2 = V3 = V4 = 3.5 V
6.15 8.31 10.2 M
3
CDT pin internal resistance R
IND
V1 = 1.5 V, V2 = V3 = V4 = 3.5 V
615 831 1020
k
3
CIT pin internal resistance 1 R
INI1
V1 = V2 = V3 = V4 = 3.5 V
123 166 204 k
3
CIT pin internal resistance 2 R
INI2
V1 = V2 = V3 = V4 = 3.5 V
12.3 16.6 20.4 k
3
CCT pin detection voltage V
CCT
V
DS
= 15.2 V,
V1 = 4.7 V, V2 = V3 = V4 = 3.5 V
V
DS
0.68
V
DS
0.70
V
DS
0.72 V 3
CDT pin detection voltage V
CDT
V
DS
= 12.0 V,
V1 = 1.5 V, V2 = V3 = V4 = 3.5 V
V
DS
0.68
V
DS
0.70
V
DS
0.72 V 3
CIT pin detection voltage V
CIT
V
DS
= 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
V
DS
0.68
V
DS
0.70
V
DS
0.72 V 3
Load short-circuit detection
delay time t
SHORT
FET gate capacitance = 2000 pF 100 300 600
s 3
0 V Battery Charge Function
0 V battery charge starting
charger voltage V
0CHA
0 V battery charge function
"available"
0.8 1.5 V 4
0 V battery charge inhibition
battery voltage V
0INH
0 V battery charge function
"inhibition" 0.4 0.7 1.1 V 4
Internal Resistance
Resistance between
VMP pin and VDD pin R
VMD
0.5 1 1.5
M
5
Resistance between
VMP pin and VSS pin R
VMS
450 900 1800
k
5
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
7
Table 5 (2 / 2)
(Ta =
25C unless otherwise specified)
Item
Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Input Voltage
Operation voltage between VDD
pin and VSS pin V
DSOP
Fixed output voltage of DOP pin
and COP pin 2
22 V 2
CTLC pin input voltage "H" V
CTLCH
V1 = V2 = V3 = V4 = 3.5 V
0.91 V 2
CTLC pin input voltage "L" V
CTLCL
V1 = V2 = V3 = V4 = 3.5 V 0.59
V 2
CTLD pin input voltage "H" V
CTLDH
V1 = V2 = V3 = V4 = 3.5 V
0.91 V 2
CTLD pin input voltage "L" V
CTLDL
V1 = V2 = V3 = V4 = 3.5 V 0.59
V 2
SEL pin input voltage "H" V
SELH
V
DS
= 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
V
DS
0.8
V 2
SEL pin input voltage "L" V
SELL
V
DS
= 14.0 V,
V1 = V2 = V3 = V4 = 3.5 V
V
DS
0.2 V 2
Input Current
Current consumption during
operation I
OPE
V1 = V2 = V3 = V4 = 3.5 V
15 33
A 1
Current consumption during
power-down I
PDN
V1 = V2 = V3 = V4 = 1.5 V
0.1
A
1
VC1 pin current I
VC1
V1 = V2 = V3 = V4 = 3.5 V
0.3 0 0.3
A
5
VC2 pin current I
VC2
V1 = V2 = V3 = V4 = 3.5 V
0.3 0 0.3
A
5
VC3 pin current I
VC3
V1 = V2 = V3 = V4 = 3.5 V
0.3 0 0.3
A
5
VC4 pin current I
VC4
V1 = V2 = V3 = V4 = 3.5 V
6.0
3.0
0.5
A
5
CTLC pin current "H" I
CTLCH
V1 = V2 = V3 = V4 = 3.5 V,
maximum current flowing into
CTLC pin
3.0 10.0 20.0
A
5
CTLC pin current "L" I
CTLCL
V1 = V2 = V3 = V4 = 3.5 V,
V
CTLC
= V
SS
0.8
0.6
0.4
A 5
CTLD pin current "H" I
CTLDH
V1 = V2 = V3 = V4 = 3.5 V,
maximum current flowing into
CTLD pin
3.0 10.0 20.0
A
5
CTLD pin current "L" I
CTLDL
V1 = V2 = V3 = V4 = 3.5 V,
V
CTLD
= V
SS
0.8
0.6
0.4
A 5
SEL pin current "H" I
SELH
V1 = V2 = V3 = V4 = 3.5 V,
V
SEL
= V
DD
0.1
A
5
SEL pin current "L" I
SELL
V1 = V2 = V3 = V4 = 3.5 V,
V
SEL
= V
SS
0.1
A
5
Output Current
COP pin leakage current I
COH
V
COP
= 22 V
0.1
A
5
COP pin sink current I
COL
V
COP
= V
SS
0.5 V 10
A
5
DOP pin source current I
DOH
V
DOP
= V
DD
0.5 V 10
A
5
DOP pin sink current I
DOL
V
DOP
= V
SS
0.5 V 10
A
5
*1. Voltage temperature coefficient 1: Overcharge detection voltage
*2. Voltage temperature coefficient 2: Discharge overcurrent detection voltage 1
*3. Since products are not screened at high and low temperature, the specification for this temperature range is
guaranteed by design, not tested in production.
*4. Details of delay time function is described in " Operation".
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
8
Test Circuit
This chapter describes how to test the S-8204A Series. In case of selecting to use it for 4-series cell battery,
set SEL pin = VDD. For 3-series cell battery, set SEL pin = VSS and short between VC3 pin and VC4 pin.
1. Current consumption during operation and power-down
(Test circuit 1)
1. 1 Current consumption during operation (IOPE)
The current at the VSS pin when V1 = V2 = V3 = V4 = 3.5 V and VVMP = VDD is the current
consumption during operation (IOPE).
1. 2 Current consumption during power-down (IPDN)
The current at the VSS pin when V1 = V2 = V3 = V4 = 1.5 V and VVMP = VSS is the current
consumption during power-down (IPDN).
2. Overcharge detection voltage, overcharge release voltage, overdischarge detection voltage,
overdischarge release voltage, discharge overcurrent detection voltage 1, discharge overcurrent
detection voltage 2, load short-circuit detection voltage, charge overcurrent detection voltage,
CTLC pin input voltage "H", CTLC pin input voltage "L", CTLD pin input voltage "H", CTLD pin
input voltage "L", SEL pin input voltage "H", SEL pin input voltage "L"
(Test circuit 2)
Confirm both COP pin and DOP pin are in "L" (its voltage level is VDS 0.1 V or less) after setting VVMP
= VSEL = VDD, VVINI = VCTLC = VCTLD = VSS, CCT pin = Open, CDT pin = Open, CIT pin = Open, V1 = V2
= V3 = V4 = 3.5 V. (This status is referred to as initial status.)
2. 1 Overcharge detection voltage (VCU1), overcharge release voltage (VCL1)
The overcharge detection voltage (VCU1) is a voltage at V1; when the COP pin's voltage is set to "H"
(its voltage level is VDS 0.9 V or more) after increasing a voltage at V1 gradually from the initial
status. After that, decreasing a voltage at V1 gradually, a voltage at V1 when the COP pin's voltage is
set to "L"; is the overcharge release voltage (VCL1).
2. 2 Overdischarge detection voltage (VDL1), overdischarge release voltage (VDU1)
The overdischarge detection voltage (VDL1) is a voltage at V1; when the DOP pin's voltage is set to "H"
after decreasing a voltage at V1 gradually from the initial status. After that, increasing a voltage at V1
gradually, a voltage at V1 when the DOP pin's voltage is set to "L"; is the overdischarge release
voltage (VDU1).
By changing the voltage at Vn (n = 2 to 4), users can define the overcharge detection voltage (VCUn),
the overcharge release voltage (VCLn), the overdischarge detection voltage (VDLn), the overdischarge
release voltage (VDUn) as well when n = 1.
2. 3 Discharge overcurrent detection voltage 1 (VDIOV1)
The discharge overcurrent detection voltage 1 (VDIOV1) is the VINI pin's voltage; when the DOP pin's
voltage is set to "H" after increasing the VINI pin's voltage gradually from the initial status.
2. 4 Discharge overcurrent detection voltage 2 (VDIOV2)
The discharge overcurrent detection voltage 2 (VDIOV2) is a voltage at the VINI pin; when a flowing
current from the CIT pin reaches 500 A or more after increasing the VINI pin's voltage gradually from
the initial status.
2. 5 Load short-circuit detection voltage (VSHORT)
The load short-circuit detection voltage (VSHORT) is the VINI pin's voltage; when the DOP pin's voltage
is set to "H" after increasing the VINI pin's voltage gradually from the initial status after setting the CIT
pin's voltage to the VSS level.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
9
2. 6 Charge overcurrent detection voltage (VCIOV)
The charge overcurrent detection voltage (VCIOV) is the VINI pin's voltage; when the COP pin's voltage
is set to "H" after decreasing the VINI pin's voltage gradually from the initial status.
2. 7 CTLC pin input voltage "H" (VCTLCH), CTLC pin input voltage "L" (VCTLCL)
The CTLC pin input voltage "H" (VCTLCH) is the CTLC pin's voltage; when the COP pin's voltage is set
to "H" after increasing the CTLC pin's voltage gradually from the initial status. After that, decreasing
the CTLC pin's voltage gradually, the CTLC pin's voltage when the COP pin's voltage is set to "L"; is
the CTLC pin input voltage "L" (VCTLCL).
2. 8 CTLD pin input voltage "H" (VCTLDH), CTLD pin input voltage "L" (VCTLDL)
The CTLD pin input voltage "H" (VCTLDH) is the CTLD pin's voltage; when the DOP pin's voltage is set
to "H" after increasing the CTLD pin's voltage gradually from the initial status. After that, decreasing
the CTLD pin's voltage gradually, the CTLD pin's voltage when the DOP pin's voltage is set to "L"; is
the CTLD pin input voltage "L" (VCTLDL).
2. 9 SEL pin input voltage "H" (VSELH), SEL pin input voltage "L" (VSELL)
Start from the initial status, set V4 = 0 V. Confirm the DOP pin is in "H". After that, decreasing the SEL
pin's voltage gradually, the SEL pin's voltage when the DOP pin's voltage is set to "L"; is the SEL pin
input voltage "L" (VSELL). After that, increasing the SEL pin's voltage gradually, the SEL pin's voltage
when the DOP pin's voltage is set to "H"; is the SEL pin input voltage "H" (VSELH).
3. CCT pin internal resistance, CDT pin internal resistance, CIT pin internal resistance 1, CIT pin
internal resistance 2, CCT pin detection voltage, CDT pin detection voltage, CIT pin detection
voltage, short circuit detection voltage delay time
(Test circuit 3)
Confirm both COP pin and DOP pin are in "L" after setting VVMP = VSEL = VDD, VVINI = VCTLC = VCTLD =
CCT = CDT = CIT = VSS, V1 = V2 = V3 = V4 = 3.5 V. (This status is referred to as initial status.)
3. 1 CCT pin internal resistance (RINC)
The CCT pin internal resistance (RINC) is RINC = VDS / ICCT, ICCT is the current which flows from the CCT
pin when setting V1 = 4.7 V from the initial status.
3. 2 CDT pin internal resistance (RIND)
The CDT pin internal resistance (RIND) is RIND = VDS / ICDT, ICDT is the current which flows from the CDT
pin when setting V1 = 1.5 V from the initial status.
3. 3 CIT pin internal resistance 1 (RINI1)
The CIT pin internal resistance 1 (RINI1) is RINI1 = VDS / ICIT1, ICIT1 is the current which flows from the CIT
pin when setting VVINI = VDIOV1 max. 0.05 V from the initial status.
3. 4 CIT pin internal resistance 2 (RINI2)
The CIT pin internal resistance 2 (RINI2) is RINI2 = VDS / ICIT2, ICIT2 is the current which flows from the CIT
pin when setting VVINI = VDIOV2 max. 0.05 V from the initial status.
3. 5 CCT pin detection voltage (VCCT)
The CCT pin detection voltage (VCCT) is the voltage at the CCT pin when the COP pin's voltage is set
to "H" (voltage VDS 0.9 V or more) after increasing the CCT pin's voltage gradually, after setting V1 =
4.7 V from the initial status.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
10
3. 6 CDT pin detection voltage (VCDT)
The CDT pin detection voltage (VCDT) is the voltage at the CDT pin when the DOP pin's voltage is set
to "H" (voltage VDS 0.9 V or more) after increasing the CDT pin's voltage gradually, after setting V1 =
1.5 V from the initial status.
3. 7 CIT pin detection voltage (VCIT)
The CIT pin detection voltage (VCIT) is the voltage at the CIT pin when the DOP pin's voltage is set to
"H" (voltage VDS 0.9 V or more) after increasing the CIT pin's voltage gradually, after setting VVINI =
VDIOV1 max. 0.05 V from the initial status.
3. 8 Load short-circuit detection delay time (tSHORT)
Load short-circuit detection delay time (tSHORT) is a period in which the DOP pin's voltage changes from
"L" to "H" by changing the VINI pin's voltage instantaneously from the initial status to VSHORT max.
0.05 V.
4. 0 V battery charge starting charger voltage (0 V battery charge function "available"), 0 V Battery
charge inhibition battery voltage (0 V battery charge function "inhibition")
(Test circuit 4)
According to user's selection of the function to charge 0 V battery, either function of 0 V battery charge
starting charger voltage or 0 V battery charge inhibition battery voltage is applied to each product.
4. 1 0 V battery charge starting charger voltage (V0CHA) (0V battery charge function "available")
In this 0 V battery charge starting charger voltage, when V1 = V2 = V3 = V4 = 0 V, VVMP = V0CHA
max., the COP pin's voltage is V0CHA max. 1 V or less.
4. 2 0 V battery charge inhibition battery voltage (V0CHA) (0V battery charge function "inhibition")
In this 0 V battery charge inhibition battery voltage, when V1 = V2 = V3 = V4 = V0INH min., VVMP = 22
V, the COP pin's voltage is VVMP 1 V or more.
5. Resistance between VMP pin and VDD pin, resistance between VMP pin and VSS pin, VC1 pin
current, VC2 pin current, VC3 pin current, VC4 pin current, CTLC pin current "H", CTLC pin
current "L", CTLD pin current "H", CTLD pin current "L", SEL pin current "H", SEL pin current
"L", COP pin leakage current, COP pin sink current, DOP pin source current, DOP pin sink
current
(Test circuit 5)
Set VVMP = VSEL = VDD, VVINI = VCTLC = VCTLD = VSS, V1 = V2 = V3 = V4 = 3.5 V, set other pins open.
(This status is referred to as initial status.)
5. 1 Resistance between VMP pin and VDD pin (RVMD)
The value of resistance between VMP pin and VDD pin (RVMD) can be defined by RVMD = VDS / IVMD by
using the VMP pin's current (IVMD) when VVINI = 1.5 V and VVMP = VSS after the initial status.
5. 2 Resistance between VMP pin and VSS pin (RVMS)
The value of resistance between VMP pin and VSS pin (RVMS) can be defined by RVMS = VDS / IVMS by
using the VMP pin's current (IVMS) when V1 = V2 = V3 = V4 = 1.8 V after the initial status.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
11
5. 3 VC1 pin current (IVC1), VC2 pin current (IVC2), VC3 pin current (IVC3), VC4 pin current (IVC4)
In the initial status, each current flows in the VC1 pin, VC2 pin, VC3 pin, VC4 pin is the VC1 pin
current (IVC1), the VC2 pin current (IVC2), the VC3 pin current (IVC3), the VC4 pin current (IVC4),
respectively.
5. 4 CTLC pin current "H" (ICTLCH), CTLC pin current "L" (ICTLCL)
In the initial status, the current which flows in the CTLC pin is the CTLC pin current "L" (ICTLCL). After
that, increasing the CTLC pin's voltage gradually, the maximum current which flows in the CTLC pin is
the CTLC pin current "H" (ICTLCH).
5. 5 CTLD pin current "H" (ICTLDH), CTLD pin current "L" (ICTLDL)
In the initial status, a current which flows in the CTLD pin is the CTLD pin current "L" (ICTLDL). After
that, increasing the CTLD pin's voltage gradually, the maximum current which flows in the CTLD pin is
the CTLD pin current "H" (ICTLDH).
5. 6 SEL pin current "H" (ISELH), SEL pin current "L" (ISELL)
In the initial status, a current which flows in the SEL pin is the SEL pin current "H" (ISELH). After that, a
current which flows in the SEL pin when setting VSEL = VSS is the SEL pin current "L" (ISELL).
5. 7 COP pin Leakage current (ICOH), COP pin sink current (ICOL)
Start from the initial status, set VCOP = VSS 0.5 V, a current which flows in the COP pin is the COP pin
sink current (ICOL). After that, a current which flows in the COP pin when setting V1 = V2 = V3 = V4 =
5.5 V, VCOP = VDD is the COP pin leakage current (ICOH).
5. 8 DOP pin source current (IDOH), DOP pin sink current (IDOL)
Start from the initial status, set VDOP = VSS 0.5 V, a current which flows in the DOP pin is the DOP pin
sink current (IDOL). After that, a current which flows in the DOP pin when setting V1 = V2 = V3 = V4 =
1.8 V, VDOP = VDD 0.5 V is the DOP pin source current (IDOH).
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
12
C1 =
0.1 F
V1
V2
V4
V3
A
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16
VDD
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLC
CTLD
VSS 9
S-8204A
SEL
10
Figure 4 Test Circuit 1
C1 =
0.1 F
V1
V2
V4
V3
V
V
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16
VDD
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLC
CTLD
VSS 9
S-8204A
SEL
10
A
Figure 5 Test Circuit 2
C1 =
0.1 F
V1
V2
V4
V3
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16
VDD
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLC
CTLD
VSS 9
S-8204A
SEL
10
V V
A
A
A
Figure 6 Test Circuit 3
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
13
C1 =
0.1 F
V1
V2
V4
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16
VDD
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLC
CTLD
VSS 9
S-8204A
SEL
10
V
V3
Figure 7 Test Circuit 4
C1 =
0.1 F
V1
V2
V4
V3
A
A
A
A
A
A
A 1 COP
2 VMP
3 DOP
4 VINI
5 CDT
6 CCT
7 CIT
8
16
VDD
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLC
CTLD
VSS 9
S-8204A
SEL
10
A
A
A
Figure 8 Test Circuit 5
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
14
Operation
Remark Refer to " Connection Example of Battery Protection IC".
1. Normal status
In the S-8204A Series, both of COP pin and DOP pin get the VSS level; when the voltage of each of the
batteries is in the range of overdischarge detection voltage (VDLn) to overcharge detection voltage (VCUn),
and due to the discharge or charge current, the VINI pin's voltage is in the range of charge overcurrent
detection voltage (VCIOV) to discharge overcurrent detection voltage 1 (VDIOV1). This is the normal status.
At this time, the charge FET and the discharge FET are on.
2. Overcharge status
In the S-8204A Series, when the voltage of one of the batteries increases to the level of more than VCUn,
the COP pin is set in high impedance. This is the overcharge status. The COP pin is pulled up to EB by
an external resistor so that the charge FET is turned off and it stops charging.
This overcharge status is released if either condition mentioned below is satisfied;
(1) In case that the VMP pin voltage is set 39 / 40 VDS or more; the voltage of each of the batteries is
in the level of overcharge release voltage (VCLn) or less.
(2) In case that the VMP pin voltage is set 39 / 40 VDS or less; the voltage of each of the batteries is
in the level of VCUn or less.
3. Overdischarge status
In the S-8204A Series, when the voltage of one of the batteries decreases to the level of less than VDLn,
the DOP pin voltage gets the VDD level. This is the overdischarge status. At this time, the discharge FET
is turned off and it stops discharging.
This overdischarge status is released / maintained if either condition mentioned below is satisfied;
(1) To release; the VMP pin voltage is in the level of more than VDD, the voltage of each of the
batteries is in the VDLn level or more.
(2) To release; the VMP pin voltage is VDS / 2 or more and the VMP pin voltage is in the level of less
than VDD; the voltage of each of the batteries is in the level of overdischarge release voltage (VDUn)
or more.
(3) The VMP pin voltage is VDS / 2 or less, the S-8204A Series maintains the power-down function.
3. 1 Power-down function
In the S-8204A Series, when it reaches the overdischarge status, the VMP pin is pulled down to the
VSS level by a resistor between VMP pin and VSS pin (RVMS). If the VMP pin voltage decreases to the
level of VDS / 2 or less, the power-down function starts to operate and almost every circuit in the
S-8204A Series stops working.
The power-down function is released if the following condition is satisfied.
(1) The VMP pin voltage gets VDS / 2 or more.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
15
4. Discharge overcurrent status
In the S-8204A Series, in batteries in the normal status, the discharging current increases more than a
certain value. As a result, if the status in which the VINI pin voltage increases to the level of VDIOV1 or
more, the DOP pin gets the VDD level. This is the discharge overcurrent status. At this time, the discharge
control FET is turned off and it stops discharging.
The S-8204A Series has three levels for discharge overcurrent detection (VDIOV1, VDIOV2, VSHORT). In the
status of discharge overcurrent, the COP pin is set in high impedance. The VMP pin is pulled up to the
VDD level by a resistor between VMP pin and VDD pin (RVMD).
The S-8204A Series' operations against discharge overcurrent detection voltage 2 (VDIOV2) and load short-
circuit detection voltage (VSHORT) are as well in VDIOV1.
The discharge overcurrent status is released if the following condition is satisfied.
(1) The VMP pin voltage gets VDS 1.2 V (typ.) or more.
5. Charge overcurrent status
In the S-8204A Series, in batteries in the normal status, the charge current increases more than a certain
value. As a result, if the status in which the VINI pin voltage decreases to the level of VCIOV or less, the
COP pin is set in high impedance. This is the charge overcurrent status. At this time, the charge control
FET is turned off and it stops charging.
In this charge overcurrent status, the VMP pin is pulled up to the VDD level by RVMD. Also in the
overdischarge status, the function of charge overcurrent detection works.
The charge overcurrent status is released if the following condition is satisfied.
(1) The VMP pin voltage gets VDS or less.
6. 0 V battery charge function
In the S-8204A Series, regarding how to charge a discharged battery (0 V battery), users are able to
select either function mentioned below.
(1) Allow to charge a 0 V battery (enable to charge a 0 V battery)
A 0 V battery is charged;
when the voltage of a charger is 0 V battery starting charger voltage (V0CHA) or more.
(2) Inhibit charging a 0 V battery (unable to charge a 0 V battery)
A 0 V battery is not charged;
when the voltage of a charger is 0 V battery charge inhibition battery voltage (V0INH) or less.
Caution When the VDD pin voltage is less than the minimum value of operation voltage between
VDD pin and VSS pin (VDSOP), the operation of the S-8204A Series is not assured.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
16
7. Delay time setting
In the S-8204A Series, users are able to set delay time for the period; from detecting the voltage of one of
the batteries or detecting changes in the voltage at the VINI pin, to the output to the COP pin, DOP pin.
Each delay time is determined by a resistor in the S-8204A Series and an external capacitor.
In the overchage detection, when the voltage of one of the batteries gets VCUn or more, the S-8204 starts
charging to the CCT pin's capacitor (CCCT) via the CCT pin's internal resistor (RINC). After a certain period,
the COP pin is set in high impedance if the voltage at the CCT pin reaches the CCT pin detection voltage
(VCCT). This period is overcharge detection delay time (tCU).
tCU is calculated using the following equation (VDS = V1 V2 V3 V4).
tCU [s] = ln (1 VCCT / VDS ) CCCT [F] RINC [M]
= ln (1 0.7 (typ.)) CCCT [F] 8.31 [M] (typ.)
= 10.0 [M] (typ.) CCCT [F]
Overdischarge detection delay time (tDL), discharge overcurrent detection delay time 1 (tDIOV1), discharge
overcurrent detection delay time 2 (tDIOV2), charge overcurrent detection delay time (tCIOV) are calculated
using the following equations as well.
tDL [ms] = ln (1 VCDT / VDS) CCDT [F] RIND [k]
tDIOV1 [ms] = ln (1 VCIT / VDS) CCIT [F] RINI1 [k]
tDIOV2 [ms] = ln (1 VCIT / VDS) CCIT [F] RINI2 [k]
tCIOV [ms] = ln (1 VCIT / VDS) CCIT [F] RINI1 [k]
In case CCCT = CCDT = CCIT = 0.1 [F], each delay time tCU, tDL, tDIOV1, tDIOV2, tCIOV is calculated as follows.
tCU [s] = 10.0 [M] (typ.) 0.1 [F] = 1.0 [s] (typ.)
tDL [ms] = 1000 [k] (typ.) 0.1 [F] = 100 [ms] (typ.)
tDIOV1 [ms] = 200 [k] (typ.) 0.1 [F] = 20 [ms] (typ.)
tDIOV2 [ms] = 20 [k] (typ.) 0.1 [F] = 2.0 [ms] (typ.)
tCIOV [ms] = 200 [k] (typ.) 0.1 [F] = 20 [ms] (typ.)
Load short-circuit detection delay time (tSHORT) is fixed internally.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
17
8. CTLC pin and CTLD pin
The S-8204A Series has two pins to control output voltage.
The CTLC pin controls the output voltage from the COP pin, the CTLD pin controls the output voltage
from the DOP pin. Thus it is possible for users to control the output voltages from the COP pin and DOP
pin independently. These controls precede the battery protection circuit.
Table 6 Conditions Set by CTLC Pin
CTLC Pin COP Pin
"H"*1 "High-Z"
Open*2 "High-Z"
"L"*3 Normal status*4
*1. "H"; CTLC VCTLCH
*2. Pulled up by ICTLCL
*3. "L"; CTLC VCTLCL
*4. The status is controlled by the voltage detection circuit.
Table 7 Conditions Set by CTLD Pin
CTLD Pin DOP Pin
"H"*1 V
DD level
Open*2 V
DD level
"L"*3 Normal status*3
*1. "H"; CTLD VCTLDH
*2. Pulled up by ICTLDL
*3. "L"; CTLD VCTLDL
*4. The status is controlled by the voltage detection circuit.
Caution Note that when the power supply fluctuates, unexpected behavior might occur if an
electrical potential is generated between the potentials of "L" level input to the CTLC pin
/ CTLD pin and IC's VSS by external filters RVSS and CVSS.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
18
9. SEL pin
The S-8204A Series has a pin to switch-control the protection for 3-cell or 4-cell battery.
The overdischarge detection for V4-cell is inhibited by setting the SEL pin "L", so that short-circuiting the
V4 cell does not allow the overdischarge detection. This setting makes it possible to use the S-8204A
Series for 3-cell protection. The SEL pin precedes the battery protection circuit. Be sure to use the SEL
pin in "H" or "L".
Table 8 Protect Conditions Set by SEL Pin
SEL Pin Condition
"H"*1 4-cell protection
Open Indefinite
"L"*2 3-cell protection
*1. "H"; SEL VSELH
*2. "L"; SEL VSELL
In cascade connection, it is possible to use the S-8204A Series for protecting 6-cell, 7-cell or 8-cell
battery by combining the electrical level of SEL pin.
Table 9 Conditions Set by SEL Pin in Cascade Connection
SEL pin in S-8204A (1) SEL pin in S-8204A (2) Condition
"L"1 "L"*1 6-series cell protection
"L"*1 "H"2 7-series cell protection
"H"*2 "H"*2 8-series cell protection
*1. "L"; SEL VSELL
*2. "H"; SEL VSELH
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
19
Timing Chart (Circuits in Figure 12, Figure 13)
1. Overcharge detection and overdischarge detection
(n = 1 to 4)
VCUn
VDUn
VDLn
VCLn
Battery voltage
VSS
COP
p
in volta
g
e
DOP pin voltage
VSS
Charger connection
Load connection
Status
*1
39 / 40 VDD
VSS
VMP pin voltage 1 / 2 VDD
VDD
VEB
VEB
Overcharge detection
delay time (tCU)
(1) (2) (1) (3) (1)
High-Z
Overdischarge detection
delay time (tDL)
VDD
(4)
High-Z
*1. (1): Normal status
(2): Overcharge status
(3): Overdischarge status
(4): Power-down status
Remark The charger is assumed to charge with a constant current. VEB indicates the open voltage of the
charger.
Figure 9
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
20
2. Discharge overcurrent detection
VCUn
VDUn
VDLn
(n = 1 to 4)
VCLn
Battery voltage
VHC
VHD
VDD
DOP pin voltage
VSS
High-Z
VEB
VSS
COP pin voltage
VDD
VSS
VMP pin voltage
VSHORT
VDIOV2
VSS
VINI pin voltage
VDD
VDIOV1
Load connection
Status
*1
Discharge overcurrent detection
delay time 1 (t
DIOV1
)
(1) (2) (1) (1)
Discharge overcurrent detection
dela
y
time 2
(
t
DIOV2
)
Load short-circuit detection
delay time (t
SHORT
)
(2) (1) (2)
High-Z
High-Z
*1. (1): Normal status
(2): Discharge overcurrent status
Remark The charger is assumed to charge with a constant current. VEB indicates the open voltage of the
charger.
Figure 10
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
21
3. Charge overcurrent detection
VCUn
VDUn
VDLn
(n = 1 to 4)
VCLn
Battery voltage
VHC
VHD
VDD
DOP pin voltage
VSS
VEB
VSS
COP pin voltage
VDD
VSS
VMP pin voltage
VINI pin voltage
VDD
VDIOV1
Charger connection
Status
*1
(3) (2) (1) (1)
(2)
VEB
VSS
VCIOV
High-Z
Charge overcurrent detection delay time (t
CIOV
)
(1)
Charge overcurrent detection delay time (t
CIOV
)
High-Z
(4)
High-Z
*1. (1): Normal status
(2): Charge overcurrent status
(3): Overdischarge status
(4): Power-down status
Remark The charger is assumed to charge with a constant current. VEB indicates the open voltage of the
charger.
Figure 11
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
22
Connection Examples of Battery Protection IC
1. 3-series cell
EB
RCOP
RVMP RDOP
RVINI
CCDT CCCT
EB
1 COP
2 VMP
3 DOP
4 VINI
5 CDT
6 CCT
7 CIT
8
16CTLC
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLD
VDD
VSS 9
S-8204A
RVC1
CVC2
CVC3
CVSS
CVC1
RVC3
RVSS
RSENSE
CTLC
SEL
10
Pch FET1
(Charge FET)
Pch FET2
(Discharge FET)
RSEL
CCIT
RVC4
RCTLC
CTLD
RCTLD
RVC2
Figure 12
2. 4-series cell
EB
RCOP
RVMP RDOP
RVINI
CCDT CCCT
EB
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16CTLC
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLD
VDD
VSS 9
S-8204A
RVC1
CVC2
CVC3
CVSS
CVC1
RVC3
RVSS
RSENSE
CTLC
SEL
10
Pch FET1
(Charge FET)
Pch FET2
(
Dischar
g
e FET
)
RSEL
CCIT
RVC4
RCTLC
CTLD
RCTLD
RVC2
CVC4
Figure 13
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
23
Table 10 Constants for External Components (Circuits in Figure 12, Figure 13)
Symbol Min. Typ. Max. Unit
RVC1
*1 0.51 1 1 k
RVC2
*1 0.51 1 1 k
RVC3
*1 0.51 1 1 k
RVC4
*1 0.51 1 1 k
RDOP 2 5.1 10 k
RCOP 0.1 1 1 M
RVMP 1 5.1 10 k
RCTLC 1 1 10 k
RCTLD 1 1 10 k
RVINI 1 1 10 k
RSEL 1 1 100 k
RSENSE 0
m
RVSS
*1 22 47 100
CVC1
*1 0 47 100 nF
CVC2
*1 0 47 100 nF
CVC3
*1 0 47 100 nF
CVC4
*1 0 47 100 nF
CCCT 0.01 0.1
F
CCDT 0.01 0.1
F
CCIT 0.01 0.1
F
CVSS
*1 0 1 2.2 F
Pch FET1
Pch FET2
*1. Set up a filter constant to be RVSS CVSS = 47 F and to be RVC1 CVC1 = RVC2 CVC2 = RVC3 CVC3
= RVC4 CVC4 = RVSS CVSS.
Caution 1. The above constants may be changed without notice.
2. It is recommended that filter constants between VDD pin and VSS pin should be set
approximately to 47 F .
e.g., CVSS RVSS = 1.0 F 47 = 47 F
Sufficient evaluation of transient power supply fluctuation and overcurrent protection
function with the actual application is needed to determine the proper constants.
Contact our sales office in case the constants should be set to other than 47 F • .
3. It has not been confirmed whether the operation is normal in circuits other than the
above example of connection. In addition, the example of connection shown above and
the constants do not guarantee proper operation. Perform thorough evaluation using an
actual application to set the constant.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
24
3. 7-Series Cell
EB
RCOP
RDOP
RVINI1
CCDT1
CCCT1
EB
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16CTLC
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLD
VDD
VSS 9
S-8204A (1)
RVC1
CVC2
CVC3
CVSS1
CVC1
RVC3
RVSS1
SEL
10
Charge FET Discharge FET
RCIT1
RVC4
RVC2
RSEL1
RINV3
RVINI2
CCDT2
CCCT2
1COP
2VMP
3DOP
4VINI
5 CDT
6 CCT
7CIT
8
16CTLC
15
VC1
14
VC2
13
VC3
12
VC4
11
CTLD
VDD
VSS 9
RVC5
CVC6
CVC7
CVSS2
CVC5
RVC7
RVSS2
SEL
10
CCIT2
RVC8
RVC6
RSEL2
RINV1
RCTLD RCTLC
M6
R2
R3
RINV2
R1
ZD1
DCOP
M1
M3
M4 M2
CEB
REB
RIFC
RIFD
RSENSE
M5
CVC4
S-8204A (2)
Figure 14
Caution 1. It is recommended that filter constants between VDD pin and VSS pin should be set
approximately to 47 F .
e.g., CVSS RVSS = 1.0 F 47 = 47 F
Sufficient evaluation of transient power supply fluctuation and overcurrent protection
function with the actual application is needed to determine the proper constants. Contact our
sales office in case the constants should be set to other than 47 F .
2. It has not been confirmed whether the operation is normal in circuits other than the above
example of connection. In addition, the example of connection shown above and the
constants do not guarantee proper operation. Perform thorough evaluation using an actual
application to set the constants.
Remark Refer to the application note for constants of each external component.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
25
Precautions
The application conditions for the input voltage, output voltage, and load current should not exceed the
package power dissipation.
Batteries can be connected in any order; however, there may be cases when discharging cannot be
performed when a battery is connected. In such a case, short the VMP pin and VDD pin or connect the
battery charger to return the IC to the normal mode.
If both an overcharge battery and an overdischarge battery are included among the whole batteries, the
condition is set in overcharge status and overdischarge status. Therefore either charging or discharging is
impossible.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement
by products including this IC of patents owned by a third party.
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
26
Characteristics (Typical Data)
1. Current consumption
1. 1 IOPE vs. VDS 1. 2 IOPE vs. Ta
0 5 10 20
I
OPE
[μA]
25
15
5
0
V
DS
[V]
35
15
30
20
10
22
40
I
OPE
[μA]
25
15
5
0
35
30
20
10
40
−40 0 25 50 75
Ta [°C]
−25 85
1. 3 IPDN vs. VDS 1. 4 IPDN vs. Ta
0 5 10 20
IPDN [μA]
0.07
0.05
0.03
0.00
VDS [V]
0.09
15
0.08
0.06
0.04
22
0.10
0.01
0.02
−40 0 25 50 75
Ta [°C]
−25 85
I
PDN
[μA]
0.07
0.05
0.03
0.00
0.09
0.08
0.06
0.04
0.10
0.01
0.02
2. Overcharge detection / release voltage, overdischarge detection / release voltage, overcurrent
detection voltage
2. 1 VCU vs. Ta 2. 2 VCL vs. Ta
−40 0 25 50 75
Ta [°C]
−25 85
V
CU
[V]
4.360
4.350
4.340
4.325
4.370
4.365
4.355
4.345
4.375
4.330
4.335
−40 0 25 50 75
Ta [°C]
−25 85
V
CL
[V]
4.14
4.10
4.18
4.16
4.12
4.20
2. 3 VDU vs. Ta 2. 4 VDL vs. Ta
−40 0 25 50 75
Ta [°C]
−25 85
V
DU
[V]
2.74
2.70
2.66
2.60
2.78
2.76
2.72
2.68
2.80
2.62
2.64
−40 0 25 50 75
Ta [°C]
−25 85
V
DL
[V]
2.02
1.98
1.94
2.06
2.04
2.00
1.96
2.08
1.92
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
27
2. 5 VDIOV1 vs. VDS 2. 6 VDIOV1 vs. Ta
10 11 12 14
V
DIOV1
[V]
0.27
0.25
0.23
0.20
V
DS
[V]
0.29
13
0.28
0.26
0.24
15
0.30
0.21
0.22
16
V
DIOV1
[V]
0.27
0.25
0.23
0.20
0.29
0.28
0.26
0.24
0.30
0.21
0.22
−40 0 25 50 75
Ta [°C]
−25 85
2. 7 VDIOV2 vs. VDS 2. 8 VDIOV2 vs. Ta
10 11 12 14
V
DIOV2
[V]
0.54
0.50
0.46
0.40
V
DS
[V]
0.58
13
0.56
0.52
0.48
15
0.60
0.42
0.44
16
VDIOV2 [V]
0.54
0.50
0.46
0.40
0.58
0.56
0.52
0.48
0.60
0.42
0.44
−40 0 25 50 75
Ta [°C]
−25 85
2. 9 VSHORT vs. VDS 2. 10 VSHORT vs. Ta
10 11 12 14
V
SHORT
[V]
1.0
0.8
V
DS
[V]
1.2
13
1.1
0.9
0.7
15
1.3
16
−40 0 25 50 75
Ta [°C]
−25 85
V
SHORT
[V]
1.0
0.8
1.2
1.1
0.9
0.7
1.3
2. 11 VCIOV vs. VDS 2. 12 VCIOV vs. Ta
10 11 12 14
VCIOV [V]
VDS [V]
13 15 16
−0.08
−0.10
−0.12
−0.15
−0.06
−0.07
−0.09
−0.11
−0.05
−0.14
−0.13
−40 0 25 50 75
Ta [°C]
−25 85
VCIOV [V]
−0.08
−0.10
−0.12
−0.15
−0.06
−0.07
−0.09
−0.11
−0.05
−0.14
−0.13
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
S-8204A Series Rev.3.5_01
28
3. CCT pin internal resistance / detection voltage, CDT pin internal resistance / detection voltage, CIT
pin internal resistance / detection voltage and load short-circuit detection delay time
3. 1 RINC vs. Ta 3. 2 VCCT vs. Ta (VDS = 15.2 V)
40 0 25 50 75
R
INC
[M
]
9.0
6.0
Ta [C]
12.0
25 85
7.0
8.0
10.0
11.0
40 0 25 50 75
V
CCT
[V]
10.7
10.4
Ta [C]
10.9
25 85
10.5
10.6
10.8
3. 3 RIND vs. Ta 3. 4 VCDT vs. Ta (VDS = 12.0 V)
40 0 25 50 75
RIND [k
]
900
600
Ta [C]
1200
25 85
700
800
1000
1100
40 0 25 50 75
VCDT [V]
8.2
Ta [C]
8.6
25 85
8.3
8.4
8.5
3. 5 RINI1 vs. Ta 3. 6 VCIT vs. Ta (VDS = 14.0 V)
40 0 25 50 75
R
INI1
[k
]
180
120
Ta [C]
240
25 85
140
160
200
220
40 0 25 50 75
V
CIT
[V]
9.6
Ta [C]
10.0
25 85
9.7
9.8
9.9
3. 7 RINI2 vs. Ta 3. 8 tSHORT vs. Ta
40 0 25 50 75
R
INI2
[k
]
18.0
12.0
Ta [C]
24.0
25 85
14.0
16.0
20.0
22.0
t
SHORT
[μs]
300
500
400
200
600
−40 0 25 50 75
Ta [°C]
−25 85
0
100
BATTERY PROTECTION IC FOR 3-SERIES OR 4-SERIES CELL PACK
Rev.3.5_01 S-8204A Series
29
4. COP pin / DOP pin
4. 1 ICOH vs. VCOP 4. 2 ICOL vs. VCOP
0 5 10 20
I
COH
[μA]
0.07
0.05
0.03
0.00
V
COP
[V]
0.09
15
0.08
0.06
0.04
22
0.10
0.01
0.02
0 3.5 7 14
I
COL
[mA]
10
0
V
COP
[V]
20
10.5
15
5
25
4. 3 IDOH vs. VDOP 4. 4 IDOL vs. VDOP
0 1.8 3.6 7.2
I
DOH
[mA]
V
DOP
[V]
5.4
3.5
2.5
1.5
0
4.5
4.0
3.0
2.0
5.0
0.5
1.0
0 3.5 7 14
IDOL [mA]
10
0
VDOP [V]
20
10.5
15
5
25
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
0.17±0.05
9
18
16
5.1±0.2
0.22±0.08
0.65
mm
No. FT016-A-P-SD-1.2
FT016-A-P-SD-1.2
TSSOP16-A-PKG Dimensions
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
4.0±0.1
2.0±0.1
ø1.5+0.1
-0
ø1.6±0.1
8.0±0.1
4.2±0.2
6.5 +0.4
-0.2
0.3±0.05
1.5±0.1
(7.2)
mm
8
1
9
16
No. FT016-A-C-SD-1.1
FT016-A-C-SD-1.1
TSSOP16-A-Carrier Tape
Feed direction
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
17.4±1.0
No. FT016-A-R-SD-2.0
FT016-A-R-SD-2.0
TSSOP16-A- Reel
QTY. 2,000
Enlarged drawing in the central part
2±0.5
ø13±0.2
ø21±0.8
21.4±1.0
17.4 +2.0
-1.5
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
17.4±1.0
No. FT016-A-R-S1-1.0
FT016-A-R-S1-1.0
TSSOP16-A- Reel
QTY. 4,000
Enlarged drawing in the central part
2±0.5
ø13±0.2
ø21±0.8
21.4±1.0
17.4 +2.0
-1.5
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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