Low Power, High Precision
Operational Amplifier
OP97
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1997–2009 Analog Devices, Inc. All rights reserved.
NULL NULL
V+
–IN
FEATURES
Low supply current: 600 μA maximum
OP07 type performance
Offset voltage: 20 μV maximum
Offset voltage drift: 0.6 μV/°C maximum
Very low bias current
25°C: 100 pA maximum
−55°C to +125°C: 250 pA maximum
High common-mode rejection: 114 dB minimum
Extended industrial temperature range: −40°C to +85°C
PIN CONNECTIONS
00299-001
V–
+IN OUT
OVER
COMP
1
2
3
4
8
7
6
5
OP97
Figure 1. 8-Lead PDIP (P Suffix)
8-Lead SOIC (S Suffix)
GENERAL DESCRIPTION
The OP97 is a low power alternative to the industry-standard
OP07 precision amplifier. The OP97 maintains the standards of
performance set by the OP07 while utilizing only 600 μA supply
current, less than 1/6 that of an OP07. Offset voltage is an ultralow
25 μV, and drift over temperature is below 0.6 μV/°C. External
offset trimming is not required in the majority of circuits.
Improvements have been made over OP07 specifications in
several areas. Notable is bias current, which remains below
250 pA over the full military temperature range. The OP97 is
ideal for use in precision long-term integrators or sample-and-
hold circuits that must operate at elevated temperatures.
Common-mode rejection and power supply rejection are also
improved with the OP97, at 114 dB minimum over wider
ranges of common-mode or supply voltage. Outstanding PSR, a
supply range specified from ±2.25 V to ±20 V, and the minimal
power requirements of the OP97 combine to make the OP97 a
preferred device for portable and battery-powered instruments.
The OP97 conforms to the OP07 pinout, with the null potenti-
ometer connected between Pin 1 and Pin 8 with the wiper to
V+. The OP97 upgrades circuit designs using AD725, OP05,
OP07, OP12, and PM1012 type amplifiers. It may replace 741-
type amplifiers in circuits without nulling or where the nulling
circuitry has been removed.
OP97
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Connections ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Application Information ................................................................ 11
AC Performance ............................................................................. 12
Guarding and Shielding ................................................................. 13
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
3/09—Rev. F to Rev. G
Changes to Figure 20 and Figure 23 ............................................... 9
Changes to Figure 26 and Figure 27 ............................................. 10
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
11/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 16
07/03—Rev. D to Rev. E
Deleted H-08A .................................................................... Universal
Deleted Q-8 ......................................................................... Universal
Deleted E-20A ..................................................................... Universal
Deleted Die Characteristics ............................................................. 4
Deleted Wafer Test Limits ............................................................... 4
Updated TPC 14 ............................................................................... 5
Updated Outline Dimensions ....................................................... 10
01/02—Rev. C to Rev. D
Edits to Absolute Maximum Ratings .............................................. 3
Edits to Ordering Guide ................................................................... 3
Deleted DICE Characteristics .......................................................... 3
Deleted Wafer Test Limits ................................................................ 3
Edits to Applications Information ................................................... 7
OP97
Rev. G | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
OP97E OP97F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT CHARACTERISTICS
Input Offset Voltage VOS 10 25 30 75 μV
Long-Term Offset
Voltage Stability ΔVOS/Time 0.3 0.3 μV/month
Input Offset Current IOS 30 100 30 150 pA
Input Bias Current IB ±30 ±100 ±30 ±150 pA
Input Noise Voltage en p-p 0.1 Hz to 10 Hz 0.5 0.5 μV p-p
Input Noise Voltage Density en fO = 10 Hz1 17 30 17 30 nV/√Hz
f
O = 1000 Hz2 14 22 14 22 nV/√Hz
Input Noise Current Density in fO = 10 Hz 20 20 fA/√Hz
Large Signal Voltage Gain AVO VO = ±10 V; RL = 2 kΩ 300 2000 200 2000 V/mV
Common-Mode Rejection CMR VCM = ±13.5 V 114 132 110 132 dB
Input Voltage Range3 IVR ±13.5 ±14.0 ±13.5 ±14.0 V
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 10 kΩ ±13 ±14 ±13 ±14 V
Differential Input Resistance4
RIN 30 30 MΩ
POWER SUPPLY
Power Supply Rejection PSR VS = ±2 V to ±20 V 114 132 110 132 dB
Supply Current ISY 380 600 380 600 μA
Supply Voltage VS Operating range ±2 ±15 ±20 ±2 ±15 ±20 V
DYNAMIC PERFORMANCE
Slew Rate SR 0.1 0.2 0.1 0.2 V/μs
Closed-Loop Bandwidth BW AVCL = 1 0.4 0.9 0.4 0.9 MHz
1 10 Hz noise voltage density is sample tested. Devices 100% tested for noise are available on request.
2 Sample tested.
3 Guaranteed by CMR test.
4 Guaranteed by design.
OP97
Rev. G | Page 4 of 16
VS = ±15 V, VCM = 0 V, −40°C ≤ TA ≤ +85°C for the OP97E/OP97F, unless otherwise noted.
Table 2.
OP97E OP97F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS 25 60 60 200 μV
Average Temperature TCVOS S suffix 0.2 0.6 0.3 2.0 μV/°C
Coefficient of VOS 0.3
Input Offset Current IOS 60 250 80 750 pA
Average Temperature TCIOS 0.4 2.5 0.6 7.5 pA/°C
Coefficient of IOS
Input Bias Current IB ±60 ±250 ±80 ±750 pA
Average Temperature
Coefficient of IB TCIB 0.4 2.5 0.6 7.5 pA/°C
Large Signal Voltage Gain AVO VO = 10 V; RL = 2 kΩ 200 1000 150 1000 V/mV
Common-Mode Rejection CMR VCM = ±13.5 V 108 128 108 128 dB
Power Supply Rejection PSR VS = ±2.5 V to ±20 V 108 126 108 128 dB
Input Voltage Range1IVR ±13.5 ±14.0 ±13.5 ±14.0 V
Output Voltage Swing VO RL = 10 kΩ ±13 ±14 ±13 ±14 V
Slew Rate SR 0.05 0.15 0.05 0.15 V/μs
Supply Current ISY 400 800 400 800 μA
Supply Voltage VS Operating range ±2.5 ±15 ±20 ±2.5 ±15 ±20 V
1 Guaranteed by CMR test.
OP97
Rev. G | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
Table 3.
Parameter Rating
Supply Voltage ±20 V
Input Voltage1 ±20 V
Differential Input Voltage2 ±1 V
Differential Input Current2 ±10 mA
Output Short-Circuit Duration Indefinite
Operating Temperature Range
OP97E, OP97F (P, S)
−40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 For supply voltages less than ±20 V, the absolute maximum input voltage is
equal to the supply voltage.
2 The inputs of the OP97 are protected by back-to-back diodes. Current-
limiting resistors are not used in order to achieve low noise. Differential
input voltages greater than 1 V cause excessive current to flow through the
input protection diodes unless limiting resistance is used.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Tab l e 4 .
Package Type θJA1 θ
JC Unit
8-Lead PDIP (P Suffix) 103 43 °C/W
8-Lead SOIC (S Suffix) 158 43 °C/W
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for
device in socket for PDIP package; θJA is specified for device soldered to
printed circuit board for SOIC package.
ESD CAUTION
OP97
Rev. G | Page 6 of 1
0
–40 –20 0 20 40
00299-00
6
TYPICAL PERFORMANCE CHARACTERISTICS
400
200
300
100
2
VS = ±15V
TA = 25°C
VCM = 0V
NUMBER OF UNITS
60
–20
0
–40
–60
–75 –50 –25 0 25 1007550 125
00299-005
20
40
T
A
= 25°C
V
CM
= 0V
I
B
–
I
B
+
I
OS
TEMPERATURE (°C)
INPUT CURRENT (pA)
60
–20
0
–40
–60
–15 –10 –5 105015
00299-006
20
40 I
B
–
I
B
+
I
OS
INPUT OFFSET VOLTAGE (µV)
1894 UNITS
Figure 2. Typical Distribution of Input Offset Voltage
400
200
300
100
3
Figure 5. Input Bias, Offset Current vs. Temperature
0
–100 –50 0 50 100
00299-00
V
S
= ±15V
T
A
= 25°C
V
CM
= 0V
NUMBER OF UNITS
1920 UNITS
INPUT BIAS CURRENT (pA)
Figure 3. Typical Distribution of Input Bias Current
500
400
200
300
100
4
T
A
= 25°C
V
S
= ±15V
COMMON-MODE VOLTAGE (V)
INPUT CURRENT (pA)
±5
±2
±1
0
012 435
00299-007
±3
±4
T
A
= 25°C
V
S
= ±15V
V
CM
=0V
Figure 6. Input Bias, Offset Current vs. Common-Mode Voltage
0
–60 –40 –20 0 20 40 60
00299-00
INPUT OFFSET CURRENT (pA)
NUMBER OF UNITS
1894 UNITS V
S
= ±15V
T
A
= 25°C
V
CM
= 0V
Figure 4. Typical Distribution of Input Offset Current
J PACKAGES
Z, P PACKAGES
TIME AFTER POWER APPLIED (Minutes)
DEVI
A
TION FROM FIN
A
LVALUE (µV)
Figure 7. Input Offset Voltage Warmup Drift
OP97
Rev. G | Page 7 of 16
1000
100
10
1
1k 3k 10k 30k 100k 300k 1M 3M 10M
EFFECTIVE OFFSET VOLTAGE (µV)
9-008
450
425
400
375
350
325
300 0 5 10 15 20
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT (µA)
00299-011
BALANCED OR UNBALANCED
V
S
= ±15V
V
CM
= 0V
SOURCE RESISTANCE (Ω)
0029
–55°C ≤ T
A
≤ +125°C
T
A
= 25°C
T
A
= +125°C
NO LOAD
T
A
= +25°C
T
A
= –55°C
Figure 8. Effective Offset Voltage vs. Source Resistance
100
10
1
0.1
1k 10k 100k 1M 10M 100M
EFFECTIVE OFFSET VOLTAGE DRIFT (µV/°C)
9-009
SOURCE RESISTANCE (Ω)
0029
BALANCED OR UNBALANCED
V
S
= ±15V
V
CM
= 0V
Figure 9. Effective TCVOS vs. Source Resistance
20
15
10
5
0
–5
–10
SHORT-CIRCUIT CURRENT (mA)
Figure 11. Supply Current vs. Supply Voltage
140
120
100
80
60
40
20
01 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
00299-012
T
A
= 25°C
V
S
=±15V
V
CM
= ±10V
Figure 12. Common-Mode Rejection vs. Frequency
140
120
100
80
60
40
POWER SUPPLY REJECTION (dB)
20
10.1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
00299-013
–15
–20 0123
TIME FROM OUTPUT SHORT (Minutes)
00299-010
T
A
= +25°C
T
A
= +25°C
T
A
= –55°C
T
A
= 25°C
V
S
=±15V
ΔV
S
=10V p-p
T
A
= –55°C
T
A
= +125°C
T
A
= +125°C
V
S
= ±15V
OUTPUT SHORTED TO GROUND
Figure 10. Short-Circuit Current vs. Time, Temperature
–PSR
+PSR
Figure 13. Power Supply Rejection vs. Frequency
OP97
Rev. G | Page 8 of 16
10k
1k
100
12 51020
OPEN-LOOP GAIN (V/mV)
9-014
LOAD RESISTANCE (kΩ)
0029
V
S
= ±15V
V
O
= ±10V
–15 50–5–10 10 15
OUTPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (10µV/DIV)
00299-017
RL = 10kΩ
VS = ±15V
VCM = 0V
TA = +125°C
T
A
= +25°C
T
A
= –55°C
T
A
= +125°C
TA = +25°C
TA = –55°C
Figure 14. Open-Loop Gain vs. Load Resistance
CURRENT NOISE DENSITY (fA/ Hz)
1k
100
10
1k
100
10
1 1
1 10 100 1k
9-015
VOLTAGE NOISE DENSITY (nV/ Hz)
FREQUENCY (Hz)
0029
TA = 25°C
VS = ±2V TO ±20V
CURRENT NOISE
VOLTAGE NOISE
1/1 CORNER
2.5Hz
1/1 CORNER
120Hz
Figure 15. Noise Density vs. Frequency
10
1
0.1
TOTAL NOISE DENSITY (µV/ Hz)
0.01
100 1k 10k 100k 1M 10M 100M
SOURCE RESISTANCE (Ω)
00299-016
TA = 25°C
VS = ±2V TO ±20V
1kHz
10Hz
RESISTOR NOISE
R
R
RS = 2R
Figure 16. Total Noise Density vs. Source Resistance
Figure 17. Open-Loop Gain Linearity
35
30
25
20
15
10
5
0
10 100 1k 10k
LOAD RESISTANCE (Ω)
00299-018
OUTPUT SWING (V p-p)
TA = 25°C
VS = ±15V
AVCL = +1
1% THD
f
O = 1kHz
Figure 18. Maximum Output Swing vs. Load Resistance
35
30
25
20
15
10
5
OUTPUT SWING (V p-p)
0
100 1k 10k 100k
FREQUENCY (Hz)
00299-019
TA = 25°C
VS = ±15V
AVCL = +1
1% THD
RL = 10kΩ
Figure 19. Maximum Output Swing vs. Frequency
OP97
Rev. G | Page 9 of 16
80
60
40
20
0
–20
90
135
180
225
–40
–60 10M100 1k 10k 100k 1M
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
9-020
FREQUENCY (Hz)
0029
80
60
40
20
0
–20
90
135
180
225
–40
–60 10M100 1k 10k 100k 1M
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
00299-023
GAIN
PHASE
T
A
= +125°C
T
A
= –55°C
V
S
= ±15V
C
L
= 20pF
R
L
= 1MΩ
T
A
= +125°C
T
A
= –55°C
PHASE
T
A
= –55°C
T
A
= +125°C
GAIN
T
A
= +125°C
T
A
= –55°C
V
S
= ±15V
C
L
= 20pF
R
L
= 1MΩ
Figure 20. Open-Loop Gain, Phase vs. Frequency (COC = 0 pF)
10
1
0.1
0.01
0.001
0.0001
10 100 1k 10k
9-021
THD + N (%)
FREQUENCY (Ω)
0029
A
VCL
= 100
A
VCL
= 10
A
VCL
= 1
T
A
= 25°C
V
S
= ±15V
R
L
= 10kΩ
1% THD
V
OUT
= 3V rms
Figure 21. Total Harmonic Distortion Plus Noise vs. Frequency
70
60
50
40
30
20
OVERSHOOT (%)
Figure 23. Open-Loop Gain, Phase vs. Frequency (COC = 100 pF)
1
0.1
0.01
0.001 1 10 100 1k 10k
OVERCOMPENSATION CAPACITOR (pF)
SLEW RATE (V/µs)
00299-024
RL = 10kΩ
VS = ±15V
CL = 100pF
TA = +125°C
TA = –55°C
Figure 24. Slew Rate vs. Overcompensation
1000
100
10
GAIN BANDWIDTH (kHz)
11 10 100 1k 10k
OVERCOMPENSATION CAPACITOR (pF)
00299-025
10
0
10 100 1k 10k
LOAD CAPACITANCE (pF)
00299-022
T
A
= 25°C
V
S
= ±15V
A
VCL
= +1
V
OUT
= 100mV p-p
C
OC
= 0pF
+EDGE
–EDGE
Figure 22. Small Signal Overshoot vs. Capacitive Load
T
A
= +125°C
T
A
= –55°C
V
S
= ±15V
C
L
= 20pF
R
L
= 1MΩ
A = 100
V
Figure 25. Gain Bandwidth Product vs. Overcompensation
OP97
Rev. G | Page 10 of 16
1k
0.1
1
0.01
0.001 110 10k1k100 100k
00299-028
10
100
80
60
40
20
0
–20
90
135
180
225
–40
–60 10M100 1k 10k 100k 1M
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
9-026
FREQUENCY (Hz)
0029
T
A
= +25°C
T
A
= –55°C
T
A
= –55°C T
A
= +125°C
T
A
= +125°C
GAIN
PHASE
V
S
= ±15V
C
L
= 20pF
R
L
= 1MΩ
Figure 26. Open-Loop Gain, Phase vs. Frequency (COC = 1000 pF)
80
60
40
20
0
–20
90
135
180
225
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
–40
–60 10M100 1k 10k 100k 1M
FREQUENCY (Hz)
00299-027
GAIN
PHASE
V
S
= ±15V
C
L
= 20pF
R
L
= 1MΩ
T
A
= +25°C
T
A
= –55°C
T
A
= –55°C
T
A
= +125°C
T
A
= +125°C
Figure 27. Open-Loop Gain, Phase vs. Frequency (COC = 10,000 pF)
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
T
A
= 25°C
V
S
=±15V
A
VCL
= 1000
A
VCL
= 1
Figure 28. Closed-Loop Output Resistance vs. Frequency
`
OP97
Rev. G | Page 11 of 16
00299-029
APPLICATION INFORMATION
The OP97 is a low power alternative to the industry-standard
precision op amp, the OP07. The OP97 can be substituted
directly into OP07, OP77, AD725, and PM1012 sockets with
improved performance and/or less power dissipation and can be
inserted into sockets conforming to the 741 pinout if nulling
circuitry is not used. Generally, nulling circuitry used with earlier
generation amplifiers is rendered superfluous by the extremely
low offset voltage of the OP97 and can be removed without
compromising circuit performance.
Extremely low bias current over the full military temperature
range makes the OP97 attractive for use in sample-and-hold
amplifiers, peak detectors, and log amplifiers that must operate
over a wide temperature range. Balancing input resistances is
not necessary with the OP97. Offset voltage and TCVOS are
degraded only minimally by high source resistance, even when
unbalanced.
The input pins of the OP97 are protected against large
differential voltage by back-to-back diodes. Current-limiting
resistors are not used to maintain low noise performance. If
differential voltages above ±1 V are expected at the inputs,
series resistors must be used to limit the current flow to a
maximum of 10 mA. Common-mode voltages at the inputs are
not restricted and may vary over the full range of the supply
voltages used.
The OP97 requires very little operating headroom about the
supply rails and is specified for operation with supplies as low as
±2 V. Typically, the common-mode range extends to within 1 V
of either rail. The output typically swings to within 1 V of the
rails when using a 10 kΩ load.
Offset nulling is achieved utilizing the same circuitry as an
OP07. A potentiometer between 5 kΩ and 100 kΩ is connected
between Pin 1 and Pin 8 with the wiper connected to the
positive supply. The trim range is between 300 μV and 850 μV,
depending upon the internal trimming of the device.
8
4
7
5
3
6
2
1
OP97
–V
C
OC
+
V
R
POT
= 5kΩ TO 100kΩ
Figure 29. Optional Input Offset Voltage Nulling
and Overcompensation Circuit
OP97
Rev. G | Page 12 of 16
AC PERFORMANCE
The ac characteristics of the OP97 are highly stable over its full
operating temperature range. Unity-gain small-signal response
is shown in Figure 30. Extremely tolerant of capacitive loading
on the output, the OP97 displays excellent response even with
1000 pF loads (see Figure 31). In large signal applications, the
input protection diodes effectively short the input to the output
during the transients if the amplifier is connected in the usual
unity-gain configuration. The output enters short-circuit current
limit, with the flow going through the protection diodes.
Improved large signal transient response is obtained by using a
feedback resistor between the output and the inverting input.
Figure 32 shows the large-signal response of the OP97 in unity-
gain with a 10 kΩ feedback resistor. The unity-gain follower
circuit is shown in Figure 33.
The overcompensation pin (Pin 5) can be used to increase the
phase margin of the OP97 or to decrease gain bandwidth
product at gains greater than 10.
00299-030
20mV 5µs
100
90
10
0%
Figure 30. Small Signal Transient Response
(CLOAD = 100 pF, AVCL = 1)
00299-031
100
90
10
0%
20mV 5µs
00299-032
100
90
10
0%
20µs2V
00299-033
Figure 31. Small-Signal Transient Response
(CLOAD = 1000 pF, AVCL = 1)
Figure 32. Large Signal Transient Response (AVCL = 1)
VOUT
VIN
OP97
10kΩ
2
3
6
00299-034
Figure 33. Unity-Gain Follower
100
90
10
0%
20mV 5µs
Figure 34. Small Signal Transient Response with Overcompensation
(CLOAD = 1000 pF, AVCL = 1, COC = 220 pF)
OP97
Rev. G | Page 13 of 16
00299-03
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the OP97,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of
moisture. Conformal coating is recommended to provide a
humidity barrier. Even a clean PCB can have 100 pA of leakage
currents between adjacent traces; therefore, use guard rings
around the inputs. Guard traces are operated at a voltage close
to that on the inputs, so that leakage currents are minimal. In
noninverting applications, connect the guard ring to the common-
mode voltage at the inverting input (Pin 2). In inverting appli-
cations, both inputs remain at ground, so that the guard trace
should be grounded. Make guard traces on both sides of the
circuit board.
High impedance circuitry is extremely susceptible to RF pickup,
line frequency hum, and radiated noise from switching power
supplies. Enclosing sensitive analog sections within grounded
shields is generally necessary to prevent excessive noise pickup.
Twisted-pair cable aid in rejection of line frequency hum.
5
V
OUT
OP97
2
3
6
I
O
I
O
30pF
AD7548
R
FB
DIGITAL
INPUTS
00299-036
Figure 35. DAC Output Amplifier
The OP97 is an excellent choice as an output amplifier for
higher resolution CMOS DACs. Its tightly trimmed offset
voltage and minimal bias current result in virtually no
degradation of linearity, even over wide temperature ranges.
Figure 36 shows a versatile monitor circuit that can typically
sense current at any point between the ±15 V supplies. This
makes it ideal for sensing current in applications such as full
bridge drivers where bidirectional current is associated with
large common-mode voltage changes. The 114 dB CMRR of the
OP97 makes the contribution of the amplifier to common-
mode error negligible, leaving only the error due to the resistor
ratio inequality. Ideally, R2/R4 = R3/R5.
V
OUT
R
L
I
L
2
3
6
7
4
R3
10kΩ
R2
10kΩ
R4
10kΩ
R5
10kΩ
R1
10kΩ
V
1
OP97
+15V
–15V
00299-037
UNITY-GAIN FOLLOWE
Figure 36. Current Monitor
R
NONINVERTING AMPLIFIE
R
INVERTING AMPLIFIER
OP97
2
3
6
OP97
2
3
6
OP97
2
3
6
PDIP
BOTTOM VIEW
81
Figure 37. Guard Ring Layout and Connections
OP97
Rev. G | Page 14 of 16
The digitally programmable gain amplifier shown in Figure 38
has 12-bit gain resolution with 10-bit gain linearity over the
range of −1 to −1024. The low bias current of the OP97 main-
tains this linearity, while C1 limits the noise voltage bandwidth,
allowing accurate measurement down to microvolt levels.
Tab l e 5 .
DIGITAL IN GAIN (Av)
4095 −1.00024
2048 −2
1024 −4
512 −8
256 −16
128 −32
64 −64
32 −128
16 −256
8 −512
4 −1024
2 −2048
1 −4096
0 Open Loop
Many high speed amplifiers suffer from less-than-perfect low
frequency performance. A combination amplifier consisting of
a high precision, slow device like the OP97 and a faster device such
as the AD8610 results in uniformly accurate performance from
dc to the high frequency limit of the AD8610, which has a gain-
bandwidth product of 25 MHz. The circuit shown in Figure 39
accomplishes this, with the AD8610 providing high frequency
amplification and the OP97 operating on low frequency signals
and providing offset correction. Offset voltage and drift of the
circuit are controlled by the OP97.
00299-038
V
OUT
2
3
6
AD7541A
I
OUT2
I
OUT1
R
FB
V
REF
18
1
2
3
17
16
+15V
–15V
0.1µF
0.1µF
C1
220pF
V
IN
±2.5mV TO ±10V
RANGE DEPENDING
ON GAIN SETTING
+15
V
OP97
0.1µF
Figure 38. Precision Programmable Gain Amplifier
00299-039
2
3
6
2
3
6
5pF
V
OUT
AD8610
OP97
0.1µF
0.1µF
10kΩ10kΩ
1µF
R1
2kΩ
R2
20kΩ
V
IN
5
A
V
= – R2
R1
Figure 39. Combination High Speed, Precision Amplifier
00299-040
100
90
10
0%
1V
5V
2µs
Figure 40. Combination Amplifier Transient Response
OP97
Rev. G | Page 15 of 16
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
OUTLINE DIMENSIONS
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 41. 8-Lead Plastic Dual In-Line Package [PDIP]
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 42. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
OP97
Rev. G | Page 16 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
OP97EP –40°C to +85°C 8-Lead PDIP N-8
OP97EPZ1
–40°C to +85°C 8-Lead PDIP N-8
OP97FP −40°C to +85°C 8-Lead PDIP N-8
OP97FPZ1
−40°C to +85°C 8-Lead PDIP N-8
OP97FS −40°C to +85°C 8-Lead SOIC_N R-8
OP97FS-REEL −40°C to +85°C 8-Lead SOIC_N R-8
OP97FS-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
OP97FSZ1 −40°C to +85°C 8-Lead SOIC_N R-8
OP97FSZ-REEL1
−40°C to +85°C 8-Lead SOIC_N R-8
OP97FSZ-REEL71
−40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part.
©1997–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00299-0-3/09(G)
