SCLS109G - MARCH 1984 - REVISED APRIL 2004 D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 16 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max Encode Eight Data Lines to 3-Line Binary (Octal) Applications Include: - n-Bit Encoding - Code Converters and Generators SN54HC148 . . . J OR W PACKAGE SN74HC148 . . . D, DW, N, OR NS PACKAGE (TOP VIEW) 4 5 6 7 EI A2 A1 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC EO GS 3 2 1 0 A0 SN54HC148 . . . FK PACKAGE (TOP VIEW) 5 4 NC VCC EO description/ordering information The 'HC148 devices feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. These devices encode eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. Data inputs and outputs are active at the low logic level. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 A1 GND NC 6 7 NC EI A2 GS 3 NC 2 1 A0 0 D D D D D D D NC - No internal connection ORDERING INFORMATION PACKAGE TA PDIP - N -40C to 85C -55C 125C -55 C to 125 C ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74HC148N Tube of 40 SN74HC148D Reel of 2500 SN74HC148DR Reel of 250 SN74HC148DT SOIC - DW Reel of 2000 SN74HC148DWR HC148 SOP - NS Reel of 2000 SN74HC148NSR HC148 CDIP - J Tube of 25 SNJ54HC148J SNJ54HC148J CFP - W Tube of 150 SNJ54HC148W SNJ54HC148W LCCC - FK Tube of 55 SNJ54HC148FK SOIC - D SN74HC148N HC148 SNJ54HC148FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) %(#"! "%' / 0 '' %$$! $ $!$( #'$!! *$,!$ $() '' *$ %(#"! %(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS109G - MARCH 1984 - REVISED APRIL 2004 FUNCTION TABLE OUTPUTS INPUTS EI 2 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 logic diagram (positive logic) 0 10 15 14 1 2 11 4 6 7 EI A0 13 1 7 5 GS 12 9 3 EO A1 2 3 4 6 A2 5 Pin numbers shown are for the D, DW, J, N, NS, and W packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS109G - MARCH 1984 - REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC148 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage 0 Input transition rise/fall time SN74HC148 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25C TYP MAX MIN MAX SN74HC148 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 8 160 80 A 3 10 10 10 pF 6V Ci SN54HC148 2 V to 6 V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER SN54HC148 SN74HC148 TO (OUTPUT) VCC 2V 69 180 270 225 1-7 A0, A1, or A2 4.5 V 23 36 54 45 6V 21 31 46 38 EO 0-7 GS tpd A0, A1, or A2 EI GS EO tt TA = 25C TYP MAX FROM (INPUT) Any MIN MIN MAX MIN MAX 2V 60 150 225 190 4.5 V 20 30 45 38 6V 17 26 38 33 2V 75 190 285 240 4.5 V 25 38 57 48 6V 21 32 48 41 2V 78 195 295 245 4.5 V 26 39 59 49 6V 22 33 50 42 2V 57 145 220 180 4.5 V 19 29 44 36 6V 16 25 38 31 2V 66 165 250 205 4.5 V 22 33 50 41 6V 19 28 43 35 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT ns ns 5 SCLS109G - MARCH 1984 - REVISED APRIL 2004 operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load TYP UNIT 35 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time, with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS109G - MARCH 1984 - REVISED APRIL 2004 APPLICATION INFORMATION 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 'HC148 'HC148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS 'HC08 0 1 2 Priority Flag (active low) 3 Encoded Data (active low) 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 'HC148 'HC148 EO A0 A1 A2 GS EO A0 A1 A2 Enable (active low) GS 'HC00 0 1 2 Priority Flag (active high) 3 Encoded Data (active high) Figure 2. Priority Encoder for 16 Bits Because the 'HC148 devices are combinational logic circuits, wrong addresses can appear during input transients. Moreover, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be considered when strobing the outputs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 MECHANICAL DATA MCFP004A- JANUARY 1995 - REVISED FEBRUARY 2002 W (R-GDFP-F16) CERAMIC DUAL FLATPACK Base and Seating Plane 0.285 (7,24) 0.245 (6,22) 0.045 (1,14) 0.026 (0,66) 0.006 (0,15) 0.080 (2,03) 0.055 (1,40) 0.004 (0,10) 0.305 (7,75) MAX 1 0.019 (0,48) 0.015 (0,38) 16 0.050 (1,27) 0.430 (10,92) 0.370 (9,40) 0.005 (0,13) MIN 4 Places 8 9 0.360 (9,14) 0.250 (6,35) 0.360 (9,14) 0.250 (6,35) 4040180-3 / C 02/02 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092AC POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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