Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 1 1Publication Order Number:
SN74LS393/D
SN74LS393
Dual 4-Stage Binary
Counter
The SN74LS393 contains a pair of high-speed 4-stage ripple
counters.
Each half of the LS393 operates as a Modulo-16 binary divider, with
the last three stages triggered in a ripple fashion. In the LS393, the
flip-flops are triggered by a HIGH-to-LOW transition of their CP
inputs. Each half of each circuit type has a Master Reset input which
responds to a HIGH signal by forcing all four outputs to the LOW
state.
•Dual Versions
•Individual Asynchronous Clear for Each Counter
•Typical Max Count Frequency of 50 MHz
•Input Clamp Diodes Minimize High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751A
PLASTIC
N SUFFIX
CASE 646
14
1
14
1
SOEIAJ
M SUFFIX
CASE 965
14 1
http://onsemi.com
Device Package Shipping
ORDERING INFORMATION
SN74LS393N 14 Pin DIP 2000 Units/Box
SN74LS393D SOIC–14 55 Units/Rail
SN74LS393DR2 SOIC–14 2500/Tape & Reel
SN74LS393M SOEIAJ–14 See Note 1
SN74LS393MEL SOEIAJ–14
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
See Note 1
SN74LS393
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock (Active LOW Going Edge)
Input to +16 (LS393)
Clock (Active LOW Going Edge)
Input to ÷2 (LS390)
Clock (Active LOW Going Edge)
Input to ÷ 5 (LS390)
Master Reset (Active HIGH) Input
Flip-Flop Outputs
CP
CP0
CP1
MR
Q0 - Q3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
1.0 U.L.
1.0 U.L.
1.5 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)
LOADING
PIN NAMES
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual InLine Package.
14 13 12 11 10 9
123456
8
7
VCC CP MR Q0Q1Q2Q3
CP MR Q0Q1Q2Q3GND
SN74LS393
http://onsemi.com
3
FUNCTIONAL DESCRIPTION
Each half of the SN74LS393 operates in the Modulo 16
binary sequence, as indicated in the ÷16 Truth Table. The
first flip-flop is triggered by HIGH-to-LOW transitions of
the CP input signal. Each of the other flip-flops is triggered
by a HIGH-to-LOW transition of the Q output of the
preceding flip-flop. Thus state changes of the Q outputs do
not occur simultaneously. This means that logic signals
derived from combinations of these outputs will be subject
to decoding spikes and, therefore, should not be used as
clocks for other counters, registers or flip-flops. A HIGH
signal on MR forces all outputs to the LOW state and
prevents counting.
SN74LS393 LOGIC DIAGRAM (one half shown)
MR
CP
KCP J
CDQ
KCP J
CDQ
KCP J
CDQ
KCP J
CDQ
Q0Q1Q2Q3
COUNT OUTPUTS
Q3Q2Q1Q0
0
1
2
3
4
5
6
7
8
9
10
11
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
12
13
14
15
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
TRUTH TABLE
SN74LS393
http://onsemi.com
4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN VIL or VIH
VOL Output LOW Voltage 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH
per Truth Table
IIH
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current 0.1 mA VCC = MAX, VIN = 7.0 V
MR –0.4 mA
IIL Input LOW Current CP, CP0–1.6 mA VCC = MAX, VIN = 0.4 V
IL
CP1–2.4 mA
CC ,IN
IOS Short Circuit Current (Note 2) –20 –100 mA VCC = MAX
ICC Power Supply Current 26 mA VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency
CP0 to Q025 35 MHz
fMAX Maximum Clock Frequency
CP1 to Q120 MHz
tPLH
tPHL Propagation Delay,
CP to Q012
13 20
20 ns CL = 15 pF
tPLH
tPHL CP to Q340
40 60
60 ns
tPHL MR to Any Output 24 39 ns
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tWClock Pulse Width 20 ns
tWMR Pulse Width 20 ns VCC = 5.0 V
trec Recovery Time 25 ns
CC
SN74LS393
http://onsemi.com
5
AC WAVEFORMS
*The number of Clock Pulses required between tPHL and tPLH measurements can be determined from the appropriate Truth Table.
*CP
Q
Q
MR & MS
CP
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tPHL
tPHL
tPLH
Figure 1.
Figure 2.
tW
tWtrec
SN74LS393
http://onsemi.com
6
PACKAGE DIMENSIONS
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 18.80
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M--- 10 --- 10
N0.015 0.039 0.38 1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG DK
C
SEATING
PLANE
N
–T–
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
SN74LS393
http://onsemi.com
7
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
 
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
SN74LS393
http://onsemi.com
8
PACKAGE DIMENSIONS
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 1.42 --- 0.056
A1
HE
Q1
LE
10 0
10
LEQ1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005) M0.10 (0.004)
D
Z
E
1
14 8
7
eA
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 965–01
ISSUE O
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “T ypicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS393/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada