SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Functionally Equivalent to QS3257
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Thin Very
Small-Outline (DGV), Small-Outline (D),
Shrink Small-Outline (DBQ), and Thin
Shrink Small-Outline (PW) Packages
description
The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer . The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3257 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
FUNCTION
OE S
FUNCTION
L L A port = B1 port
LH A port = B2 port
H X Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1B1
1B2
1A
2B1
2B2
2A
GND
VCC
OE
4B1
4B2
4A
3B1
3B2
3A
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1B11A
OE
1B2
SW
SW
2B12A
2B2
SW
SW
3B13A
3B2
SW
SW
4B14A
4B2
SW
SW
S
4
7
9
12
1
15
2
3
5
6
11
10
14
13
simplified schematic, each FET switch
A
(OE)
B
SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI/O < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VIH
High level control in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7
V
V
IH
High
-
le
v
el
control
inp
u
t
v
oltage
VCC = 2.7 V to 3.6 V 2
V
VIL
Low level control in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7
V
V
IL
Lo
w-
le
v
el
control
inp
u
t
v
oltage
VCC = 2.7 V to 3.6 V 0.8
V
TAOperating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VIK VCC = 3 V, II = –18 mA –1.2 V
IIVCC = 3.6 V, VI = VCC or GND ±1µA
Ioff VCC = 0, VI or VO= 0 to 4.5 V 10 µA
ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA
∆ICC§Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
CiControl inputs VI = 3 V or 0 3 pF
Ci(OFF)
A port
V 3Vor0
OE V
5.5 p
F
C
io(OFF) B port
V
O =
3
V
or
0
,
OE
=
V
CC 10.5
pF
V23V
II = 64 mA 5 8
VCC = 2.3 V,
TYP at VCC =25V
I =
II = 24 mA 5 8
r
TYP
at
VCC
=
2
.
5
V
VI = 1.7 V, II = 15 mA 27 40
Ω
r
on
II = 64 mA 5 7
Ω
VCC = 3 V
I =
II = 24 mA 5 7
VI = 2.4 V, II = 15 mA 10 15
‡All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
t
A or B†B or A 0.35 0.25
ns
tpd SA or B 1.8 6.1 1.8 5.3 ns
ten SA or B 1.7 6.1 1.7 5.3 ns
tdis SA or B 1 4.8 1 4.5 ns
ten OE A or B 1.9 5.6 2 5 ns
tdis OE A or B 1 5.5 1.6 5.5 ns
†The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VOH
VOL
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN74CBTLV3257
LOW-VOLTAGE 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS040D – DECEMBER 1997 – REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
VCC/2
VCC/2
VCC/2VCC/2
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.3 V
VOH – 0.3 V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
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Copyright 1999, Texas Instruments Incorporated