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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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March 2016
©2016 Fairchild Semiconductor Corporation
FDMA410NZT Rev. 1.0
www.fairchildsemi.com
1
FDMA410NZT Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
D
DS
G
D
D
Pin 1
Drain Source
MicroFET 2X2 (Bottom View)
5
16
2
34
D
D
S
D
D
G
Bottom Drain Contact
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 20 V
VGS Gate to Source Voltage ±8 V
ID
-Continuous TA = 25 °C (Note 1a) 9.5 A
-Pulsed (Note 4) 63
PD
Power Dissipation TA = 25 °C (Note 1a) 2.4 W
Power Dissipation TA = 25 °C (Note 1b) 0.9
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 52 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1b) 145
Device Marking Device Package Reel Size Tape Width Quantity
410T FDMA410NZT MicroFET 2X2 7 ’’ 8 mm 3000 units
FDMA410NZT
Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
20 V, 9.5 A, 23 mΩ
Features
0.55mm max package height MicroFET 2x2mm Package
Max rDS(on) = 23 mΩ at VGS = 4.5 V, ID = 9.5 A
Max rDS(on) = 29 mΩ at VGS = 2.5 V, ID = 8.0 A
Max rDS(on) = 36 mΩ at VGS = 1.8 V, ID = 4.0 A
Max rDS(on) = 60 mΩ at VGS = 1.5 V, ID = 2.0 A
HBM ESD protection level > 1.5 kV (Note 3)
RoHS Compliant
General Description
This Single N-Channel MOSFET has been designed using
Fairchild Semiconductor’s advanced Power Trench process to
optimize the rDS(ON) @ VGS = 1.5 V on special MicroFET
leadframe.
This design is similar to the FDMA410NZ, however it features
our new advanced 0.55mm max 2x2 MLP package technology.
Applications
Li-lon Battery Pack
Baseband Switch
Load Switch
DC-DC Conversion
Mobile Device Switching
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2
©2016 Fairchild Semiconductor Corporation
FDMA410NZT Rev. 1.0
FDMA410NZT Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 20 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 15 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 μA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 0.4 0.8 1.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C –3 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 4.5 V, ID = 9.5 A 14 23
mΩ
VGS = 2.5 V, ID = 8.0 A 18 29
VGS = 1.8 V, ID = 4.0 A 25 36
VGS = 1.5 V, ID = 2.0 A 35 60
VGS = 4.5 V, ID = 9.5 A,
TJ = 125 °C 21 32
gFS Forward Transconductance VDD = 5 V, ID = 9.5 A 36 S
Ciss Input Capacitance VDS = 10 V, VGS = 0 V,
f = 1 MHz
935 1310 pF
Coss Output Capacitance 122 170 pF
Crss Reverse Transfer Capacitance 84 118 pF
RgGate Resistance f = 1 MHz 0.1 1.4 3.0 Ω
td(on) Turn-On Delay Time
VDD = 10 V, ID = 9.5 A,
VGS = 4.5 V, RGEN = 6 Ω
8.5 17 ns
trRise Time 3.0 10 ns
td(off) Turn-Off Delay Time 27 44 ns
tfFall Time 3.3 10 ns
QgTotal Gate Charge VGS = 4.5 V , VDD = 10 V,
ID = 9.5 A
10 14 nC
Qgs Gate to Source Charge 1.2 nC
Qgd Gate to Drain “Miller” Charge 2.0 nC
ISMaximum Continuous Drain-Source Diode Forward Current 2.0 A
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2.0 A (Note 2) 0.7 1.2 V
trr Reverse Recovery Time IF = 9.5 A, di/dt = 100 A/μs 16 30 ns
Qrr Reverse Recovery Charge 4.5 10 nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
4. Pulsed Id please refer to Fig.11 SOA curve for more details.
a.52 °C/W when mounted
on a 1 in2 pad of 2 oz copper.
b. 145 °C/W when mounted on a
minimum pad of 2 oz copper.
www.fairchildsemi.com
3
©2016 Fairchild Semiconductor Corporation
FDMA410NZT Rev. 1.0
FDMA410NZT Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
0.0 0.5 1.0 1.5 2.0
0
20
40
60
80
VGS = 2.5 V
VGS = 1.5 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 1.8 V
VGS = 4.5 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 20406080
0
1
2
3
VGS = 1.8 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 2.5 V
VGS = 3.5 V
VGS = 1.5 V
VGS = 4.5 V
N o r m a l i z e d O n - R e s i s t a n c e
vs Drain Current and Gate Voltage
F i g u r e 3 . N o r m a l i z e d O n R e s i s t a n c e
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID = 9.5 A
VGS = 4.5 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Temperature
Figure 4.
12345
0
20
40
60
80
100
TJ = 125 oC
ID = 9.5 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
O n -R es i s t an ce v s G a t e to
Source Voltage
Figure 5. Transfer Characteristics
1234
0
20
40
60
80
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.3 0.6 0.9 1.2 1.5
0.001
0.01
0.1
1
10
80
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
S ou r ce to D ra i n D io d e
Forward Voltage vs Source Current
www.fairchildsemi.com
4
©2016 Fairchild Semiconductor Corporation
FDMA410NZT Rev. 1.0
FDMA410NZT Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
Figure 7.
01234567
0.0
1.5
3.0
4.5
ID = 9.5 A
VDD = 8 V
VDD = 12 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 10 V
Gate Charge Characteristics Figure 8.
0.1 1 10 20
10
100
1000
2000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
C a p a c i t a n c e v s D r a i n
to Source Voltage
Figure 9.
0.01 0.1 1 10 100
1
10
20
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
U n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10.
02468
10-5
10-4
10-3
10-2
10-1
1
10
VDS = 0 V
TJ = 25 oC
TJ = 125 oC
VGS, GATE TO SOURCE VOLTAGE (V)
Ig, GATE LEAKAGE CURRENT (A)
Gate Leakage Current vs Gate to Source
Voltage
Fig u r e 11. For w a r d Bias Safe
Operating Area
0.1 1 10 50
0.01
0.1
1
10
100
LIMITED BY rDS(on)
DC
10 s
1 s
CURVE BENT TO
MEASURED DATA
10 μs
100 ms
10 ms
1 ms
100 μs
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
SINGLE PULSE
TJ = MAX RATED
RθJA = 145 oC/W
TA = 25 oC
Figure 12.
10-5 10-4 10-3 10-2 10-1 100101100 1000
0.1
1
10
100
1000
SINGLE PULSE
RθJA = 145 oC/W
TA = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
S i n g l e P u l s e M a x i m u m
Power Dissipation
Typical Characteristics TJ = 25 °C unless otherwise noted
www.fairchildsemi.com
5
©2016 Fairchild Semiconductor Corporation
FDMA410NZT Rev. 1.0
FDMA410NZT Ultra Thin N-Channel 1.5 V PowerTrench® MOSFET
Figure 13.
10-6 10-5 10-4 10-3 10-2 10-1 1
10-4
10-3
10-2
10-1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
NOTES:
ZθJA(t) = r(t) x RθJA
RθJA = 145 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJA(t) + TA
PDM
t1
t2
Junction-to-Case Transient Thermal Response Curve
Typical Characteristics TJ = 25 °C unless otherwise noted
BOTTOM VIEW
SIDE VIEW
NOTES:
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
D. DRAWING FILENAME: MKT-FR015L3TrevB.
0.10 C A B
0.05 C
13
4
6
(0.50)
(0.30)
(0.50)
(0.15)
0.265±0.065
(6X)
1.00±0.05
0.61±0.05
0.30±0.05 (6X)
0.90±0.10
0.65
1.30
78
5
2
(0.225) 4X
RECOMMENDED LAND PATTERN OPT 1
4
6
3
1
RECOMMENDED LAND PATTERN OPT 2
4
6
3
1
0.66
1.05 2.30
(0.20)
(0.45)
1.00
2.05±0.10
2.05±0.10
AB
TOP VIEW
PIN #1
IDENT
0.50±0.05
0.15±0.05
0.025±0.025
CSEATING PLANE
PIN #1 IDENT
NO TRACES OR
VIAS ALLOWED
IN THIS AREA
(0.20)
1.00
2.301.05
0.47 (6X)
0.40 TYP (6X)
0.65 TYP
0.47 (6X)
0.40 TYP (7X)
0.65 TYP
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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