NTE857M
NTE857SM
Integrated Circuit
Low–Noise JFET–Input Operational Amplifier
Description:
The NTE857M and NTE857SM are low–noise JFET input operational amplifiers combining two
state–of–the–art linear technologies on a single monolithic integrated circuit. Each internally com-
pensated operational amplifier has well matched high voltage JFET input devices for low input offset
voltage. The BIFET technology provides wide bandwidths and fast slew rates with low input bias cur-
rents, input offset currents, and supply currents. Moreover, these devices exhibit low–noise and low
harmonic distortion making them ideal for use in high–fidelity audio amplifier applications.
Features:
DAvailable in Two Different Package Types:
8–Lead Mini DIP (NTE857M)
SOIC–8 Surface Mount (NTE857SM)
DLow Input Noise Voltage: 18nV√Hz Typ
DLow Harmonic Distortion: 0.01% Typ
DLow Input Bias and Offset Currents
DHigh Input Impedance: 1012Ω Typ
DHigh Slew Rate: 13V/µs Typ
DWide Gain Bandwidth: 4MHz Typ
DLow Supply Current: 1.4mA per Amp
Absolute Maximum Ratings:
Supply Voltage
VCC +18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VEE –18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Input Voltage, VID ±30V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Range (Note 1), VIDR ±15V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Short–Circuit Duration (Note 2), tSContinuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation, PD680mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derate Above TA = +47°C 10mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Ambient Temperature Range, TA0 to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, Tstg –65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or
15V, whichever is less.
Note 2. The output may be shorted to GND or either supply. Temperature and/or supply voltages
must be limited to ensure that power dissipation ratungs are not exceeded.
Electrical Characteristics: (VCC = +15V, VEE = –15V, TA = +25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Offset Voltage VIO RS ≤ 10k, –310 mV
VCM = 0 TA = 0 to +70°C– – 13 mV
Average Temperature
Coefficient of Input Offset
Voltage
∆VIO/∆T TA = 0 to +70°C–10 –µV/°C
Input Offset Current IIO VCM = 0, –550 pA
Note 3 TA = 0 to +70°C––2nA
Input Bias Current IIB VCM = 0, –30 200 pA
Note 3 TA = 0 to +70°C––7nA
Input Resistance ri–1012 –Ω
Common Mode Input Voltage
Range VICR ±10 +15, –12 –V
Large–Signal Voltage Gain AVOL VO = ±10V,
≤
25 150 –V/mV
RL ≤ 2k TA = 0 to +70°C15 – – V/mV
Output Voltage Swing VORL = 10k 24 28 –V
(Peak–to–Peak) RL ≥ 10k TA = 0 to +70°C24 – – V
RL ≥ 2k 20 – – V
Common Mode Rejection Ratio CMRR RS ≤ 10k 70 100 –dB
Supply Voltage Rejection Ratio PSRR RS ≤ 10k 70 100 –dB
Supply Current (Each Amplifier) ID–1.4 2.5 mA
Unity Gain Bandwidth BW –4–MHz
Slew Rate SR VIN = 10V, RL = 2k, CL = 100pF –13 –V/µs
Rise Time tr–0.1 –µs
Overshoot Factor VIN = 20mV, RL = 2k,
CL = 100pF –10 –%
Equivalent Input Noise Voltage enRS = 100Ω, f = 1000Hz –18 –nV/√Hz
Equivalent Input Noise Current inRS = 100Ω, f = 1000Hz –0.01 –pA/√Hz
Total Harmonic Distortion THD VO(RMS) = 10V, RS ≤ 1k,
RL ≥ 2k, f = 1000Hz –0.01 –%
Channel Separation AV = 100 –120 –dB
Note 3. Input Bias currents of JFET input operational amplifiers approximately double for every 10°C
rise in Junction Temperature. To maintain Junction Temperature as close to Ambient Tem-
perature as possible, pulse techniques must be used during test.
VCC
N.C.
VEE
Pin Connection Diagram
NTE857M
NTE857SM
Output
Inverting Input (1)
1
2
3
4
Offset Null
Non–Inverting Input (1)
8
7
6
5Offset Null
14
.260 (6.6)
.390 (9.9)
Max
85
.155
(3.93)
.145 (3.68)
.300
(7.62)
.300 (7.62)
.100 (2.54)
.198 (5.03)
.236
(5.99)
NOTE: Pin1 on Beveled Edge
.154
(3.91)
061
(1.53)
.006 (.152)
14
85
.192 (4.9)
.050 (1.27) 016
(.406)
