DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx Module Configuration VMS Part Number VR5Vx287214EBP VR5Vx287214EBS VR5Vx287214EBW VR5Vx287214EBZ VR5Vx287214EBY VR5Vx567214FBP VR5Vx567214FBS VR5Vx567214FBW VR5Vx567214FBZ VR5Vx567214FBY VR5Vx567214ECP VR5Vx567214ECS VR5Vx567214ECW VR5Vx127214FEP VR5Vx127214FES VR5Vx127214FEW VR5Vx127214GBP VR5Vx127214GBS VR5Vx127214GBW VR5Vx127214GBZ VR5Vx127214GBY VR5Vx127214FCP VR5Vx127214FCS VR5Vx127214FCW VR5Vx127214EPP VR5Vx127214EPS VR5Vx1G7214FPP VR5Vx1G7214FPS Notes: VA = Address Parity VR = No Address Parity Capacity 1GB 1GB 1GB 1GB 1GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 8GB 8GB Module Device Configuration Configuration 128Mx72 128M x 4 bit (18) 128Mx72 128M x 4 bit (18) 128Mx72 128M x 4 bit (18) 128Mx72 128M x 4 bit (18) 128Mx72 128M x 4 bit (18) 256Mx72 256M x 4 bit (18) 256Mx72 256M x 4 bit (18) 256Mx72 256M x 4 bit (18) 256Mx72 256M x 4 bit (18) 256Mx72 256M x 4 bit (18) 256Mx72 128M x 4 bit (36) 256Mx72 128M x 4 bit (36) 256Mx72 128M x 4 bit (36) 512Mx72 256M x 4 bit (36 die) 512Mx72 256M x 4 bit (36 die) 512Mx72 256M x 4 bit (36 die) 512Mx72 512M x 4 bit (18) 512Mx72 512M x 4 bit (18) 512Mx72 512M x 4 bit (18) 512Mx72 512M x 4 bit (18) 512Mx72 512M x 4 bit (18) 512Mx72 256M x 4 bit (36) 512Mx72 256M x 4 bit (36) 512Mx72 256M x 4 bit (36) 512Mx72 128M x 4 bit (72) 512Mx72 128M x 4 bit (72) 1Gx72 256M x 4 bit (72) 1Gx72 256M x 4 bit (72) Device Package FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA RAM-StackTM RAM-StackTM RAM-StackTM DDP BGA DDP BGA DDP BGA FBGA FBGA FBGA FBGA FBGA RAM-StackTM RAM-StackTM RAM-StackTM RAM-StackTM RAM-StackTM RAM-StackTM RAM-StackTM Module Performance Ranks 1 PC2-3200 1 PC2-4200 1 PC2-5300 1 PC2-6400 1 PC2-6400 1 PC2-3200 1 PC2-4200 1 PC2-5300 1 PC2-6400 1 PC2-6400 2 PC2-3200 2 PC2-4200 2 PC2-5300 2 PC2-3200 2 PC2-4200 2 PC2-5300 1 PC2-3200 1 PC2-4200 1 PC2-5300 1 PC2-6400 1 PC2-6400 2 PC2-3200 2 PC2-4200 2 PC2-5300 4 PC2-3200 4 PC2-4200 4 PC2-3200 4 PC2-4200 CAS Latency CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL6 (6-6-6) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL6 (6-6-6) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL6 (6-6-6) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL5 (5-5-5) CL3 (3-3-3) CL4 (4-4-4) CL3 (3-3-3) CL4 (4-4-4) Features * * * * * * * * * * * * Single 1.8V 0.1V Power Supply Registered inputs with one-clock delay CAS Latency: CL 3, 4, 5 Burst Length (4, 8) Burst type (Sequential & Interleave) Auto & Self-Refresh. 8k/64ms Refresh Period. Differential CLK (/CLK) input. On-die termination (ODT) Off-chip driver (OCD) impedance calibration Serial Presence Detect with EEPROM. RoHS Compliant* (see last page) Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 1 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx PIN CONFIGURATIONS Front Side Pin Back Side Pin Front Side Pin Back Side Pin Front Side Pin Back Side 1 VREF 121 VSS 31 DQ19 2 VSS 122 DQ4 32 VSS 3 DQ0 123 DQ5 33 DQ24 4 DQ1 124 VSS 34 DQ25 5 VSS 125 DQS9 35 VSS 6 /DQS0 126 /DQS9 36 /DQS3 7 DQS0 127 VSS 37 DQS3 8 VSS 128 DQ6 38 VSS 9 DQ2 129 DQ7 39 DQ26 10 DQ3 130 VSS 40 DQ27 11 VSS 131 DQ12 41 VSS 12 DQ8 132 DQ13 42 CB0 13 DQ9 133 VSS 43 CB1 14 VSS 134 DQS10 44 VSS 15 /DQS1 135 /DQS10 45 /DQS8 16 DQS1 136 VSS 46 DQS8 17 VSS 137 RFU 47 VSS 18 /RESET 138 RFU 48 CB2 19 NC 139 VSS 49 CB3 20 VSS 140 DQ14 50 VSS 21 DQ10 141 DQ15 51 VDDQ 22 DQ11 142 VSS 52 CKE0 23 VSS 143 DQ20 53 VDD 24 DQ16 144 DQ21 54 *BA2 25 DQ17 145 VSS 55 ***ERR_OUT 26 VSS 146 DQS11 56 VDDQ 27 /DQS2 147 /DQS11 57 A11 28 DQS2 148 VSS 58 A7 29 VSS 149 DQ22 59 VDD 30 DQ18 150 DQ23 60 A5 *Pins are used with 1Gbit devices (7214F in PN) **Pins are not used for single rank module *** Pins are used on modules with Address Parity Pins are used on quad rank modules only. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 VSS DQ28 DQ29 VSS DQS12 /DQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 /DQS17 VSS CB6 CB7 VSS VDDQ **CKE1 VDD ***A15 ***A14 VDDQ A12 A9 VDD A8 A6 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 A4 VDDQ A2 VDD VSS VSS VDD ***PAR_IN VDD A10/AP BA0 VDDQ /WE /CAS VDDQ **/S1 **ODT1 VDDQ VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 VDDQ A3 A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDDQ /RAS /S0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DQS13 /DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 DQS14 /DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS /S2 /S3 VSS DQS15 /DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 /DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 Pin Front Side Pin Back Side Pin Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 2 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY CK0 IN Positive Edge /CK0 IN Negative Edge CKE [1:0] IN Active High /S [3:0] IN Active Low ODT[1:0] IN Active High /RAS, /CAS, /WE IN Active Low VREF Supply VDD Supply BA [2:0] IN - A [n:0] IN - DQ [63:0], CB [7:0] VDD, VSS DQS [17:0] /DQS [17:0] I/O - Supply I/O I/O Positive Edge Negative Edge SA [2:0] IN - SDA I/O - SCL IN - DESCRIPTION Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both /S[0:1] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, /S[2:3] operate similarly to /S[0:1] for a second set of register outputs. On-Die Termination control signals CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS, and /WE define the operation to be executed by the SDRAM. Reference voltage for SSTL18 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank of four or eight is activated. During a Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, and BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge. Data and Check Bit Input/Output pins Power and ground for the DDR SDRAM input buffers and core logic. Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pull-up. Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 3 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY VDDSPD Supply - /RESET IN Par_In Err_Out IN OUT DESCRIPTION Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3 Volt) operations. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Parity bit for the Address and Control bus. ("1 ": Odd, "0 ": Even) Parity error found in the Address and Control bus Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 4 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx MECHANICAL OUTLINE Dimensions are in inches. (Tolerance is +/- 0.005, unless otherwise stated.) Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 5 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx FUNCTIONAL BLOCK DIAGRAM (Single Rank) Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 6 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx FUNCTIONAL BLOCK DIAGRAM (Dual Rank) RCKE1 RO DT1 RCS1 RCKE0 RO DT0 RCS0 VSS ODT ODT ODT ODT ODT ODT ODT CS CKE U 30 ODT CS CKE ODT CS CKE U 31 ODT CS CKE ODT CS CKE Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 7 of 19 ODT ODT CS CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM ODT ODT CS CKE U 18 DM ODT ODT CS U 27 U 13 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DQ S17 /D Q S 1 7 CB4 CB5 CB6 CB7 U 12 U 29 CKE DM DM CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 28 CKE DQ S16 /D Q S 1 6 D Q 60 D Q 61 D Q 62 D Q 63 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM U 22 CS DM DM CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 11 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CS DQ S15 /D Q S 1 5 D Q 52 D Q 53 D Q 54 D Q 55 U 10 DM U 21 CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 20 CS DQ S14 /D Q S 1 4 D Q 44 D Q 45 D Q 46 D Q 47 U4 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM U 19 CKE DM DM CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE DQ S13 /D Q S 1 3 D Q 36 D Q 37 D Q 38 D Q 39 DM CS DM U3 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 ODT DQ S12 /D Q S 1 2 D Q 28 D Q 29 D Q 30 D Q 31 U2 CKE U 35 ODT ODT CS CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM CS U 34 ODT ODT CS CKE DQ S11 /D Q S 1 1 D Q 20 D Q 21 D Q 22 D Q 23 U1 CKE ODT ODT CS CKE DM CS ODT ODT CS CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE ODT ODT CS CKE DQ S10 /D Q S 1 0 D Q 12 D Q 13 D Q 14 D Q 15 CS ODT ODT CS CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM ODT ODT CS CKE U9 DM DM CKE ODT CS CKE U 17 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 ODT DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DQS8 /D Q S 8 CB0 CB1 CB2 CB3 U 16 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 ODT DM CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM CKE DQS7 /D Q S 7 D Q 56 D Q 57 D Q 58 D Q 59 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 33 CS DM U 32 CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 15 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS6 /D Q S 6 D Q 48 D Q 49 D Q 50 D Q 51 U 14 CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DM CS DQS5 /D Q S 5 D Q 40 D Q 41 D Q 42 D Q 43 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE DM U 26 CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM CKE DQS4 /D Q S 4 D Q 32 D Q 33 D Q 34 D Q 35 U8 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U 25 CS DM U 24 CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 U7 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DQS9 /D Q S 9 DQ4 DQ5 DQ6 DQ7 U 23 CS DQS3 /D Q S 3 D Q 24 D Q 25 D Q 26 D Q 27 U6 DM CKE DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DM DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CS DQS2 /D Q S 2 D Q 16 D Q 17 D Q 18 D Q 19 U5 CKE DM DM CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE DQS1 /D Q S 1 DQ8 DQ9 D Q 10 D Q 11 ODT DM CS DQS /D Q S I/O 0 I/O 1 I/O 2 I/O 3 CKE DQS0 /D Q S 0 DQ0 DQ1 DQ2 DQ3 U 36 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx FUNCTIONAL BLOCK DIAGRAM (Single/Dual Rank Register, PLL, EEPROM) DUAL RANK /S 0 /S 1 BA0 - BA2 A0 - An /R A S /C A S /W E CKE0 CKE1 ODT0 ODT1 /R E S E T P A R _ IN PCK7 /P C K 7 R E G I S T E R R C S 0: U 1 ~ U 18 R C S 1: U 19 ~ U 3 6 B A 0 - B A 2: U 1 ~ U 36 A 0 - A n : U 1 ~ U 36 /R A S : U 1 ~ U 36 /C A S : U 1 ~ U 36 /W E : U 1 ~ U 3 6 R C K E 0 : U 1 ~ U 18 R C K E 1: U 19 ~ U 3 6 R O D T 0: U 1 ~ U 1 8 R O D T 1: U 19 ~ U 36 CK0 /C K 0 /R E S E T P L L P C K 7 to R e gister /P C K 7 to R e gister S erial P D U 1~ U 36 U 1~ U 36 U 1~ U 36 VDDSPD V D D /V D D Q VREF VSS /E R R _ O U T P C K 0 ~ 6 , 8,9 to U 1 ~ U 36 /P C K 0 ~ 6, 8,9 to U 1 ~ U 36 S IN G L E R A N K RCS0: U1 ~ U18 /S 0 BA0 - BA2 A0 - An /R A S /C A S /W E CKE0 ODT0 /R E S E T P A R _IN PCK7 /P C K 7 R E G I S T E R B A 0 - B A 2: U 1 ~ U 18 A 0 - A n: U 1 ~ U 18 /R A S : U 1 ~ U 18 /C A S : U 1 ~ U 18 /W E : U 1 ~ U 18 R C K E 0 : U 1 ~ U 18 CK0 /C K 0 /R E S E T P L L P C K 0 ~ 6 , 8,9 to U 1 ~ U 18 /P C K 0 ~ 6, 8,9 to U 1 ~ U 18 P C K 7 to R e gister /P C K 7 to R e gister R O D T 0 : U 1 ~ U 18 VDDSPD V D D /V D D Q VREF VSS /E R R _ O U T SCL WP A0 A1 A2 S erial P D U 1~ U 18 U 1~ U 18 U 1~ U 18 SDA SA0 SA1 SA2 N o tes : T he resistor value s m ay vary depend ing on system s a pplication Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 8 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx FUNCTIONAL BLOCK DIAGRAM QUAD RANK VSS RODT1 RODT0 RCKE1 RCKE0 RCS3 RCS2 RCS1 RCS0 ODT3 ODT2 ODT1 ODT0 ODT3 ODT2 ODT1 ODT0 U11 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U12 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U13 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U14 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U15 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U16 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U17 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 R E G I S T E R CKE3 CKE2 CKE1 CKE0 1:2 U10 U18 PCK 0 ~ 6, 8,9 to U1 ~ U18 /PCK 0 ~ 6, 8,9 to U1 ~ U18 PCK7 to Register /PCK7 to Register SCL WP /S0 ~ /S1 /S2 ~ /S3 BA0 - BA2 A0 - An /RAS /CAS /WE CKE0 CKE1 ODT0 ODT1 /RESET PAR_IN PCK7 /PCK7 CKE3 CKE2 CKE1 CKE0 DQS /DQS I/O [0~3] RDQS DQS17 /DQS17 CB4 ~ CB7 S3 S2 S1 S0 DQS /DQS I/O [0~3] RDQS DQS16 /DQS16 DQ60 ~ DQ63 S3 S2 S1 S0 DQS /DQS I/O [0~3] RDQS DQS15 /DQS15 DQ52 ~ DQ55 S3 S2 S1 S0 DQS /DQS I/O [0~3] RDQS DQS14 /DQS14 DQ44 ~ DQ47 S3 S2 S1 S0 DQS /DQS I/O [0~3] RDQS DQS13 /DQS13 DQ36 ~ DQ39 S3 S2 S1 S0 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 DQS /DQS I/O [0~3] RDQS ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 DQS12 /DQS12 DQ28 ~ DQ31 S3 S2 S1 S0 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 DQS /DQS I/O [0~3] RDQS ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 DQS11 /DQS11 DQ20 ~ DQ23 S3 S2 S1 S0 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 DQS /DQS I/O [0~3] RDQS ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 P L L DQS10 /DQS10 DQ12 ~ DQ15 S3 S2 S1 S0 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U9 DQS /DQS I/O [0~3] RDQS ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 U8 DQS9 /DQS9 DQ4 ~ DQ7 S3 S2 S1 S0 ODT3 ODT2 ODT1 ODT0 CKE3 CKE2 CKE1 CKE0 CK0 /CK0 /RESET RDQS DQS /DQS I/O [0~3] U7 S3 S2 S1 S0 DQS8 /DQS8 CB0 ~ CB3 RDQS DQS /DQS I/O [0~3] U6 S3 S2 S1 S0 DQS7 /DQS7 DQ56 ~ DQ59 RDQS DQS /DQS I/O [0~3] U5 S3 S2 S1 S0 DQS6 /DQS6 DQ48 ~ DQ51 RDQS DQS /DQS I/O [0~3] U4 S3 S2 S1 S0 DQS5 /DQS5 DQ40 ~ DQ43 RDQS DQS /DQS I/O [0~3] U3 S3 S2 S1 S0 DQS4 /DQS4 DQ32 ~ DQ35 RDQS DQS /DQS I/O [0~3] U2 S3 S2 S1 S0 DQS3 /DQS3 DQ24 ~ DQ27 RDQS DQS /DQS I/O [0~3] U1 S3 S2 S1 S0 DQS2 /DQS2 DQ16 ~ DQ19 RDQS DQS /DQS I/O [0~3] S3 S2 S1 S0 DQS1 /DQS1 DQ8 ~ DQ11 RDQS DQS /DQS I/O [0~3] S3 S2 S1 S0 DQS0 /DQS0 DQ0 ~ DQ3 RCS0 ~ RCS1: U1 ~ U18 RCS2 ~ RCS3: U1 ~ U18 BA0 - BA2: U1 ~ U18 A0 - An: U1 ~ U18 /RAS: U1 ~ U18 /CAS: U1 ~ U18 /WE: U1 ~ U18 RCKE0: U1 ~ U18 RCKE1: U1 ~ U18 RODT0: U1 ~ U18 RODT1: U1 ~ U18 A0 A1 A2 SDA SA0 SA1 SA2 VDDSPD VDD/VDDQ VREF VSS Serial PD U1~U18 U1~U18 U1~U18 Notes: 1. Unless otherwise noted, resistor values are 22 Ohms +/- 5% /ERR_OUT ABSOLUTE MAXIMUM RATINGS Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 9 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx Parameter Symbol Value Unit Voltage on any pin relative to GND Vin, Vout -0.5 ~ 2.3 V Voltage on VDD supply relative to GND VDD -1.0 ~ 2.3 V Voltage on VDDQ supply relative to GND VDDQ -0.5 ~ 2.3 V Storage temperature TSTG -55 ~ +100 C Short circuit current Ios 50 mA Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (SSTL_1.8) Recommended operating conditions (Voltages referenced to GND, Tcase = 0 to 85C) Parameter Symbol Min. Max. Unit Notes Case Temperature Tcase 0 85 C Supply voltage VDD 1.7 1.9 V Supply voltage for DQ, DQS VDDQ 1.7 1.9 V Input reference voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 1, 2 EEPROM Supply Voltage VDDSPD 1.7 3.6 V Input high voltage VIH VREF + 0.125 VDDQ + 0.3 V Input low voltage VIL -0.3 VREF - 0.125 V Input leakage current Single Rank IIL -10 10 A 3 Output leakage current Single Rank IOL -5 5 A 4 Input leakage current Dual Rank IIL -10 10 A 3 Output leakage current Dual Rank IOL -10 10 A 4 Input leakage current Quad Rank IIL -10 10 A 3 Output leakage current Quad Rank IOL -20 20 A 4 Note: 1. Peak to peak AC noise on VREF may not exceed +/- 2% VREF (DC). VREF is also expected to track noise variation in VDD. 2. 3. 4. For any pin under test input of 0 V VIN VDDQ +0.3 V. Any input 0V<Vin<VDD; all other pins not under test = 0V. 0V<VOUT<VDDQ; DQ and ODT disabled CAPACITANCE (VDD = 1.8V, TA = 25C) Min Max Unit Parameter Symbol Single Rank Dual Rank Quad Rank Single Rank Dual Rank Quad Rank Input capacitance (A0 ~ An, BA0 ~ BA1) Input capacitance (/RAS, /CAS, /WE) Input capacitance (CKE0 ~ *CKE1) Input capacitance (/S0 ~*/S3) Input capacitance (CK0, /CK0) Input capacitance (DQS0 ~ DQS17, 400MHz, 533MHz /DQS0 ~ /DQS17) 667MHz Data input/output capacitance (DQ0 ~ 400MHz, 533MHz DQ63, CB0 ~ CB7) 667MHz CIN1 CIN2 CIN3 CIN4 CIN5 CIN6a CIN6b CIN7a CIN7b 10 10 10 10 10 10 7 10 10 10 10 10 10 12 12 12 12 7 12.5 12.5 12.5 12.5 8 9 8.5 9 8.5 12 12 12 12 8 13 12 13 12 7 7.5 7.5 7.5 7.5 *Used in Dual or Quad Rank module only Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 10 of 19 8 21 19 21 19 pF pF pF pF pF pF pF pF pF DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx DC CHARACTERISTICS DEFINITIONS (Recommended operating conditions unless otherwise noted, Tcase = 0 to 85 C) Parameter Operating one bank active-precharge current Symbol Test Condition Unit Note tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /S is HIGH between valid commands; Address bus inputs are mA 1, 2 SWITCHING; Data bus inputs are SWITCHING IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC Operating one bank (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /S is mA 1, 2 active-read-precharge IDD1 HIGH between valid commands; Address bus inputs are SWITCHING; current Data pattern is same as IDD4W Precharge power-down All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address IDD2P mA 1, 3 current bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control IDD2Q mA 1, 3 standby current and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control Precharge standby IDD2N and address bus inputs are SWITCHING; Data bus inputs are mA 1, 3 current SWITCHING Fast PDN Exit IDD3P-F All banks open; tCK = tCK(IDD); CKE is LOW; Active power-down MR(12) = 0 mA 1, 3 Other control and address bus inputs are current Slow PDN Exit IDD3P-S STABLE; Data bus inputs are FLOATING MR(12) = 1 All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Other mA 1, 3 Active standby current IDD3N control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = Operating burst read mA 1, 2 IDD4R tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; address current bus inputs are SWITCHING; Data pattern is same as IDD4W All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, Operating burst write mA 1, 2 IDD4W /S is HIGH between valid commands; Address bus inputs are current SWITCHING; Data bus inputs are SWITCHING tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is Auto refresh current IDD5 HIGH, /S is HIGH between valid commands; Other control and address mA 1, 3 bus inputs are SWITCHING; Data bus inputs are SWITCHING CK and /CK at 0V; CKE < 0.2V; Other control and address bus inputs mA 1, 3 Self refresh current IDD6 are FLOATING; Data bus inputs are FLOATING All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = Operating bank mA 1, 2 tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, /S is HIGH between valid IDD7 interleave read current commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R Note: 1. Calculated values are from component data. ODT disabled. IDD1 and IDD4R are defined with the outputs disabled. Currents are for DDR2 SDRAM components only. 2. Inactive ranks are in IDD2P Precharge Power-Down Standby Current mode. 3. All ranks are in the same IDD current mode. IDD0 Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 11 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx DC CHARACTERISTICS CURRENTS (Single Rank 512Mbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx287214EBP PC2-3200 CL3 (3-3-3) 1260 1530 144 540 630 540 216 900 1620 1440 1890 144 3240 VR5Vx287214EBS PC2-4200 CL4 (4-4-4) 1350 1530 144 540 630 540 216 900 1800 1620 1890 144 3240 VR5Vx287214EBW PC2-5300 CL5 (5-5-5) 1350 1530 144 630 720 540 216 990 2070 1890 1980 144 3240 VR5Vx287214EBZ/Y PC2-6400 CL6/CL5 1530 1710 144 630 720 540 216 990 2340 2160 2070 144 3870 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS (Dual Rank 512Mbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx567214ECP PC2-3200 CL3 (3-3-3) 1404 1674 288 1080 1260 1080 432 1800 1764 1584 3780 288 3384 VR5Vx567214ECS PC2-4200 CL4 (4-4-4) 1494 1674 288 1080 1260 1080 432 1800 1944 1764 3780 288 3384 VR5Vx567214ECW PC2-5300 CL5 (5-5-5) 1494 1674 288 1260 1440 1080 432 1980 2214 2034 3960 288 3384 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 12 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx DC CHARACTERISTICS CURRENTS (Single Rank 1Gbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx567214FBP PC2-3200 CL3 (3-3-3) 1260 1620 126 630 630 540 180 720 1890 1890 3690 126 4680 VR5Vx567214FBS PC2-4200 CL4 (4-4-4) 1260 1710 126 720 720 540 180 810 2250 2250 3780 126 4860 VR5Vx567214FBW PC2-5300 CL5 (5-5-5) 1530 1800 126 720 720 540 180 990 2430 2430 3870 126 5040 VR5Vx567214FBZ/Y PC2-5300 CL6/CL5 1620 1980 126 900 900 720 180 1080 2880 2880 4230 126 6030 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS (Dual Rank 1Gbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx127214FEP VR5Vx127214FCP PC2-3200 CL3 (3-3-3) 1386 1746 252 1260 1260 1080 360 1440 2016 2016 7380 252 4806 VR5Vx127214FES VR5Vx127214FCS PC2-4200 CL4 (4-4-4) 1386 1836 252 1440 1440 1080 360 1620 2376 2376 7560 252 4986 VR5Vx127214FEW VR5Vx127214FCW PC2-5300 CL5 (5-5-5) 1656 1926 252 1440 1440 1080 360 1980 2556 2556 7740 252 5166 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 13 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx DC CHARACTERISTICS CURRENTS (Dual Rank 2Gbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx1227214GBP PC2-3200 CL3 (3-3-3) 1530 1890 270 810 900 720 324 1170 2340 2700 4500 270 5220 VR5Vx127214GBS PC2-4200 CL4 (4-4-4) 1530 1890 270 810 900 720 324 1170 2340 2700 4500 270 5220 VR5Vx127214GBW PC2-5300 CL5 (5-5-5) 1620 1980 270 900 990 720 324 1260 2700 3060 4680 270 5760 VR5Vx127214GBZ/Y PC2-6400 CL6/CL5 1710 2160 270 990 1080 900 324 1440 3060 3600 5040 270 6300 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA DC CHARACTERISTICS CURRENTS (Quad Rank 512Mbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx127214EPP PC2-3200 CL3 (3-3-3) 1692 1962 576 2160 2520 2160 864 3600 2052 1872 7560 576 3672 VR5Vx127214EPS PC2-4200 CL4 (4-4-4) 1782 1962 576 2160 2520 2160 864 3600 2232 2050 7560 576 3672 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 14 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx DC CHARACTERISTICS CURRENTS (Quad Rank 1Gbit) Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 VR5Vx1G7214FPP PC2-3200 CL3 (3-3-3) 1638 1998 504 2520 2520 2160 720 2880 2268 2268 14760 504 5058 VR5Vx1G7214FPS PC2-4200 CL4 (4-4-4) 1638 2088 504 2880 2880 2160 720 3240 2628 2628 15120 504 5238 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 15 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx AC INPUT TEST CONDITIONS Parameter Input reference voltage Input signal maximum peak to peak swing Input signal maximum slew rate Symbol Value Unit Notes VREF VSWING (MAX) SLEW 0.50 * VDDQ 1.0 1.0 V V V/ns 1, 2 Notes: 1. The Input signal minimum slew rate is to be maintain over the range from VIL(DC) max to VIL(AC) min for raising edges and the range from VIH(DC) min to VIL(AC) max for falling edges. 2. AC timings are reference with input waveforms switching from VIL(AC) to VIH(AC) on the positive transition and VIH(AC) to VIL(AC) on the negative transitions. AC OPERATING CONDITIONS (VDD = 1.8V 0.1V, TOPR = 0 to 85 C) Value Parameter Symbol Unit Min Notes Max Input Differential Voltage VID(ac) 0.5 VDDQ +0.6 V 1 0.5*VDDQ -0.175 0.5*VDDQ +0.175 Input Crossing Point Voltage VIX(ac) V 2 Notes: 1. VID (AC) specifies the input differential voltage I Vtr - Vcp I required for switching, where Vtr is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and Vcp is the complementary input (such as /CK, /DQS, /LDQS, /UDQS, /RDQS). The minimum value is equal to VIH (AC) - VIL (AC). The typical value of Vix (AC) is expected to be about 0.5 x VDDQ of the transmitting devices and Vix (AC) is expected to track variations in VDDQ. 2. OCD Default Characteristics Description Min Nom Max Unit Notes Output Impedance Pull-Up and Pull-Down mismatch Output slew rate Notes: 12.6 0 1.5 18 - 23.4 4 4.5 Ohms Ohms V/ns 1, 2 1, 2, 3 1, 4, 5 1. 2. 3. 4. 5. Absolute specifications: 0C Tcase 85C; VDD = 1.8V +/- 0.1V, VDDQ = 1.8V +/- 0.1V. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage. Slew rate measured from vil(ac) to vih(ac). The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 16 of 19 DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx AC CHARACTERISTICS (AC operating conditions unless otherwise noted. Values are for SDRAM only. Reference JEDEC standard JESD82 for register and PLL information.) Symbol tAC tDQSCK tCH tCL tHP tCK tDH(base) tDS(base) tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH(base) tIS(base) tRPRE tRPST tRRD tRRD tFAW tFAW tCCD tWR PC2-3200 PC2-4200 PC2-5300 min max min max min max DQ output access time from CK/CK -600 +600 -500 +500 -450 +450 DQS output access time from CK/CK -500 +500 -450 +450 -400 +400 CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 CK half period min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) Clock cycle time, CL=x 5000 8000 3750 8000 3000 8000 DQ and DM input hold time 275 x 225 x 175 x DQ and DM input setup time 150 x 100 x 100 x Control & Address input pulse width for each input 0.6 x 0.6 x 0.6 x DQ and DM input pulse width for each input 0.35 x 0.35 x 0.35 x tAC tAC tAC Data-out high-impedance time from CK/CK x x x max max max tAC tAC tAC tAC DQS low-impedance time from CK/CK tAC min tAC min max min max max 2*tACmi tAC 2*tACm tAC 2*tAC tAC DQ low-impedance time from CK/CK n max in max min max DQS-DQ skew for DQS and associated DQ signals x 350 x 300 x 240 DQ hold skew factor x 450 x 400 x 340 tHP tHP tHP DQ/DQS output hold time from DQS x x x tQHS tQHS tQHS First DQS latching transition to associated clock -0.25 0.25 -0.25 0.25 -0.25 0.25 edge DQS input high pulse width 0.35 x 0.35 x 0.35 x DQS input low pulse width 0.35 x 0.35 x 0.35 x DQS falling edge to CK setup time 0.2 x 0.2 x 0.2 x DQS falling edge hold time from CK 0.2 x 0.2 x 0.2 x Mode register set command cycle time 2 x 2 x 2 x Write postamble 0.4 0.6 0.4 0.6 0.4 0.6 Write preamble 0.35 x 0.35 x 0.35 x Address and control input hold time 475 x 375 x 275 x Address and control input setup time 350 x 250 x 200 x Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 Active to active command period for 1kb page size 7.5 x 7.5 x 7.5 x products Active to active command period for 2kb page size 10 x 10 x 10 x products Four Bank Activate period for 1kb page size 37.5 37.5 37.5 products Four Bank Activate period for 2kb page size 50 50 50 products CAS to CAS command delay 2 2 2 Write recovery time 15 x 15 x 15 x Parameter PC2-6400 min max - 400 400 - 350 350 0.45 0.55 0.45 0.55 min (tCL, tCH) 2500 8000 125 x 50 x 0.6 x 0.35 x tAC x max tAC tAC min max 2*tAC tAC min max x 200 x 300 tHP x tQHS ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps - 0.25 0.25 tCK 0.35 0.35 0.2 0.2 2 0.4 0.35 250 175 0.9 0.4 x x x x x 0.6 x x x 1.1 0.6 tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK 7.5 x ns 10 x ns 35 ns 45 ns 2 15 x x Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 17 of 19 Units tCK ns DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx AC CHARACTERISTICS PC2-3200 Symbol tRC tRFC tRCD tRP tRAS tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS t t AOND t t CKE AON Parameter t AOF min max min max PC2-6400 min max Units CL = 3 55 ns CL = 4 60 CL = 5 60 57.5 256Mb, 512Mb 105 105 105 105 Auto-Refresh to Active/Auto1Gb 127.5 70000 127.5 70000 127.5 70000 127.5 70000 ns Refresh command period 2Gb 195 195 195 195 CL = 3 15 Active to Read or Write (with and ns CL = 4 15 without Auto-Precharge) delay CL = 5 15 12.5 CL = 3 15 Precharge command period ns CL = 4 15 CL = 5 15 12.5 CL = 3 40 Active to Precharge command 70000 70000 70000 70000 ns CL = 4 45 CL = 5 45 45 Auto precharge write recovery + precharge time WR+tRP x WR+tRP x WR+tRP x WR+tRP x tCK Internal write to read command delay 10 x 7.5 x 7.5 x 7.5 ns Internal read to precharge command delay 7.5 7.5 7.5 7.5 ns tRFC + tRFC + tRFC + tRFC + Exit self refresh to a non-read command ns 10 10 10 10 Exit self refresh to a read command 200 200 200 200 x tCK Exit precharge power down to any non-read 2 x 2 x 2 x 2 x tCK command Exit active power down to read command 2 x 2 x 2 x 2 x tCK Exit active power down to read command 6 - AL 6 - AL 7 - AL 8 - AL tCK (slow exit, lower power) CKE minimum pulse width 3 3 3 3 tCK (high and low pulse width) ODT turn-on delay 2 2 2 2 2 2 2 2 tCK ODT turn-on AOFD ODT turn-off delay t max PC2-5300 Active to Active/Auto-Refresh command period AONPD ODT turn-on(Power-Down mode) t min PC2-4200 ODT turn-off AOFPD ODT turn-off (Power-Down mode) tANPD ODT to power down entry latency tAXPD ODT power down exit latency tOIT OCD drive mode output delay Minimum time clocks remain ON after CKE tDelay asynchronously drops LOW tAC(max) +1 tAC(min)+ 2tCK+tAC 2 (max)+1 2.5 2.5 tAC(max) tAC(min) + 0.6 2.5tCK+ tAC(min)+ tAC(max) 2 +1 tAC(max) +1 tAC(min)+ 2tCK+tAC 2 (max)+1 2.5 2.5 TAC(max) tAC(min) + 0.6 2.5tCK+ tAC(min)+ tAC(max) 2 +1 TAC(max) +0.7 tAC(min)+ 2tCK+tAC 2 (max)+1 2.5 2.5 tAC(max) tAC(min) + 0.6 2.5tCK+ tAC(min)+ tAC(max) 2 +1 tAC(max) ns + 0.7 tAC(min)+ 2tCK+tAC ns 2 (max)+1 2.5 2.5 tCK TAC(max) tAC(min) ns + 0.6 2.5tCK + tAC(min)+ tAC(max) ns 2 +1 3 8 0 tIS+tCK +tIH 3 8 0 tIS+tCK +tIH 3 8 0 tIS+tCK +tIH 3 8 0 tIS+tCK +tIH tAC(min) 12 tAC(min) 12 tAC(min) 12 tAC(min) Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 18 of 19 12 tCK tCK ns ns DDR2 PC2-xx00 ECC REGISTERED VLP DIMM VR5Vxxx7214xxx REVISION HISTORY Revision Release Date A August 29, 2007 B B1 C D October 17, 2008 February 23, 2009 May 21, 2009 July 21, 2009 Description of Change Initial Release. Convert PS5VRxx7214xxx to include address parity. Add 2Gb DDP device configurations Remove stacked BGA options Add PC2-6400 configurations Add 2Gb mono Checked By (Full Name) Brian Ouellette Ken Ishiguro Brian Ouellette Brian Ouellette Brian Ouellette Brian Ouellette STATEMENT OF COMPLIANCE Viking Modular Solutions shall use commercially reasonable efforts to provide components, parts, materials, products and processes to Customer that do not contain: (i) lead, mercury, hexavalent chromium, polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) above 0.1% by weight in homogeneous material or (ii) cadmium above 0.01% by weight of homogeneous material, except as provided in any exemption(s) from RoHS requirements (including the most current version of the "Annex" to Directive 2002/95/EC of 27 January, 2003), as codified in the specific laws of the EU member countries. Viking Modular Solutions strives to obtain appropriate contractual protections from its suppliers in connection with the RoHS Directives. Viking Modular Solutions20091 EllipseFoothill Ranch, CA 92610 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingmodular.com This Data Sheet is subject to change without notice. Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette Page 19 of 19