VR5VR287214EBY - Viking Technology

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 1 of 19

Module Configuration

VMS Part Number Capacity Module

Configuration Device

Package Module

Ranks Performance CAS

Latency

VR5Vx287214EBP 1GB 128Mx72 128M x 4 bit (18) FBGA 1 PC2-3200 CL3 (3-3-3)

VR5Vx287214EBS 1GB 128Mx72 128M x 4 bit (18) FBGA 1 PC2-4200 CL4 (4-4-4)

VR5Vx287214EBW 1GB 128Mx72 128M x 4 bit (18) FBGA 1 PC2-5300 CL5 (5-5-5)

VR5Vx287214EBZ 1GB 128Mx72 128M x 4 bit (18) FBGA 1 PC2-6400 CL6 (6-6-6)

VR5Vx287214EBY 1GB 128Mx72 128M x 4 bit (18) FBGA 1 PC2-6400 CL5 (5-5-5)

VR5Vx567214FBP 2GB 256Mx72 256M x 4 bit (18) FBGA 1 PC2-3200 CL3 (3-3-3)

VR5Vx567214FBS 2GB 256Mx72 256M x 4 bit (18) FBGA 1 PC2-4200 CL4 (4-4-4)

VR5Vx567214FBW 2GB 256Mx72 256M x 4 bit (18) FBGA 1 PC2-5300 CL5 (5-5-5)

VR5Vx567214FBZ 2GB 256Mx72 256M x 4 bit (18) FBGA 1 PC2-6400 CL6 (6-6-6)

VR5Vx567214FBY 2GB 256Mx72 256M x 4 bit (18) FBGA 1 PC2-6400 CL5 (5-5-5)

VR5Vx567214ECP 2GB 256Mx72 128M x 4 bit (36) RAM-Stack™ 2 PC2-3200 CL3 (3-3-3)

VR5Vx567214ECS 2GB 256Mx72 128M x 4 bit (36) RAM-Stack™ 2 PC2-4200 CL4 (4-4-4)

VR5Vx567214ECW 2GB 256Mx72 128M x 4 bit (36) RAM-Stack™ 2 PC2-5300 CL5 (5-5-5)

VR5Vx127214FEP 4GB 512Mx72 256M x 4 bit (36 die) DDP BGA 2 PC2-3200 CL3 (3-3-3)

VR5Vx127214FES 4GB 512Mx72 256M x 4 bit (36 die) DDP BGA 2 PC2-4200 CL4 (4-4-4)

VR5Vx127214FEW 4GB 512Mx72 256M x 4 bit (36 die) DDP BGA 2 PC2-5300 CL5 (5-5-5)

VR5Vx127214GBP 4GB 512Mx72 512M x 4 bit (18) FBGA 1 PC2-3200 CL3 (3-3-3)

VR5Vx127214GBS 4GB 512Mx72 512M x 4 bit (18) FBGA 1 PC2-4200 CL4 (4-4-4)

VR5Vx127214GBW 4GB 512Mx72 512M x 4 bit (18) FBGA 1 PC2-5300 CL5 (5-5-5)

VR5Vx127214GBZ 4GB 512Mx72 512M x 4 bit (18) FBGA 1 PC2-6400 CL6 (6-6-6)

VR5Vx127214GBY 4GB 512Mx72 512M x 4 bit (18) FBGA 1 PC2-6400 CL5 (5-5-5)

VR5Vx127214FCP 4GB 512Mx72 256M x 4 bit (36) RAM-Stack™ 2 PC2-3200 CL3 (3-3-3)

VR5Vx127214FCS 4GB 512Mx72 256M x 4 bit (36) RAM-Stack™ 2 PC2-4200 CL4 (4-4-4)

VR5Vx127214FCW 4GB 512Mx72 256M x 4 bit (36) RAM-Stack™ 2 PC2-5300 CL5 (5-5-5)

VR5Vx127214EPP 4GB 512Mx72 128M x 4 bit (72) RAM-Stack™ 4 PC2-3200 CL3 (3-3-3)

VR5Vx127214EPS 4GB 512Mx72 128M x 4 bit (72) RAM-Stack™ 4 PC2-4200 CL4 (4-4-4)

VR5Vx1G7214FPP 8GB 1Gx72 256M x 4 bit (72) RAM-Stack™ 4 PC2-3200 CL3 (3-3-3)

VR5Vx1G7214FPS 8GB 1Gx72 256M x 4 bit (72) RAM-Stack™ 4 PC2-4200 CL4 (4-4-4)

Notes:

VA = Address Parity

VR = No Address Parity

Features

• Single 1.8V ± 0.1V Power Supply

• Registered inputs with one-clock delay

• CAS Latency: CL 3, 4, 5

• Burst Length (4, 8)

• Burst type (Sequential & Interleave)

• Auto & Self-Refresh.

• 8k/64ms Refresh Period.

• Differential CLK (/CLK) input.

• On-die termination (ODT)

• Off-chip driver (OCD) impedance calibration

• Serial Presence Detect with EEPROM.

• RoHS Compliant* (see last page)

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 2 of 19

PIN CONFIGURATIONS

Pin Front

Side Pin Back

Side Pin Front Side Pin Back

Side Pin Front Side Pin Back Side Pin Front Side Pin Back

Side

1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DQS14

2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 /DQS5 212 /DQS14

3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS

4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46

5 VSS 125 DQS9 35 VSS 155 DQS12 65 VSS 185 CK0 95 DQ42 215 DQ47

6 /DQS0 126 /DQS9 36 /DQS3 156 /DQS12 66 VSS 186 /CK0 96 DQ43 216 VSS

7 DQS0 127 VSS 37 DQS3 157 VSS 67 VDD 187 VDD 97 VSS 217 DQ52

8 VSS 128 DQ6 38 VSS 158 DQ30 68 ***PAR_IN 188 A0 98 DQ48 218 DQ53

9 DQ2 129 DQ7 39 DQ26 159 DQ31 69 VDD 189 VDD 99 DQ49 219 VSS

10 DQ3 130 VSS 40 DQ27 160 VSS 70 A10/AP 190 BA1 100 VSS 220

†/S2

11 VSS 131 DQ12 41 VSS 161 CB4 71 BA0 191 VDDQ 101 SA2 221 †/S3

12 DQ8 132 DQ13 42 CB0 162 CB5 72 VDDQ 192 /RAS 102 NC 222 VSS

13 DQ9 133 VSS 43 CB1 163 VSS 73 /WE 193 /S0 103 VSS 223 DQS15

14 VSS 134 DQS10 44 VSS 164 DQS17 74 /CAS 194 VDDQ 104 /DQS6 224 /DQS15

15 /DQS1 135 /DQS10 45 /DQS8 165 /DQS17 75 VDDQ 195 ODT0 105 DQS6 225 VSS

16 DQS1 136 VSS 46 DQS8 166 VSS 76 **/S1 196 A13 106 VSS 226 DQ54

17 VSS 137 RFU 47 VSS 167 CB6 77 **ODT1 197 VDD 107 DQ50 227 DQ55

18 /RESET 138 RFU 48 CB2 168 CB7 78 VDDQ 198 VSS 108 DQ51 228 VSS

19 NC 139 VSS 49 CB3 169 VSS 79 VSS 199 DQ36 109 VSS 229 DQ60

20 VSS 140 DQ14 50 VSS 170 VDDQ 80 DQ32 200 DQ37 110 DQ56 230 DQ61

21 DQ10 141 DQ15 51 VDDQ 171 **CKE1 81 DQ33 201 VSS 111 DQ57 231 VSS

22 DQ11 142 VSS 52 CKE0 172 VDD 82 VSS 202 DQS13 112 VSS 232 DQS16

23 VSS 143 DQ20 53 VDD 173 ***A15 83 /DQS4 203 /DQS13 113 /DQS7 233 /DQS16

24 DQ16 144 DQ21 54 *BA2 174 ***A14 84 DQS4 204 VSS 114 DQS7 234 VSS

25 DQ17 145 VSS 55

***ERR_OUT 175 VDDQ 85 VSS 205 DQ38 115 VSS 235 DQ62

26 VSS 146 DQS11 56 VDDQ 176 A12 86 DQ34 206 DQ39 116 DQ58 236 DQ63

27 /DQS2 147 /DQS11 57 A11 177 A9 87 DQ35 207 VSS 117 DQ59 237 VSS

28 DQS2 148 VSS 58 A7 178 VDD 88 VSS 208 DQ44 118 VSS 238 VDDSPD

29 VSS 149 DQ22 59 VDD 179 A8 89 DQ40 209 DQ45 119 SDA 239 SA0

30 DQ18 150 DQ23 60 A5 180 A6 90 DQ41 210 VSS 120 SCL 240 SA1

*Pins are used with 1Gbit devices (7214F in PN)

**Pins are not used for single rank module

*** Pins are used on modules with Address Parity

† Pins are used on quad rank modules only.

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 3 of 19

PIN FUNCTION DESCRIPTION

SYMBOL TYPE POLARITY DESCRIPTION

CK0 IN Positive Edge

Positive line of the differential pair of system clock inputs that drives input to the

on-DIMM PLL.

/CK0 IN Negative Edge

Negative line of the differential pair of system clock inputs that drives the input

to the on-DIMM PLL.

CKE [1:0] IN Active High

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers of the SDRAMs. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all

banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

/S [3:0] IN Active Low

Enables the associated SDRAM command decoder when low and disables

decoder when high. When decoder is disabled, new commands are ignored and

previous operations continue. These input signals also disable all outputs

(except CKE and ODT) of the register(s) on the DIMM when both inputs are

high. When both /S[0:1] are high, all register outputs (except CKE, ODT and

Chip select) remain in the previous state. For modules supporting 4 ranks,

/S[2:3] operate similarly to /S[0:1] for a second set of register outputs.

ODT[1:0] IN Active High On-Die Termination control signals

/RAS, /CAS, /WE IN Active Low CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS,

and /WE define the operation to be executed by the SDRAM.

VREF Supply Reference voltage for SSTL18 inputs

VDD Supply

Isolated power supply for the DDR SDRAM output buffers to provide improved

noise immunity

BA [2:0] IN - Selects which SDRAM bank of four or eight is activated.

A [n:0] IN -

During a Bank Activate command cycle, Address defines the row address.

During a Read or Write command cycle, Address defines the column address.

In addition to the column address, AP is used to invoke autoprecharge

operation at the end of the burst read or write cycle. If AP is high, autoprecharge

is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low,

autoprecharge is disabled. During a Precharge command cycle, AP is used in

conjunction with BA0, BA1, and BA2 to control which bank(s) to precharge. If

AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or

BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to

precharge.

DQ [63:0],

CB [7:0] I/O - Data and Check Bit Input/Output pins

VDD, VSS Supply - Power and ground for the DDR SDRAM input buffers and core logic.

DQS [17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data.

/DQS [17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data.

SA [2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to

configure the serial SPD EEPROM address range.

SDA I/O -

This bi-directional pin is used to transfer data into or out of the SPD EEPROM.

A resistor must be connected from the SDA bus line to VDDSPD on the system

planar to act as a pull-up.

SCL IN -

This signal is used to clock data into and out of the SPD EEPROM. A resistor

may be connected from the SCL bus time to VDDSPD on the system planar to

act as a pull-up.

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 4 of 19

PIN FUNCTION DESCRIPTION

SYMBOL TYPE POLARITY DESCRIPTION

VDDSPD Supply -

Serial EEPROM positive power supply (wired to a separate power pin at the

connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt

and 3.3 Volt) operations.

/RESET IN

The RESET pin is connected to the RST pin on the register and to the OE pin

on the PLL. When low, all register outputs will be driven low and the PLL clocks

to the DRAMs and register(s) will be set to low level (the PLL will remain

synchronized with the input clock)

Par_In IN

Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)

Err_Out OUT

Parity error found in the Address and Control bus

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 5 of 19

MECHANICAL OUTLINE

Dimensions are in inches. (Tolerance is +/- 0.005, unless otherwise stated.)

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 6 of 19

FUNCTIONAL BLOCK DIAGRAM (Single Rank)

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 7 of 19

FUNCTIONAL BLOCK DIAGRAM (Dual Rank)

RCKE1

RODT1

RCS1

RCKE0

RODT0

RCS0

VSS

DQS0

DQ0

DQ1

DQ2

DQ3 U5

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 0

U23

I/O 0

I/O 1

I/O 2

I/O 3

CKE

ODT

/D Q S

DQS

DQS1

DQ8

DQ9

DQ10

DQ11 U6

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1

U24

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS2

DQ16

DQ17

DQ18

DQ19 U7

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 2

U25

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS3

DQ24

DQ25

DQ26

DQ27 U8

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 3

U26

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS4

DQ32

DQ33

DQ34

DQ35 U14

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 4

U32

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS5

DQ40

DQ41

DQ42

DQ43 U15

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 5

U33

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS6

DQ48

DQ49

DQ50

DQ51 U16

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 6

U34

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS7

DQ56

DQ57

DQ58

DQ59 U17

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 7

U35

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS8

CB0

CB1

CB2

CB3 U9

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 8

U27

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS9

DQ4

DQ5

DQ6

DQ7 U1

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 9

U19

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS10

DQ12

DQ13

DQ14

DQ15 U2

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 0

U20

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS11

DQ20

DQ21

DQ22

DQ23 U3

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 1

U21

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS12

DQ28

DQ29

DQ30

DQ31 U4

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 2

U22

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS13

DQ36

DQ37

DQ38

DQ39 U10

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 3

U28

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS14

DQ44

DQ45

DQ46

DQ47 U11

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 4

U29

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS15

DQ52

DQ53

DQ54

DQ55 U12

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 5

U30

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS16

DQ60

DQ61

DQ62

DQ63 U13

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 6

U31

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DQS17

CB4

CB5

CB6

CB7 U18

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

/D Q S 1 7

U36

I/O 0

I/O 1

I/O 2

I/O 3

DQS

CKE

ODT

/D Q S

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 8 of 19

FUNCTIONAL BLOCK DIAGRAM (Single/Dual Rank Register, PLL, EEPROM)

CK0

/CK0

/RESET

PCK 0 ~ 6, 8,9 to U1 ~ U36

/PCK 0 ~ 6, 8,9 to U1 ~ U36

PCK7 to Register

/PCK7 to Register

VDDSPD

VDD/VDDQ

VREF

VSS

Serial PD

U1~U36

W P A0 A1 A2

SA0 SA1 SA2

SCL SDA

/PCK 0 ~ 6, 8,9 to U1 ~ U18

BA0 - BA2: U1 ~ U18

DUAL RANK

SINGLE RANK

CK0

/CK0

/RESET

PCK 0 ~ 6, 8,9 to U1 ~ U18

PCK7 to Register

/PCK7 to Register

VDDSPD

VDD/VDDQ

VREF

VSS

Serial PD

U1~U18

/S0

BA0 - BA2

A0 - An

/RAS

/CAS

/WE

CKE0

ODT0

/RESET

PCK7

/PCK7

RCS0: U1 ~ U18

A0 - An: U1 ~ U18

/RAS: U1 ~ U18

/CAS: U1 ~ U18

/WE: U1 ~ U18

RCKE0: U1 ~ U18

RODT0: U1 ~ U18

BA0 - BA2: U1 ~ U36

/S0

/S1

BA0 - BA2

A0 - An

/RAS

/CAS

/WE

CKE0

CKE1

ODT0

ODT1

/RESET

PCK7

/PCK7

RCS0: U1 ~ U18

RCS1: U19 ~ U36

A0 - An: U1 ~ U36

/RAS: U1 ~ U36

/CAS: U1 ~ U36

/WE: U1 ~ U36

RCKE0: U1 ~ U18

RCKE1: U19 ~ U36

RODT0: U1 ~ U18

RODT1: U19 ~ U36

Notes:

The resistor values may vary depending on systems application

PAR_IN /ERR_OUT

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 9 of 19

FUNCTIONAL BLOCK DIAGRAM QUAD RANK

RCKE0

RCS3

RCS1

RCS0

RCKE1

RCS2

DQS1

DQ8 ~ DQ11

/DQS1

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS2

DQ16 ~ DQ19

/DQS2

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS3

DQ24 ~ DQ27

/DQS3

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS4

DQ32 ~ DQ35

/DQS4

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS5

DQ40 ~ DQ43

/DQS5

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS6

DQ48 ~ DQ51

/DQS6

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS7

DQ56 ~ DQ59

/DQS7

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS8

CB0 ~ CB3

/DQS8

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS11

DQ20 ~ DQ23

/DQS11

U12

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS10

DQ12 ~ DQ15

/DQS10

U11

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS12

DQ28 ~ DQ31

/DQS12

U13

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS13

DQ36 ~ DQ39

/DQS13

U14

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS14

DQ44 ~ DQ47

/DQS14

U15

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS15

DQ52 ~ DQ55

/DQS15

U16

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS16

DQ60 ~ DQ63

/DQS16

U17

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

DQS17

CB4 ~ CB7

/DQS17

U18

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

RODT0

RODT1

VSS

DQS0

DQ0 ~ DQ3

/DQS0

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

Notes:

1. Unless otherwise noted, resistor values are 22 Ohms +/- 5%

WP A0 A1 A2

SA0 SA1 SA2

SCL SDA

VDDSPD

VDD/VDDQ

VREF

VSS

Serial PD

U1~U18

CK0

/CK0

/RESET

PCK 0 ~ 6, 8,9 to U1 ~ U18

/PCK 0 ~ 6, 8,9 to U1 ~ U18

PCK7 to Register

/PCK7 to Register

BA0 - BA2: U1 ~ U18

1:2

/S0 ~ /S1

/S2 ~ /S3

BA0 - BA2

A0 - An

/RAS

/CAS

/WE

CKE0

CKE1

ODT0

ODT1

/RESET

PCK7

/PCK7

RCS0 ~ RCS1: U1 ~ U18

RCS2 ~ RCS3: U1 ~ U18

A0 - An: U1 ~ U18

/RAS: U1 ~ U18

/CAS: U1 ~ U18

/WE: U1 ~ U18

RCKE0: U1 ~ U18

RCKE1: U1 ~ U18

RODT0: U1 ~ U18

RODT1: U1 ~ U18

DQS9

DQ4 ~ DQ7

/DQS9

U10

DQS

RDQS

I/O [0~3]

/DQS

ODT0

ODT1

ODT2

ODT3

CKE0

CKE1

CKE2

CKE3

PAR_IN /ERR_OUT

ABSOLUTE MAXIMUM RATINGS

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 10 of 19

Parameter Symbol Value Unit

Voltage on any pin relative to GND Vin, Vout -0.5 ~ 2.3 V

Voltage on VDD supply relative to GND VDD -1.0 ~ 2.3 V

Voltage on VDDQ supply relative to GND VDDQ -0.5 ~ 2.3 V

Storage temperature TSTG -55 ~ +100 °C

Short circuit current Ios 50 mA

Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be

restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect

device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS (SSTL_1.8)

Recommended operating conditions (Voltages referenced to GND, Tcase = 0 to 85°C)

Parameter Symbol Min. Max. Unit Notes

Case Temperature Tcase 0 85 ºC

Supply voltage VDD 1.7 1.9 V

Supply voltage for DQ, DQS VDDQ 1.7 1.9 V

Input reference voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 1, 2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Input high voltage VIH VREF + 0.125 VDDQ + 0.3 V

Input low voltage VIL -0.3 VREF - 0.125 V

Input leakage current Single Rank IIL -10 10 µA 3

Output leakage current Single Rank IOL -5 5 µA 4

Input leakage current Dual Rank IIL -10 10 µA 3

Output leakage current Dual Rank IOL -10 10 µA 4

Input leakage current Quad Rank IIL -10 10 µA 3

Output leakage current Quad Rank IOL -20 20 µA 4

Note: 1. Peak to peak AC noise on VREF may not exceed +/- 2% VREF (DC). VREF is also expected to track noise variation in VDD.

2. For any pin under test input of 0 V ≤ VIN ≤ VDDQ +0.3 V.

3. Any input 0V<Vin<VDD; all other pins not under test = 0V.

4. 0V<VOUT<VDDQ; DQ and ODT disabled

CAPACITANCE (VDD = 1.8V, TA = 25ºC)

Min Max Unit

Parameter Symbol Single

Rank Dual

Rank Quad

Rank Single

Rank Dual

Rank Quad

Rank

Input capacitance (A0 ~ An, BA0 ~ BA1) CIN1 10 10 10 12 12 12 pF

Input capacitance (/RAS, /CAS, /WE) CIN2 10 10 10 12 12 12 pF

Input capacitance (CKE0 ~ *CKE1) CIN3 10 12 pF

Input capacitance (/S0 ~*/S3) CIN4 10 12 pF

Input capacitance (CK0, /CK0) CIN5 7 7 7 8 8 8 pF

400MHz, 533MHz CIN6a 7.5 10 12.5 9 13 21 pF Input capacitance (DQS0 ~ DQS17,

/DQS0 ~ /DQS17) 667MHz CIN6b 7.5 10 12.5 8.5 12 19 pF

400MHz, 533MHz CIN7a 7.5 10 12.5 9 13 21 pF Data input/output capacitance (DQ0 ~

DQ63, CB0 ~ CB7) 667MHz CIN7b 7.5 10 12.5 8.5 12 19 pF

*Used in Dual or Quad Rank module only

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 11 of 19

DC CHARACTERISTICS DEFINITIONS (Recommended operating conditions unless otherwise noted, Tcase = 0 to 85 °C)

Note: 1. Calculated values are from component data. ODT disabled. IDD1 and IDD4R are defined with the outputs disabled. Currents

are for DDR2 SDRAM components only.

2. Inactive ranks are in IDD2P Precharge Power-Down Standby Current mode.

3. All ranks are in the same IDD current mode.

Parameter Symbol Test Condition Unit Note

Operating one bank

active-precharge

current

IDD0

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH,

/S is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

mA 1, 2

Operating one bank

active-read-precharge

current

IDD1

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC

(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /S is

HIGH between valid commands; Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

mA 1, 2

Precharge power-down

current IDD2P All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING mA 1, 3

Precharge quiet

standby current IDD2Q All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING mA 1, 3

Precharge standby

current IDD2N

All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control

and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

mA 1, 3

IDD3P-F Fast PDN Exit

MR(12) = 0 Active power-down

current IDD3P-S

All banks open; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING Slow PDN Exit

MR(12) = 1

mA 1, 3

Active standby current IDD3N

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =

tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Other

control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

mA 1, 3

Operating burst read

current IDD4R

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =

tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; address

bus inputs are SWITCHING; Data pattern is same as IDD4W

mA 1, 2

Operating burst write

current IDD4W

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH,

/S is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

mA 1, 2

Auto refresh current IDD5

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is

HIGH, /S is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA 1, 3

Self refresh current IDD6 CK and /CK at 0V; CKE < 0.2V; Other control and address bus inputs

are FLOATING; Data bus inputs are FLOATING mA 1, 3

Operating bank

interleave read current IDD7

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =

tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD =

tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, /S is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data

pattern is same as IDD4R

mA 1, 2

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 12 of 19

DC CHARACTERISTICS CURRENTS (Single Rank 512Mbit)

Symbol VR5Vx287214EBP

PC2-3200 CL3 (3-3-3) VR5Vx287214EBS

PC2-4200 CL4 (4-4-4) VR5Vx287214EBW

PC2-5300 CL5 (5-5-5) VR5Vx287214EBZ/Y

PC2-6400 CL6/CL5 Unit

IDD0 1260 1350 1350 1530 mA

IDD1 1530 1530 1530 1710 mA

IDD2P 144 144 144 144 mA

IDD2Q 540 540 630 630 mA

IDD2N 630 630 720 720 mA

IDD3P-F 540 540 540 540 mA

IDD3P-S 216 216 216 216 mA

IDD3N 900 900 990 990 mA

IDD4R 1620 1800 2070 2340 mA

IDD4W 1440 1620 1890 2160 mA

IDD5 1890 1890 1980 2070 mA

IDD6 144 144 144 144 mA

IDD7 3240 3240 3240 3870 mA

DC CHARACTERISTICS CURRENTS (Dual Rank 512Mbit)

Symbol VR5Vx567214ECP

PC2-3200 CL3 (3-3-3) VR5Vx567214ECS

PC2-4200 CL4 (4-4-4) VR5Vx567214ECW

PC2-5300 CL5 (5-5-5) Unit

IDD0 1404 1494 1494 mA

IDD1 1674 1674 1674 mA

IDD2P 288 288 288 mA

IDD2Q 1080 1080 1260 mA

IDD2N 1260 1260 1440 mA

IDD3P-F 1080 1080 1080 mA

IDD3P-S 432 432 432 mA

IDD3N 1800 1800 1980 mA

IDD4R 1764 1944 2214 mA

IDD4W 1584 1764 2034 mA

IDD5 3780 3780 3960 mA

IDD6 288 288 288 mA

IDD7 3384 3384 3384 mA

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 13 of 19

DC CHARACTERISTICS CURRENTS (Single Rank 1Gbit)

Symbol VR5Vx567214FBP

PC2-3200 CL3 (3-3-3) VR5Vx567214FBS

PC2-4200 CL4 (4-4-4) VR5Vx567214FBW

PC2-5300 CL5 (5-5-5) VR5Vx567214FBZ/Y

PC2-5300 CL6/CL5 Unit

IDD0 1260 1260 1530 1620 mA

IDD1 1620 1710 1800 1980 mA

IDD2P 126 126 126 126 mA

IDD2Q 630 720 720 900 mA

IDD2N 630 720 720 900 mA

IDD3P-F 540 540 540 720 mA

IDD3P-S 180 180 180 180 mA

IDD3N 720 810 990 1080 mA

IDD4R 1890 2250 2430 2880 mA

IDD4W 1890 2250 2430 2880 mA

IDD5 3690 3780 3870 4230 mA

IDD6 126 126 126 126 mA

IDD7 4680 4860 5040 6030 mA

DC CHARACTERISTICS CURRENTS (Dual Rank 1Gbit)

Symbol

VR5Vx127214FEP

VR5Vx127214FCP

PC2-3200 CL3 (3-3-3)

VR5Vx127214FES

VR5Vx127214FCS

PC2-4200 CL4 (4-4-4)

VR5Vx127214FEW

VR5Vx127214FCW

PC2-5300 CL5 (5-5-5) Unit

IDD0 1386 1386 1656 mA

IDD1 1746 1836 1926 mA

IDD2P 252 252 252 mA

IDD2Q 1260 1440 1440 mA

IDD2N 1260 1440 1440 mA

IDD3P-F 1080 1080 1080 mA

IDD3P-S 360 360 360 mA

IDD3N 1440 1620 1980 mA

IDD4R 2016 2376 2556 mA

IDD4W 2016 2376 2556 mA

IDD5 7380 7560 7740 mA

IDD6 252 252 252 mA

IDD7 4806 4986 5166 mA

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 14 of 19

DC CHARACTERISTICS CURRENTS (Dual Rank 2Gbit)

Symbol VR5Vx1227214GBP

PC2-3200 CL3 (3-3-3) VR5Vx127214GBS

PC2-4200 CL4 (4-4-4) VR5Vx127214GBW

PC2-5300 CL5 (5-5-5) VR5Vx127214GBZ/Y

PC2-6400 CL6/CL5 Unit

IDD0 1530 1530 1620 1710 mA

IDD1 1890 1890 1980 2160 mA

IDD2P 270 270 270 270 mA

IDD2Q 810 810 900 990 mA

IDD2N 900 900 990 1080 mA

IDD3P-F 720 720 720 900 mA

IDD3P-S 324 324 324 324 mA

IDD3N 1170 1170 1260 1440 mA

IDD4R 2340 2340 2700 3060 mA

IDD4W 2700 2700 3060 3600 mA

IDD5 4500 4500 4680 5040 mA

IDD6 270 270 270 270 mA

IDD7 5220 5220 5760 6300 mA

DC CHARACTERISTICS CURRENTS (Quad Rank 512Mbit)

Symbol VR5Vx127214EPP

PC2-3200 CL3 (3-3-3) VR5Vx127214EPS

PC2-4200 CL4 (4-4-4) Unit

IDD0 1692 1782 mA

IDD1 1962 1962 mA

IDD2P 576 576 mA

IDD2Q 2160 2160 mA

IDD2N 2520 2520 mA

IDD3P-F 2160 2160 mA

IDD3P-S 864 864 mA

IDD3N 3600 3600 mA

IDD4R 2052 2232 mA

IDD4W 1872 2050 mA

IDD5 7560 7560 mA

IDD6 576 576 mA

IDD7 3672 3672 mA

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 15 of 19

DC CHARACTERISTICS CURRENTS (Quad Rank 1Gbit)

Symbol VR5Vx1G7214FPP

PC2-3200 CL3 (3-3-3) VR5Vx1G7214FPS

PC2-4200 CL4 (4-4-4) Unit

IDD0 1638 1638 mA

IDD1 1998 2088 mA

IDD2P 504 504 mA

IDD2Q 2520 2880 mA

IDD2N 2520 2880 mA

IDD3P-F 2160 2160 mA

IDD3P-S 720 720 mA

IDD3N 2880 3240 mA

IDD4R 2268 2628 mA

IDD4W 2268 2628 mA

IDD5 14760 15120 mA

IDD6 504 504 mA

IDD7 5058 5238 mA

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 16 of 19

AC INPUT TEST CONDITIONS

Parameter Symbol Value Unit Notes

Input reference voltage VREF 0.50 * VDDQ V

Input signal maximum peak to peak swing VSWING (MAX) 1.0 V

Input signal maximum slew rate SLEW 1.0 V/ns 1, 2

Notes:

1. The Input signal minimum slew rate is to be maintain over the range from VIL(DC) max to VIL(AC) min for raising edges and the range from

VIH(DC) min to VIL(AC) max for falling edges.

2. AC timings are reference with input waveforms switching from VIL(AC) to VIH(AC) on the positive transition and VIH(AC) to VIL(AC) on the

negative transitions.

AC OPERATING CONDITIONS (VDD = 1.8V ± 0.1V, TOPR = 0 to 85 °C)

Value

Parameter Symbol Min Max Unit Notes

Input Differential Voltage VID(ac) 0.5 VDDQ +0.6 V 1

Input Crossing Point Voltage VIX(ac) 0.5*VDDQ -0.175 0.5*VDDQ +0.175 V 2

Notes:

1. VID (AC) specifies the input differential voltage I Vtr – Vcp I required for switching, where Vtr is the true input (such as CK, DQS, LDQS, UDQS,

RDQS) level and Vcp is the complementary input (such as /CK, /DQS, /LDQS, /UDQS, /RDQS). The minimum value is equal to VIH (AC) – VIL

(AC).

2. The typical value of Vix (AC) is expected to be about 0.5 x VDDQ of the transmitting devices and Vix (AC) is expected to track variations in

VDDQ.

OCD Default Characteristics

Description Min Nom Max Unit Notes

Output Impedance 12.6 18 23.4 Ohms 1, 2

Pull-Up and Pull-Down mismatch 0 - 4 Ohms 1, 2, 3

Output slew rate 1.5 - 4.5 V/ns 1, 4, 5

Notes:

1. Absolute specifications: 0°C ≤ Tcase ≤ 85°C; VDD = 1.8V +/- 0.1V, VDDQ = 1.8V +/- 0.1V.

2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.

Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for

values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.

4. Slew rate measured from vil(ac) to vih(ac).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is

guaranteed by design and characterization.

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 17 of 19

AC CHARACTERISTICS (AC operating conditions unless otherwise noted. Values are for SDRAM only. Reference

JEDEC standard JESD82 for register and PLL information.)

PC2-3200 PC2-4200 PC2-5300 PC2-6400

Symbol Parameter min max min max min max min max Units

tAC DQ output access time from CK/CK -600 +600 -500 +500 -450 +450 - 400 400 ps

tDQSCK DQS output access time from CK/CK -500 +500 -450 +450 -400 +400 - 350 350 ps

tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

tHP CK half period min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) min (tCL, tCH) ps

tCK Clock cycle time, CL=x 5000 8000 3750 8000 3000 8000 2500 8000 ps

tDH(base) DQ and DM input hold time 275 x 225 x 175 x 125 x ps

tDS(base) DQ and DM input setup time 150 x 100 x 100 x 50 x ps

tIPW Control & Address input pulse width for each input 0.6 x 0.6 x 0.6 x 0.6 x tCK

tDIPW DQ and DM input pulse width for each input 0.35 x 0.35 x 0.35 x 0.35 x tCK

tHZ Data-out high-impedance time from CK/CK x tAC

max x tAC

max ps

tLZ(DQS) DQS low-impedance time from CK/CK tAC min tAC

max

tAC

min

tAC

max tAC min tAC

max ps

tLZ(DQ) DQ low-impedance time from CK/CK 2*tACmi

tAC

max

2*tACm

tAC

max

2*tAC

min

tAC

max

2*tAC

min

tAC

max ps

tDQSQ DQS-DQ skew for DQS and associated DQ signals x 350 x 300 x 240 x 200 ps

tQHS DQ hold skew factor x 450 x 400 x 340 x 300 ps

tQH DQ/DQS output hold time from DQS tHP -

tQHS x tHP -

tQHS x ps

tDQSS First DQS latching transition to associated clock

edge -0.25 0.25 -0.25 0.25 -0.25 0.25 - 0.25 0.25 tCK

tDQSH DQS input high pulse width 0.35 x 0.35 x 0.35 x 0.35 x tCK

tDQSL DQS input low pulse width 0.35 x 0.35 x 0.35 x 0.35 x tCK

tDSS DQS falling edge to CK setup time 0.2 x 0.2 x 0.2 x 0.2 x tCK

tDSH DQS falling edge hold time from CK 0.2 x 0.2 x 0.2 x 0.2 x tCK

tMRD Mode register set command cycle time 2 x 2 x 2 x 2 x tCK

tWPST Write postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tWPRE Write preamble 0.35 x 0.35 x 0.35 x 0.35 x tCK

tIH(base)

ddress and control input hold time 475 x 375 x 275 x 250 x ps

tIS(base)

ddress and control input setup time 350 x 250 x 200 x 175 x ps

tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

tRRD

ctive to active command period for 1kb page size

products 7.5 x 7.5 x 7.5 x 7.5 x ns

tRRD

ctive to active command period for 2kb page size

products 10 x 10 x 10 x 10 x ns

tFAW Four Bank Activate period for 1kb page size

products 37.5 37.5 37.5 35 ns

tFAW Four Bank Activate period for 2kb page size

products 50 50 50 45 ns

tCCD CAS to CAS command delay 2 2 2 2 x tCK

tWR Write recovery time 15 x 15 x 15 x 15 x ns

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 18 of 19

AC CHARACTERISTICS PC2-3200 PC2-4200 PC2-5300 PC2-6400

Symbol Parameter min max min max min max min max Units

CL = 3 55 - - -

CL = 4 - 60 - -

tRC

ctive to Active/Auto-Refresh

command period CL = 5 -

57.5

- ns

256Mb, 512Mb 105 105 105 105

1Gb 127.5 127.5 127.5 127.5

tRFC

uto-Refresh to Active/Auto-

Refresh command period 2Gb 195

70000

195

70000

195

70000

195

70000 ns

CL = 3 15 - - -

CL = 4 - 15 - -

tRCD

ctive to Read or Write (with and

without Auto-Precharge) delay CL = 5 -

12.5

- ns

CL = 3 15 - - -

CL = 4 - 15 - -

tRP Precharge command period

CL = 5 -

12.5

- ns

CL = 3 40 - - -

CL = 4 - 45 - -

tRAS

ctive to Precharge command

CL = 5 -

70000

70000 ns

tDAL

uto precharge write recovery + precharge time WR+tRP x WR+tRP x WR+tRP x WR+tRP x tCK

tWTR Internal write to read command delay 10 x 7.5 x 7.5 x 7.5 ns

tRTP Internal read to precharge command delay 7.5 7.5 7.5 7.5 ns

tXSNR Exit self refresh to a non-read command tRFC +

10 tRFC +

10 ns

tXSRD Exit self refresh to a read command 200 200 200 200 x tCK

tXP Exit precharge power down to any non-read

command 2 x 2 x 2 x 2 x tCK

tXARD Exit active power down to read command 2 x 2 x 2 x 2 x tCK

tXARDS Exit active power down to read command

(slow exit, lower power) 6 - AL 6 - AL 7 - AL 8 - AL tCK

tCKE CKE minimum pulse width

(high and low pulse width) 3 3 3 3 tCK

tAOND ODT turn-on delay 2 2 2 2 2 2 2 2 tCK

tAON ODT turn-on tAC(min) tAC(max)

+1 tAC(min) tAC(max)

+1 tAC(min) TAC(max)

+0.7 tAC(min) tAC(max)

+ 0.7 ns

tAONPD ODT turn-on(Power-Down mode) tAC(min)+

2 2tCK+tAC

(max)+1 tAC(min)+

2 2tCK+tAC

(max)+1 tAC(min)+

2 2tCK+tAC

(max)+1 tAC(min)+

2 2tCK+tAC

(max)+1

tAOFD ODT turn-off delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5

tCK

tAOF ODT turn-off tAC(min) tAC(max)

+ 0.6 tAC(min) TAC(max)

+ 0.6 tAC(min) tAC(max)

+ 0.6 tAC(min) TAC(max)

+ 0.6 ns

tAOFPD ODT turn-off (Power-Down mode) tAC(min)+

2.5tCK+

tAC(max)

tAC(min)+

2.5tCK+

tAC(max)

tAC(min)+

2.5tCK+

tAC(max)

tAC(min)+

2.5tCK +

tAC(max)

+1 ns

tANPD ODT to power down entry latency 3 3 3 3 tCK

tAXPD ODT power down exit latency 8 8 8 8 tCK

tOIT OCD drive mode output delay 0 12 0 12 0 12 0 12 ns

tDelay Minimum time clocks remain ON after CKE

asynchronously drops LOW

tIS+tCK

+tIH tIS+tCK

+tIH ns

DDR2 PC2-xx00

ECC REGISTERED VLP DIMM

VR5Vxxx7214xxx

Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610

Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com

This Data Sheet is subject to change without notice.

Doc. # PS5Vxxx7214xxx  Revision D  Created By: Brian Ouellette

Page 19 of 19

REVISION HISTORY

Revision Release Date Description of Change Checked By (Full Name)

A August 29, 2007 Initial Release. Convert PS5VRxx7214xxx

to include address parity.

Brian Ouellette

Ken Ishiguro

B October 17, 2008 Add 2Gb DDP device configurations Brian Ouellette

B1 February 23, 2009 Remove stacked BGA options Brian Ouellette

C May 21, 2009 Add PC2-6400 configurations Brian Ouellette

D July 21, 2009 Add 2Gb mono Brian Ouellette

STATEMENT OF COMPLIANCE

Viking Modular Solutions shall use commercially reasonable efforts to provide components, parts, materials, products and

processes to Customer that do not contain: (i) lead, mercury, hexavalent chromium, polybrominated biphenyls (PBB) and

polybrominated diphenyl ethers (PBDE) above 0.1% by weight in homogeneous material or (ii) cadmium above 0.01% by

weight of homogeneous material, except as provided in any exemption(s) from RoHS requirements (including the most

current version of the “Annex” to Directive 2002/95/EC of 27 January, 2003), as codified in the specific laws of the EU

member countries. Viking Modular Solutions strives to obtain appropriate contractual protections from its suppliers in

connection with the RoHS Directives.