DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7214xxx
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette
Page 11 of 19
DC CHARACTERISTICS DEFINITIONS (Recommended operating conditions unless otherwise noted, Tcase = 0 to 85 °C)
Note: 1. Calculated values are from component data. ODT disabled. IDD1 and IDD4R are defined with the outputs disabled. Currents
are for DDR2 SDRAM components only.
2. Inactive ranks are in IDD2P Precharge Power-Down Standby Current mode.
3. All ranks are in the same IDD current mode.
Parameter Symbol Test Condition Unit Note
Operating one bank
active-precharge
current
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH,
/S is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
mA 1, 2
Operating one bank
active-read-precharge
current
IDD1
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC
(IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /S is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
mA 1, 2
Precharge power-down
current IDD2P All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING mA 1, 3
Precharge quiet
standby current IDD2Q All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING mA 1, 3
Precharge standby
current IDD2N
All banks idle; tCK = tCK(IDD); CKE is HIGH, /S is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA 1, 3
IDD3P-F Fast PDN Exit
MR(12) = 0 Active power-down
current IDD3P-S
All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING Slow PDN Exit
MR(12) = 1
mA 1, 3
Active standby current IDD3N
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; Other
control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA 1, 3
Operating burst read
current IDD4R
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /S is HIGH between valid commands; address
bus inputs are SWITCHING; Data pattern is same as IDD4W
mA 1, 2
Operating burst write
current IDD4W
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH,
/S is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
mA 1, 2
Auto refresh current IDD5
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is
HIGH, /S is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA 1, 3
Self refresh current IDD6 CK and /CK at 0V; CKE < 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING mA 1, 3
Operating bank
interleave read current IDD7
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD =
tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, /S is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data
pattern is same as IDD4R
mA 1, 2