74HC244DTR2G - ON Semiconductor - Datasheet.Directory

March, 2007 − Rev. 0

1Publication Order Number:

74HC244/D

74HC244

Octal 3−State Noninverting

Buffer/Line Driver/

Line Receiver

High−Performance Silicon−Gate CMOS

The 74HC244 is identical in pinout to the LS244. The device inputs

are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed

to be used with 3−state memory address drivers, clock drivers, and

other bus−oriented systems. The device has noninverting outputs and

two active−low output enables.

The HC244 is similar in function to the HC240A.

Features

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 136 FETs or 34 Equivalent Gates

•This is a Pb−Free Device

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MARKING

DIAGRAM

244

ALYW G

TSSOP−20

DT SUFFIX

CASE 948E

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

HC244 = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

74HC244

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LOGIC DIAGRAM

DATA

INPUTS

B4 17

218

3YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING

OUTPUTS

PIN 20 = VCC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A

ENABLE B

FUNCTION TABLE

Inputs Outputs

Enable A,

Enable B A, B YA, YB

LLL

LHH

HXZ

Z = high impedance

PIN ASSIGNMENT

YB4

ENABLE A

GND

YB1

YB2

YB3 5

YA2

YA1

ENABLE B

VCC

YA4

YA3

ORDERING INFORMATION

Device Package Shipping†

74HC244DTR2G TSSOP−20* 2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V

Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±35 mA

ICC DC Supply Current, VCC and GND Pins ±75 mA

PDPower Dissipation in Still Air, TSSOP Package† 450 mW

Tstg Storage Temperature – 65 to + 150 _C

TLLead Temperature, 1 mm from Case for 10 Seconds

(TSSOP Package) 260

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device

reliability.

†Derating — TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

74HC244

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RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TAOperating Temperature, All Package Types – 55 + 125 _C

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

1000

500

400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol Parameter Test Conditions

VCC

(V)

– 55 to

25_Cv 85_Cv 125_CUnit

VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

VIL Maximum Low−Level Input Voltage Vout = 0.1 V

|Iout| v 20 mA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

VOH Minimum High−Level Output

Voltage

Vin = VIH

|Iout| v 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

VOL Maximum Low−Level Output

Voltage

Vin = VIL

|Iout| v 20 mA

2.0

4.5

6.0

0.1

Vin = VIL |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

3.0

4.5

6.0

0.26

0.33

0.4

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

IOZ Maximum Three−State Leakage

Current

Output in High−Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0 ±0.5 ±5.0 ±10 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 mA

6.0 4.0 40 40 mA

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

74HC244

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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol Parameter

VCC

(V)

Guaranteed Limit

Unit

– 55 to

25_Cv85_Cv125_C

tPLH,

tPHL

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

2.0

3.0

4.5

6.0

115

135

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

140

165

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

3.0

4.5

6.0

110

140

165

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

3.0

4.5

6.0

Cin Maximum Input Capacitance −10 10 10 pF

Cout Maximum Three−State Output Capacitance

(Output in High−Impedance State)

−15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

CPD Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

Figure 1. Figure 2.

VCC

GND

DATA INPUT

A OR B

OUTPUT

YA OR YB

10%

50%

90%

10%

50%

90%

tTLH

tPLH tPHL

tTHL

ENABLE

A OR B

OUTPUT Y

50%

90%

10%

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

74HC244

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TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)

Data input pins. Data on these pins appear in noninverted

form on the corresponding Y outputs, when the outputs are

enabled.

CONTROLS

Enable A, Enable B (Pins 1, 19)

Output enables (active−low). When a low level is applied

to these pins, the outputs are enabled and the devices

function as noninverting buffers. When a high level is

applied, the outputs assume the high impedance state.

OUTPUTS

YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4

(Pins 18, 16, 14, 12, 9, 7, 5, 3)

Device outputs. Depending upon the state of the

output−enable pins, these outputs are either noninverting

outputs or high−impedance outputs.

LOGIC DETAIL

DATA

INPUT

A OR B

ENABLE A OR

ENABLE B

TO THREE OTHER

A OR B INVERTERS

ONE OF 8

INVERTERS

VCC

74HC244

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

−−− −−−

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

74HC244

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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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74HC244/D

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