LTC5540IUH#TRPBF - Linear Technology Corporation

LTC5540

5540f

Typical applicaTion

DescripTion

600MHz to 1.3GHz

High Dynamic Range

Downconverting Mixer

The LTC

5540 is part of a family of high dynamic range, high

gain passive downconverting mixers covering the 600MHz

to 4GHz frequency range. The LTC5540 is optimized for

0.6GHz to 1.3GHz RF applications. The LO frequency

must fall within the 0.7GHz to 1.2GHz range for optimum

performance. A typical application is a LTE or GSM receiver

with a 700MHz to 915MHz RF input and high-side LO.

The LTC5540 is designed for 3.3V operation, however; the

IF ampliﬁer can be powered by 5V for the highest P1dB.

An integrated SPDT LO switch with fast switching accepts

two active LO signals, while providing high isolation.

The LTC5540’s high conversion gain and high dynamic

range enable the use of lossy IF ﬁlters in high-selectivity

receiver designs, while minimizing the total solution cost,

board space and system-level variation.

High Dynamic Range Downconverting Mixer Family

PART# RF RANGE LO RANGE

LTC5540 600MHz –1.3GHz 700MHz – 1.2GHz

LTC5541 1.3GHz – 2.3GHz 1.4GHz – 2.0GHz

LTC5542 1.6GHz – 2.7GHz 1.7GHz – 2.5GHz

LTC5543 2.3GHz – 4GHz 2.4GHz – 3.6GHz

FeaTures

applicaTions

n Conversion Gain: 7.9dB at 900MHz

n IIP3: 25.9dBm at 900MHz

n Noise Figure: 9.9dB at 900MHz

n 16.2dB NF Under +5dBm Blocking

n High Input P1dB

n 3.3V Supply, 640mW Power Consumption

n Shutdown Pin

n 50Ω Single-Ended RF and LO Inputs

n LO Inputs 50Ω Matched when Shutdown

n High Isolation LO Switch

n 0dBm LO Drive Level

n High LO-RF and LO-IF Isolation

n Small Solution Size

n 20-Lead (5mm × 5mm) QFN package

n Wireless Infrastructure Receivers

(LTE, GSM, W-CDMA)

n Point-to-Point Microwave links

n High Dynamic Range Downmixer Applications

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

AMP ADC

700MHz

915MHz

LNA

BIAS

SYNTH 2

SYNTH 1

VCCIF

3.3V or 5V 22pF

5.6pF

1.5pF

1µF 150nH 150nH

1nF

190MHz

SAW

190MHz

BPF

IMAGE

BPF

SHDN

22pF

SHDN

(0V/3.3V)

LTC5540

VCC2

VCC 3.3V

VCC1 VCC3 LOSEL

LO SELECT

(0V/3.3V)

1090MHz

ALTERNATE LO FOR

FREQUENCY-HOPPING

100pF

LO1

LO2

IF+IF–

5540 TA01

1µF

Wideband Receiver

Wideband Conversion Gain, IIP3

and NF vs RF Input Frequency

RF FREQUENCY (MHz)

600

GC (dB), NF (dB)

IIP3 (dBm)

900 1000700

5540 TA01a

800

IIP3

TA = +25°C

fIF = 190MHz

fLO = fRF + fIF

LTC5540

5540f

pin conFiguraTionabsoluTe MaxiMuM raTings

Mixer Supply Voltage (VCC1, VCC2)...........................3.8V

LO Switch Supply Voltage (VCC3).............................3.8V

IF Supply Voltage (IF+, IF–) ......................................5.5V

Shutdown Voltage (SHDN) ................–0.3V to VCC +0.3V

LO Select Voltage (LOSEL) ................–0.3V to VCC +0.3V

LO1, LO2 Input Power (0.2GHz to 2GHz) ...............9dBm

LO1, LO2 Input DC Voltage ....................................±0.5V

RF Input Power (0.2GHz to 2GHz) ........................15dBm

RF Input DC Voltage ............................................... ±0.1V

Operating Temperature Range .................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Junction Temperature (TJ) .................................... 150°C

(Note 1)

20 19 18 17 16

6 7 8

TOP VIEW

GND

UH PACKAGE

20-LEAD (5mm s 5mm) PLASTIC QFN

9 10

GND

SHDN

LO2

VCC3

GND

LO1

IFBIAS

IF+

IF–

GND

IFGND

VCC2

LOBIAS

VCC1

LOSEL

GND

TJMAX = 150°C, θJA = 34°C/W, θJC = 3°C/W

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC5540IUH#PBF LTC5540IUH#TRPBF 5540 20-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ac elecTrical characTerisTics

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm,

unless otherwise noted. Test circuit shown in Figure 1. (Notes 2, 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

LO Input Frequency Range 700 to 1200 MHz

RF Input Frequency Range Low-Side LO

High-Side LO

800 to 1300

600 to 1100

MHz

IF Output Frequency Range Requires External Matching 5 to 500 MHz

RF Input Return Loss ZO = 50Ω, 600MHz to 1300MHz >12 dB

LO Input Return Loss ZO = 50Ω, 700MHz to 1200MHz >12 dB

IF Output Return Loss Requires External Matching >12 dB

LO Input Power fLO = 700MHz to 1200MHz –4 0 6 dBm

LO to RF Leakage fLO = 700MHz to 1200MHz <–30 dBm

LO to IF Leakage fLO = 700MHz to 1200MHz <–37 dBm

LO Switch Isolation LO1 Selected, 700MHz < fLO < 1200MHz

LO2 Selected, 700MHz < fLO < 1200MHz

>50

>47

RF to LO Isolation fRF = 600MHz to 1300MHz >55 dB

RF to IF Isolation fRF = 600MHz to 1300MHz >37 dB

LTC5540

5540f

High-Side LO Downmixer Application: RF = 600MHz to 1100MHz, IF = 190MHz, fLO = fRF+fIF

PARAMETER CONDITIONS MIN TYP MAX UNITS

Conversion Gain RF = 700MHz

RF = 900MHz

RF = 1100MHz

6.3

7.6

7.9

Conversion Gain Flatness RF = 900 ±30MHz, LO = 1090MHz, IF=190 ±30MHz ±0.20 dB

Conversion Gain vs Temperature TA = –40ºC to +85ºC, RF = 900MHz –0.008 dB/°C

Input 3rd Order Intercept RF = 700MHz

RF = 900MHz

RF = 1100MHz

23.4

26.5

25.9

23.8

dBm

SSB Noise Figure RF = 700MHz

RF = 900MHz

RF = 1100MHz

10.0

9.9

10.4

11.7

SSB Noise Figure Under Blocking fRF = 900MHz, fLO = 1090MHz,

fBLOCK = 800MHz, PBLOCK = 5dBm

16.2 dB

2LO – 2RF Output Spurious Product

(fRF = fLO – fIF/2)

fRF = 995MHz at –10dBm, fLO = 1090MHz, fIF = 190MHz –70 dBc

3LO – 3RF Output Spurious Product

(fRF = fLO – fIF/3)

fRF = 1026.67MHz at –10dBm, fLO = 1090MHz, fIF = 190MHz –75 dBc

Input 1dB Compression RF = 900MHz, VCCIF = 3.3V

RF = 900MHz, VCCIF = 5V

14.5

dBm

ac elecTrical characTerisTics

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm,

PRF = –3dBm (∆f = 2MHz for two-tone IIP3 tests),unless otherwise noted. Test circuit shown in Figure 1. (Notes 2, 3, 4)

Low-Side LO Downmixer Application: RF = 800MHz-1300MHz, IF = 190MHz, fLO = fRF–fIF

PARAMETER CONDITIONS MIN TYP MAX UNITS

Conversion Gain RF = 900MHz

RF = 1100MHz

RF = 1300MHz

7.0

7.8

8.0

Conversion Gain Flatness RF = 900MHz ±30MHz, LO = 710MHz, IF = 190 ±30MHz ±0.33 dB

Conversion Gain vs Temperature TA = –40°C to 85°C, RF = 900MHz –0.007 dB/°C

Input 3rd Order Intercept RF = 900MHz

RF = 1100MHz

RF = 1300MHz

24.4

24.1

23.6

dBm

SSB Noise Figure RF = 900MHz

RF = 1100MHz

RF = 1300MHz

10.6

10.5

10.3

SSB Noise Figure Under Blocking fRF = 900MHz, fLO = 710MHz, fIF = 190MHz,

fBLOCK = 1000MHz, PBLOCK = 5dBm

16.7 dB

2RF – 2LO Output Spurious Product

(fRF = fLO + fIF/2)

fRF = 805MHz at –10dBm, fLO = 710MHz,

fIF = 190MHz

–61.5 dBc

3RF – 3LO Output Spurious Product

(fRF = fLO + fIF/3)

fRF = 773.33MHz at –10dBm, fLO = 710MHz,

fIF = 190MHz

–68 dBc

Input 1dB Compression RF = 900MHz, VCCIF = 3.3V

RF = 900MHz, VCCIF = 5V

dBm

LTC5540

5540f

Dc elecTrical characTerisTics

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, unless otherwise

noted. Test circuit shown in Figure 1. (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply Requirements (VCC, VCCIF)

VCC Supply Voltage (Pins 6, 8 and 14) 3.1 3.3 3.5 V

VCCIF Supply Voltage (Pins 18 and 19) 3.1 3.3 5.3 V

VCC Supply Current (Pins 6 + 8 + 14)

VCCIF Supply Current (Pins 18 + 19)

Total Supply Current (VCC + VCCIF)

193

116

120

236

Total Supply Current – Shutdown SHDN = High 500 µA

Shutdown Logic Input (SHDN) Low = On, High = Off

SHDN Input High Voltage (Off) 3 V

SHDN Input Low Voltage (On) 0.3 V

SHDN Input Current –0.3V to VCC + 0.3V –20 30 µA

Turn On Time 1 µs

Turn Off Time 1.5 µs

LO Select Logic Input (LOSEL) Low = LO1 Selected, High = LO2 Selected

LOSEL Input High Voltage 3 V

LOSEL Input Low Voltage 0.3 V

LOSEL Input Current –0.3V to VCC + 0.3V –20 30 µA

LO Switching Time 50 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC5540 is guaranteed functional over the operating

temperature range from –40°C to 85°C.

Note 3: SSB Noise Figure measured with a small-signal noise source,

bandpass ﬁlter and 6dB matching pad on RF input, bandpass ﬁlter and

6dB matching pad on the LO input, and no other RF signals applied.

Note 4: LO switch isolation is measured at the IF output port at the IF

frequency with fLO1 and fLO2 offset by 2MHz.

VCC Supply Current

vs Supply Voltage

(Mixer and LO Switch)

VCCIF Supply Current

vs Supply Voltage (IF Ampliﬁer)

Total Supply Current

vs Temperature (VCC + VCCIF)

Typical Dc perForMance characTerisTics

SHDN = Low, Test circuit shown in Figure 1.

VCC SUPPLY VOLTAGE (V)

3.0

SUPPLY CURRENT (mA)

105

100

110

3.4 3.5 3.63.1 3.2

5540 G01

3.3

85°C

25°C

–40°C

VCCIF SUPPLY VOLTAGE (V)

3.0

SUPPLY CURRENT (mA)

130

110

150

3.3 4.5 4.8 5.1 5.43.6 3.9

5540 G02

4.2

85°C

25°C

–40°C

TEMPERATURE (°C)

–45

160

SUPPLY CURRENT (mA)

200

210

190

180

170

220

–25 55 75 95–5 15

5540 G03

VCC = 3.3V, VCCIF = 5V

(DUAL SUPPLY)

VCC = VCCIF = 3.3V

(SINGLE SUPPLY)

LTC5540

5540f

Typical ac perForMance characTerisTics

700MHz Conversion Gain, IIP3

and NF vs LO Input Power

900MHz Conversion Gain, IIP3

and NF vs LO Input Power

1100MHz Conversion Gain, IIP3

and NF vs LO Input Power

Conversion Gain, IIP3 and NF

vs Supply Voltage (Single Supply)

Conversion Gain, IIP3 and NF

vs IF Supply Voltage (Dual Supply)

900MHz Conversion Gain, IIP3

and RF Input P1dB vs Temperature

High-Side LO

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for two-tone IIP3 tests, ∆f = 2MHz),

IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.

Conversion Gain, IIP3 and NF

vs RF Frequency LO Leakage vs LO Frequency RF Isolation vs RF Frequency

RF FREQUENCY (MHz)

600

GC (dB), IIP3 (dBm)

SSB NF (dB)

900 1000 1100700

5540 G04

800

85°C

25°C

–40°C

IIP3

LO FREQUENCY (MHz)

700

–60

LO LEAKAGE (dBm)

–30

–20

–40

–50

–10

900 1000 1100 1200800

5540 G05

LO-RF

LO-IF

RF FREQUENCY (MHz)

600

ISOLATION (dB)

900 1000 12001100 1300700

5540 G06

800

RF-LO

RF-IF

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

42 6–4

5540 G07

0–2

85°C

25°C

–40°C

IIP3

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

42 6–4

5540 G08

0–2

85°C

25°C

–40°C

IIP3

VCC, VCCIF SUPPLY VOLTAGE (V)

3.0

GC (dB), IIP3 (dBm)

SSB NF (dB)

3.53.4 3.63.1

5540 G10

3.33.2

85°C

25°C

–40°C

IIP3

RF = 900MHz

VCC = VCCIF

VCCIF SUPPLY VOLTAGE (V)

3.0

GC (dB), IIP3 (dBm)

SSB NF (dB)

5 5.53.5

5540 G11

4.54

85°C

25°C

–40°C

IIP3

RF = 900MHz

VCC = 3.3V

TEMPERATURE (°C)

–45

GC (dB), IIP3 (dBm), P1dB (dBm)

35 55 75 95–25

5540 G12

15–5

RF = 900MHz

VCCIF = 5.0V

VCCIF = 3.3V

IIP3

P1dB

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

42 6–4

5540 G09

0–2

85°C

25°C

–40°C

IIP3

LTC5540

5540f

SSB Noise Figure

vs RF Blocker Level

LO Switch Isolation

vs LO Frequency

Wideband Conversion Gain

vs IF Frequency

900MHz Conversion

Gain Distribution 900MHz IIP3 Distribution

900MHz SSB Noise

Figure Distribution

Typical ac perForMance characTerisTics

High-Side LO (continued)

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for two-tone IIP3 tests, ∆f = 2MHz),

IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.

2-Tone IF Output Power, IM3 and

IM5 vs RF Input Power

Single-Tone IF Output Power, 2 × 2

and 3 × 3 Spurs vs RF Input Power

2 × 2 and 3 × 3 Spur Suppression

vs LO Power

RF INPUT POWER (dBm)

–12

–80

–70

–60

OUTPUT POWER (dBm)

–10

–50

–40

–30

–20

0 3 6–9 –6 –3

5540 G14

2LO–2RF

RF = 995MHz

IFOUT

RF = 900MHz

LO = 1090MHz

3LO–3RF

RF = 1026.67MHz

RF INPUT POWER (dBm/TONE)

–12

–80

–70

OUTPUT POWER (dBm/TONE)

–30

–20

–10

–40

–60

–50

–6 –3 0 3 6–9

5540 G13

IFOUT

IM3

IM5

RF1 = 899 MHz

RF2 = 901MHz

LO = 1090MHz

LO INPUT POWER (dBm)

–6

–85

–80

RELATIVE SPUR LEVEL (dBc)

–65

–60

–75

–70

–55

0 3 6–3

5540 G15

RF = 900MHz

PRF = –10dBM

LO = 1090MHz

2LO–2RF

RF = 995MHz

3LO–3RF

RF = 1026.67MHz

LO FREQUENCY (MHz)

700

ISOLATION (dB)

1000 1100 1200 1300800 900

5540 G17

LO1 SELECTED

LO2 SELECTED

RF BLOCKER POWER (dBm)

–20

SSB NF (dBm)

–5 0 5 10–15 –10

5540 G16

RF = 900MHz

BLOCKER = 800MHz

PLO = +6dBm

PLO = +3dBm

PLO = 0dBm

PLO = –3dBm

IF FREQUENCY (MHz)

140

GAIN (dB)

200 220 240160 180

5540 G18

85°C

25°C

–40°C

fRF = 850MHz TO 950MHz

fLO = 1090MHz

GAIN (dB)

6.5

DISTRIBUTION (%)

97 7.5 8

5540 G19

8.5

90°C

25°C

–45°C

IIP3 (dBm)

DISTRIBUTION (%)

2824.5 25 25.5

5540 G20

26 26.5 27 27.5

90°C

25°C

–45°C

NOISE FIGURE (dB)

8 8.5 9 9.5 10 10.5 11 11.5 12

DISTRIBUTION (%)

5540 G21

90°C

25°C

–45°C

LTC5540

5540f

Conversion Gain, IIP3 and NF

vs RF Frequency

900MHz Conversion Gain, IIP3

and RF Input P1dB vs Temperature

Typical ac perForMance characTerisTics

Low-Side LO

VCC = 3.3V, VCCIF = 3.3V, SHDN = Low, TA = 25°C, PLO = 0dBm, PRF = –3dBm (–3dBm/tone for two-tone IIP3 tests, ∆f = 2MHz),

IF = 190MHz, unless otherwise noted. Test circuit shown in Figure 1.

900MHz SSB Noise Figure

vs RF Blocker Level

900MHz Conversion Gain, IIP3

and NF vs LO Power

1300MHz Conversion Gain, IIP3

and NF vs LO Power

1100MHz Conversion Gain, IIP3

and NF vs LO Power

2-Tone IF Output Power, IM3 and

IM5 vs RF Input Power

2 × 2 and 3 × 3 Spur Suppression

vs LO Power

Single-Tone IF Output Power, 2 × 2

and 3 × 3 Spurs vs RF Input Power

RF FREQUENCY (MHz)

800

GC (dB), IIP3 (dBm)

SSB NF (dB)

1100 1200 1300900 1000

5540 G22

85°C

25°C

–40°C

IIP3

RF BLOCKER POWER (dBm)

–20

SSB NF (dB)

–5 0 5 10–15 –10

5540 G23

PLO = +6dBm

PLO = +3dBm

PLO = 0dBm

PLO = –3dBm

RF = 900MHz

BLOCKER = 1000MHz

TEMPERATURE (°C)

–45

GC (dB), IIP3 (dBm), P1dB (dBm)

35 55 75 95–25

5540 G24

15–5

VCCIF = 5.0V

VCCIF = 3.3V

IIP3

P1dB

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

0 2 4 6–4 –2

5540 G25

85°C

25°C

–40°C

IIP3

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

0 2 4 6–4 –2

5540 G26

85°C

25°C

–40°C

IIP3

LO INPUT POWER (dBm)

–6

GC (dB), IIP3 (dBm)

SSB NF (dB)

0 2 4 6–4 –2

5540 G27

85°C

25°C

–40°C

IIP3

RF INPUT POWER (dBm/TONE)

–12

–80

–70

OUTPUT POWER (dBm/TONE)

–30

–20

–10

–40

–60

–50

–6 –3 0 3 6–9

5540 G28

IM3

IM5

RF1 = 899MHz

RF2 = 901MHz

LO = 710MHz

IFOUT

RF INPUT POWER (dBm)

–12

–80

–70

–60

OUTPUT POWER (dBm)

–10

–50

–40

–30

–20

0 3 6–9 –6 –3

5540 G29

2RF–2LO

RF = 805MHz

IFOUT

RF = 900MHz

LO = 710MHz

3RF–3LO

RF = 733.33MHz

LO INPUT POWER (dBm)

–6

–80

–75

RELATIVE SPUR LEVEL (dBc)

–60

–55

–70

–65

–50

0 3 6–3

5540 G30

2RF–2LO

RF = 805MHz

3RF–3LO

RF = 773.33MHz

RF = 900MHz

PRF = –10dBM

LO = 710MHz

LTC5540

5540f

pin FuncTions

NC (Pin 1): This pin is not connected internally. It can be

left ﬂoating, connected to ground or to VCC.

RF (Pin 2): Single-Ended Input for the RF Signal. This pin

is internally connected to the primary side of the RF input

transformer, which has low DC resistance to ground. A series

DC-blocking capacitor should be used to avoid damage

to the integrated transformer. The RF input is impedance

matched, as long as the selected LO input is driven with a

0dBm ±6dB source between 0.7GHz and 1.2GHz.

CT (Pin 3): RF Transformer Secondary Center-Tap. This

pin may require a bypass capacitor to ground. See the

Applications Information section. This pin has an internally

generated bias voltage of 1.2V. It must be DC-isolated

from ground and VCC.

GND (Pins 4, 10, 12, 13, 17, Exposed Pad Pin 21):

Ground. These pins must be soldered to the RF ground

plane on the circuit board. The exposed pad metal of the

package provides both electrical contact to ground and

good thermal contact to the printed circuit board.

SHDN (Pin 5): Shutdown Pin. When the input voltage is

less than 0.3V, the internal circuits supplied through pins

6, 8, 14, 18 and 19 are enabled. When the input voltage

is greater than 3V, all circuits are disabled. Typical input

current is less than 10μA. This pin must not be allowed

to ﬂoat.

VCC2 (Pin 6) and VCC1 (Pin 8): Power Supply Pins for

the LO Buffer and Bias Circuits. These pins are internally

connected and must be externally connected to a regulated

3.3V supply, with bypass capacitors located close to the

pin. Typical current consumption is 97mA.

LOBIAS (Pin 7): This Pin Allows Adjustment of the LO

Buffer Current. Typical DC voltage is 2.2V.

LOSEL (Pin 9): LO1/LO2 Select Pin. When the input voltage

is less than 0.3V, the LO1 port is selected. When the input

voltage is greater than 3V, the LO2 port is selected. Typical

input current is 11μA for LOSEL = 3.3V. This pin must not

be allowed to ﬂoat.

LO1 (Pin 11) and LO2 (Pin 15): Single-Ended Inputs for

the Local Oscillators. These pins are internally biased

at 0V and require external DC blocking capacitors. Both

inputs are internally matched to 50Ω, even when the chip

is disabled (SHDN = high).

VCC3 (Pin 14): Power Supply Pin for the LO Switch. This

pin must be connected to a regulated 3.3V supply and

bypassed to ground with a capacitor near the pin. Typical

DC current consumption is less than 100μA.

IFGND (Pin 16): DC Ground Return for the IF Ampliﬁer.

This pin must be connected to ground to complete the IF

ampliﬁer’s DC current path. Typical DC current is 96mA.

IF– (Pin 18) and IF+ (Pin 19): Open-Collector Differential

Outputs for the IF Ampliﬁer. These pins must be connected

to a DC supply through impedance matching inductors, or

a transformer center-tap. Typical DC current consumption

is 48mA into each pin.

IFBIAS (Pin 20): This Pin Allows Adjustment of the IF Amp

Current. Typical DC voltage is 2.1V.

LTC5540

5540f

block DiagraM

SHDN

PASSIVE

MIXER

VCC2 VCC1

VCC3

GND PINS ARE

NOT SHOWN

LO1

LOSEL

LOBIAS

LO2

IF+

IFBIAS IF–IFGND EXPOSED

PAD

5540 BD

AMP

181920

AMP

BIAS

TesT circuiT

GND

BIAS

DC1431A

BOARD

STACK-UP

(NELCO N4000-13)

0.015”

0.062”

4:1

IFOUT

190MHz

50Ω

C10

L2L1

LTC5540

1617181920

LO2IN

50Ω

LO1IN

50Ω

C6C5

106 8 9

LOSEL

(0V/3.3V)

VCC

3.1V TO 3.5V

97mA

SHDN

(0V/3.3V)

RFIN

50Ω

VCCIF

3.1V TO 5.3V

96mA

IFBIAS IF+IF–GND

GND

LO2

LO1

VCC3

VCC2 VCC1

LOBIAS LOSEL

IFGND

GND

SHDN

5541 TC

REF DES VALUE SIZE COMMENTS

C3, C4 100pF 0402 AVX

C6, C7, C8 22pF 0402 AVX

C5, C9 1µF 0603 AVX

C10 1000pF 0402 AVX

L1, L2 150nH 0603 Coilcraft 0603CS

L3 30nH 0603 Coilcraft 0603CS

R2 2.05k 0402

(Alternate)

TC4-1W-7ALN+

(WBC4-6TLB)

Mini-Circuits

(Coilcraft)

HIGH-SIDE LO

C1 5.6pF 0402 AVX

C2 1.5pF 0402 AVX

LOW-SIDE LO

C1, C2 100pF 0402 AVX

L1, L2 vs IF

Frequencies

IF (MHz) L1, L2 (nH)

140 270

190 150

240 100

380 33

450 22

Figure 1. Standard Downmixer Test Circuit Schematic (190MHz IF)

LTC5540

5540f

Introduction

The LTC5540 consists of a high linearity passive double-

balanced mixer core, IF buffer ampliﬁer, high speed single-

pole double-throw (SPDT) LO switch, LO buffer ampliﬁer

and bias/enable circuits. See Pin Functions section for a

description of each pin function. The RF and LO inputs

are single-ended. The IF output is differential. Low-side or

high-side LO injection can be used. The evaluation circuit,

shown in Figure 1, utilizes bandpass IF output matching and

an IF transformer to realize a 50Ω single-ended IF output.

The evaluation board layout is shown in Figure 2.

applicaTions inForMaTion

Figure 2. Evaluation Board Layout

RF Input

The mixer’s RF input, shown in Figure 3, is connected to

the primary winding of an integrated transformer. A 50Ω

match is realized when a series capacitor, C1, is connected

to the RF input. C1 is also needed for DC blocking if the

RF source has DC voltage present, since the primary side

of the RF transformer is DC-grounded internally. The DC

resistance of the primary is approximately 5Ω.

The secondary winding of the RF transformer is internally

connected to the passive mixer. The center-tap of the

transformer secondary is connected to pin 3 (CT) to allow

the connection of bypass capacitor, C2. The value of C2

is LO frequency-dependent. C2 should be located within

5540 F02

2mm of pin 3 for proper high-frequency decoupling. The

nominal DC voltage on the CT pin is 1.2V.

For the RF input to be properly matched, the selected

LO input must be driven. The values of C1 and C2 can

be chosen to optimize the performance for high-side

or low-side LO (see the table in Figure 1). For high-side

applications, a broadband input match is realized with

C1 = 5.6pF. The measured input return loss is shown in

Figure 4 for LO frequencies of 700MHz, 1090MHz and

1200MHz. As shown in Figure 4, the RF input impedance

is dependent on LO frequency, although a single value of

C1 is adequate to cover a wide RF range.

LTC5540

RFIN

TO MIXER

5540 F03

Figure 3. RF Input Schematic

Figure 4. RF Input Return Loss

FREQUENCY (MHz)

600

–25

RETURN LOSS (dB)

–5

–10

–15

–20

1200700 800 900 1000

5541 F04

1100

LO = 700MHz

LO = 1090MHz

LO = 1200MHz

C1 = 5.6pF

LTC5540

5540f

applicaTions inForMaTion

The RF input impedance and input reﬂection coefﬁcient,

versus RF frequency, is listed in Table 1. The reference

plane for this data is pin 2 of the IC, with no external

matching, and the LO is driven at 1090MHz.

Table 1. RF Input Impedance and S11

(at Pin 2, No External Matching, LO Input Driven at 1090MHz)

(GHz)

RF INPUT

IMPEDANCE

S11

MAG ANGLE

0.4 14.7 + j19.7 0.6 133.8

0.5 18.1 + j24.4 0.6 122.9

0.6 23.1 + j27.7 0.5 113.4

0.7 29.9 + j30.6 0.4 102.3

0.8 39.0 + j32.9 0.4 88.2

0.9 52.8 + j31.7 0.3 67.8

1.0 67.3 + j15.4 0.2 34.3

1.1 55.2 – j13.4 0.1 –61.4

1.2 36.2 – j11.2 0.2 –133.5

1.3 31.2 – j4.8 0.2 –162.4

1.4 29.8 – j0.2 0.3 –179.2

LO2IN

LO1IN

VCC2 VCC1

VCC3

LO BUFFER

MIXER

LTC5540

LO1

LOSELLOBIAS

LO2

5540 F05

BIAS

4mA

LO Inputs

The mixer’s LO input circuit, shown in Figure 5, consists

of an integrated SPDT switch, a balun transformer, and

a two-stage high-speed limiting differential ampliﬁer to

drive the mixer core. The LTC5540’s LO ampliﬁers are

optimized for the 0.7GHz to 1.2GHz LO frequency range.

LO frequencies above or below this frequency range may

be used with degraded performance.

Figure 5. LO Input Schematic

The LO switch is designed for high isolation and fast

(<50ns) switching. This allows the use of two active

synthesizers in frequency-hopping applications. If only

one synthesizer is used, then the unused LO input may

be grounded. The LO switch is powered by VCC3 (Pin 14)

and controlled by the LOSEL logic input (Pin 9). The LO1

and LO2 inputs are always 50Ω-matched when VCC is

applied to the chip, even when the chip is shutdown. The

DC resistance of the selected LO input is approximately

23Ω and the unselected input is approximately 50Ω. A

logic table for the LO switch is shown in Table 2. Measured

LO input return loss is shown in Figure 6.

Table 2. LO Switch Logic Table

LOSEL ACTIVE LO INPUT

Low LO1

High LO2

The LO ampliﬁers are powered by VCC1 and VCC2 (pin 8

and pin 6). When the chip is enabled (SHDN = low), the

internal bias circuit provides a regulated 4mA current to the

ampliﬁer’s bias input, which in turn causes the ampliﬁers

to draw approximately 80mA of DC current. This 4mA

reference is also connected to LOBIAS (Pin 7) to allow

modiﬁcation of the ampliﬁer’s DC bias current for special

applications. The recommended application circuits require

no LO ampliﬁer bias modiﬁcation, so this pin should be

left open-circuited.

Figure 6. LO Input Return loss

FREQUENCY (MHz)

500

–30

RETURN LOSS (dB)

–5

–10

–15

–20

–25

1300600 700 1000 1100800 900

5540 F06

1200

NOT SELECTED

OR SHUTDOWN

SELECTED

C3 = C4 = 100pF

LTC5540

5540f

applicaTions inForMaTion

The nominal LO input level is 0dBm although the limiting

ampliﬁers will deliver excellent performance over a ±6dBm

input power range. LO input power greater than 6dBm

may cause conduction of the internal ESD diodes. Series

capacitors C3 and C4 optimize the input match and provide

DC blocking.

The LO1 input impedance and input reﬂection coefﬁcient,

versus frequency, is shown in Table 3. The LO2 port

is identical due to the symmetric device layout and

packaging.

Table 3. LO1 Input Impedance vs Frequency

(at Pin 11, No External Matching, LOSEL = Low)

FREQUENCY

(GHz)

INPUT

IMPEDANCE

S11

MAG ANGLE

0.6 48.9 + j30.6 0.3 74.9

0.7 62.8 + j29.4 0.28 51.9

0.8 78.0 + j17.2 0.25 23.9

0.9 80.4 – j4.55 0.24 –6.5

1.0 68.3 – j20.5 0.23 –38.4

1.1 54.6 – j24.1 0.23 –66.3

1.2 44.7 – j22.3 0.24 –90.1

1.3 38.1 – j18.7 0.25 –110.5

1.4 33.8 – j14.9 0.26 –127.3

IF Output

The IF ampliﬁer, shown in Figure 7, has differential open-

collector outputs (IF+ and IF–), a DC ground return pin

(IFGND), and a pin for modifying the internal bias (IFBIAS).

The IF outputs must be biased at the supply voltage (VCCIF),

which is applied through matching inductors L1 and L2.

Alternatively, the IF outputs can be biased through the

center tap of a transformer. Each IF output pin draws

approximately 48mA of DC supply current (96mA total).

Resistor R2 is used to improve the impedance match.

IFGND (pin 16) must be grounded or the ampliﬁer will

not draw DC current. Grounding through inductor L3

improves LO-IF and RF-IF leakage performance but is

otherwise not necessary. High DC resistance in L3 will

reduce the IF ampliﬁer supply current, which will degrade

RF performance.

For optimum single-ended performance, the differential

IF outputs must be combined through an external IF

4:1

T1 IFOUT

VCC

C10

L2L1

L3 (OR SHORT)

VCCIF

16181920

AMP

BIAS

96mA

4mA

IFGND

LTC5540

IFBIAS IF–

IF+

(OPTION TO

REDUCE

DC POWER)

5540 F07

Figure 7. IF Ampliﬁer Schematic with Bandpass Match

transformer or discrete IF balun circuit. The evaluation

board (see Figures 1 and 2) uses a 4:1 ratio IF transformer

for impedance transformation and differential to single-

ended transformation. It is also possible to eliminate the

IF transformer and drive differential ﬁlters or ampliﬁers

directly.

The IF output impedance can be modeled as 320Ω in

parallel with 2.3pF at IF frequencies. An equivalent small-

signal model (including bondwire inductance) is shown in

Figure 8. Frequency-dependent differential IF output

impedance is listed in Table 4. This data is referenced

to the package pins (with no external components) and

includes the effects of IC and package parasitics.

19 18

IF+IF–

0.9nH0.9nH

RIF

CIF

LTC5540

5540 F08

Figure 8. IF Output Small-Signal Model

LTC5540

5540f

applicaTions inForMaTion

Bandpass IF Matching

The IF output can be matched for IF frequencies as low

as 70MHz or as high as 500MHz using the bandpass

IF matching shown in Figure 1 and Figure 7. L1 and L2

resonate with the internal IF output capacitance at the

desired IF frequency. The value of L1, L2 is calculated

as follows:

L1 = L2 = 1/[(2 π fIF)2 • 2 • CIF]

where CIF is the internal IF capacitance (listed in Table 4).

Values of L1 and L2 are tabulated in Figure 1 for various IF

frequencies. For IF frequencies below 70MHz, the values

of L1, L2 become unreasonably high and the lowpass

topology shown in Figure 9 is preferred. Measured IF

output return loss for bandpass IF matching is plotted

in Figure 10.

Table 4. IF Output Impedance vs Frequency

FREQUENCY (MHz)

DIFFERENTIAL OUTPUT

IMPEDANCE (RIF || XIF (CIF))

70 674 || -j1137 (2pF)

140 628 || -j569 (2pF)

190 606 || -j419 (2pF)

240 584 || -j316 (2.1pF)

300 561 || -j253 (2.1pF)

380 532 || -j182 (2.3pF)

450 511 || -j154 (2.3pF)

Lowpass IF Matching

An alternative IF matching network shown in Figure 9 uses

a lowpass topology, which provides excellent RF to IF

and LO to IF isolation. VCCIF is supplied through the

center tap of the 4:1 transformer. A lowpass impedance

transformation is realized by shunt elements R2 and

C13 (in parallel with the internal RIF and CIF), and series

inductors L1 and L2. Resistor R2 is used to reduce the

IF output resistance, or it can be deleted for the highest

conversion gain. The ﬁnal impedance transformation to

50Ω is realized by transformer T1. The matching element

values shown in Figure 9 are optimized for a wideband

30MHz-150MHz IF match. The demo board (see Figure 2)

has been laid out to accommodate this matching topology

with very few modiﬁcations.

IF Ampliﬁer Bias

The IF ampliﬁer delivers excellent performance with

VCCIF = 3.3V, which allows the VCC and VCCIF supplies

to be common. With VCCIF increased to 5V, the RF input

P1dB increases by almost 3dB, at the expense of higher

power consumption. Mixer performance at 900MHz is

shown in Table 5 with VCCIF = 3.3V and 5V. For the highest

conversion gain, high-Q wire-wound chip inductors are

recommended for L1 and L2, especially when using

VCCIF = 3.3V. Low-cost multilayer chip inductors may be

substituted, with a slight reduction in conversion gain.

Table 5. Performance Comparison with VCCIF = 3.3V and 5V

(RF = 900MHz, High-Side LO, IF = 190MHz)

VCCIF ICCIF GCP1dB IIP3 NF

3.3V 96 7.9 11 25.9 9.9

5V 99 7.9 14.5 25.9 10.0

Figure 10. IF Output Return Loss - Bandpass Matching

4:1

IFOUT

50Ω

30MHz TO 150MHz

VCCIF

3.1-5.3V

22pF

1819 IF–

IF+

1µF

C13

1.5pF

82nH

LTC5540

5540 F09

Figure 9. IF Output with Lowpass Matching

100nH

FREQUENCY (MHz)

–20

RETURN LOSS (dB)

–5

–10

–15

500100 150 200 250 300 350

5540 F10

400 450

33nH

270nH

150nH

LTC5540

5540f

applicaTions inForMaTion

The IFBIAS pin (pin 20) is available for reducing the DC

current consumption of the IF ampliﬁer, at the expense of

IIP3. This pin should be left open-circuited for optimum

performance. The internal bias circuit produces a 4mA

reference for the IF ampliﬁer, which causes the ampliﬁer

to draw approximately 96mA. If resistor R1 is connected

to pin 20 as shown in Figure 7, a portion of the reference

current can be shunted to ground, resulting in reduced

IF ampliﬁer current. For example, R1 = 1kΩ will shunt

away 1.5mA from pin 20 and the IF ampliﬁer current will

be reduced by 38% to approximately 59mA. The nominal,

open-circuit DC voltage at pin 20 is 2.1V. Table 6 lists RF

performance at 900MHz versus IF ampliﬁer current.

LTC5540

SHDN 500Ω

VCC2

5540 F11

Figure 11. Shutdown Input Circuit

Table 6. Mixer Performance with Reduced IF Ampliﬁer Current

(RF = 900MHz, High-Side LO, IF = 190MHz, VCC = VCCIF = 3.3V)

(kΩ)

ICCIF

(mA)

(dB)

IIP3

(dBm)

P1dB

(dBm)

(dB)

OPEN 96 7.9 25.9 11.0 9.9

4.7 86 7.7 25.3 11.1 9.9

2.2 77 7.6 24.7 11.3 9.9

1 59 7.3 23.0 10.8 9.8

(RF = 900MHz, Low-Side LO, IF = 190MHz, VCC = VCCIF = 3.3V)

(kΩ)

ICCIF

(mA)

(dB)

IIP3

(dBm)

P1dB

(dBm)

(dB)

OPEN 96 7.0 24.4 11.0 10.6

4.7 86 6.9 23.4 11.0 10.6

2.2 77 6.8 23.2 11.1 10.6

1 59 6.3 22.4 10.5 10.5

Shutdown Interface

Figure 11 shows a simpliﬁed schematic of the SHDN pin

interface. To disable the chip, the SHDN voltage must be

higher than 3.0V. If the shutdown function is not required,

the SHDN pin should be connected directly to GND. The

voltage at the SHDN pin should never exceed the power

supply voltage (VCC) by more than 0.3V. If this should

occur, the supply current could be sourced through the

ESD diode, potentially damaging the IC.

The SHDN pin must be pulled high or low. If left ﬂoating,

then the on/off state of the IC will be indeterminate. If a

three-state condition can exist at the SHDN pin, then a

pull-up or pull-down resistor must be used.

Supply Voltage Ramping

Fast ramping of the supply voltage can cause a current

glitch in the internet ESD protection circuits. Depending on

the supply inductance, this could result in a supply voltage

transient that exceeds the maximum rating. A supply voltage

ramp time of greater than 1ms is recommended.

LTC5540

5540f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

5.00 p 0.10

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

2019

BOTTOM VIEW—EXPOSED PAD

2.60 REF 2.70 p 0.10

0.75 p 0.05 R = 0.125

TYP

R = 0.05

TYP

0.25 p 0.05

0.65 BSC

0.200 REF

0.00 – 0.05

(UH20) QFN 0208 REV Ø

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 p0.05

0.25 p0.05

0.65 BSC

2.60 REF 2.70 p 0.05

4.10 p 0.05

5.50 p 0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.30 TYP

OR 0.35 s 45o

CHAMFER

2.70 p 0.10

2.70 p 0.05

UH Package

20-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1818 Rev Ø)

LTC5540

5540f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0410 • PRINTED IN USA

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

Infrastructure

LT5527 400MHz to 3.7GHz, 5V Downconverting Mixer 2.3dB Gain, 23.5dBm IIP3 and 12.5dB NF at 1900MHz, 5V/78mA Supply

LT5557 400MHz to 3.8GHz, 3.3V Downconverting Mixer 2.9dB Gain, 24.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/82mA Supply

LTC6400-X 300MHz Low Distortion IF Amp/ADC Driver Fixed Gain of 8dB, 14dB, 20dB and 26dB; >36dBm OIP3 at 300MHz, Differential I/O

LTC6401-X 140MHz Low Distortion IF Amp/ADC Driver Fixed Gain of 8dB, 14dB, 20dB and 26dB; >40dBm OIP3 at 140MHz, Differential I/O

LTC6416 2GHz 16-Bit ADC Buffer 40.25dBm OIP3 to 300MHz, Programmable Fast Recovery Output Clamping

LTC6412 31dB Linear Analog VGA 35dBm OIP3 at 240MHz, Continuous Gain Range –14dB to 17dB

LT5554 Ultralow Distort IF Digital VGA 48dBm OIP3 at 200MHz, 2dB to 18dB Gain Range, 0.125dB Gain Steps

LT5575 700MHz to 2.7GHz Direct Conversion I/Q

Demodulator

Integrated Baluns, 28dBm IIP3, 13dBm P1dB, 0.03dB I/Q Amplitude Match,

0.4° Phase Match

LT5578 400MHz to 2.7GHz Upconverting Mixer 27dBm OIP3 at 900MHz, 24.2dBm at 1.95GHz, Integrated RF Transformer

LT5579 1.5GHz to 3.8GHz Upconverting Mixer 27.3dBm OIP3 at 2.14GHz, NF = 9.9dB, 3.3V Supply, Single-Ended LO and RF Ports

LTC5598 5MHz to 1.6GHz I/Q Modulator 27.7dBm OIP3 at 140MHz, 22.9dBm at 900MHz, –161.2dBm/Hz Noise Floor

RF Power Detectors

LT5534 50MHz to 3GHz Log RF Power Detector with

60dB Dynamic Range

±1dB Output Variation over Temperature, 38ns Response Time, Log Linear

Response

LT5537 Wide Dynamic Range Log RF/IF Detector Low Frequency to 1GHz, 83dB Log Linear Dynamic Range

LT5570 2.7GHz Mean-Squared Detector ±0.5dB Accuracy Over Temperature and >50dB Dynamic Range, 500ns Rise Time

LT5581 6GHz Low Power RMS Detector 40dB Dynamic Range, ±1dB Accuracy Over Temperature, 1.5mA Supply Current

ADCs

LTC2208 16-Bit, 130Msps ADC 78dBFS Noise Floor, >83dB SFDR at 250MHz

LTC2262-14 14-Bit, 150Msps ADC Ultralow Power 72.8dB SNR, 88dB SFDR, 149mW Power Consumption

LTC2242-12 12-Bit, 250Msps ADC 65.4dB SNR, 78dB SFDR, 740mW Power Consumption

Typical applicaTion

RF INPUT FREQUENCY (MHz)

400

GAIN (dB), NF (dB), IIP3 (dBm)

420 540440 460 480

5541 TA02

500 520

IIP3 TA= 25°C

fIF = 190MHz

fLO = fRF + fIF

400MHz

TO 540MHz

BIAS

3.3pF

6.8pF

SHDN

22pF

SHDN

(0V/3.3V)

LTC5542

VCC2

VCC 3.3V

VCC1 VCC3 LOSEL

10pF

LO1

590MHz

TO 730MHz

LO2

IF+IF–

5540 TA02

1µF

VCCIF

3.3V

OR 5V 22pF 2k

150nH 150nH

1nF

4:1

1µF

IFOUT

190MHz

Gain, NF and IIP3 vs RF Frequency

450MHz Downconverting Mixer Application