MT18VDDT3272DIG-202XX - Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HER EIN ARE SUBJE CT TO CHANGE BY MICRON WITHO U T NOTICE.

pdf: 09005aef80e1141d, source: 09005aef80e11353

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

DDR SDRAM

REGISTERED DIMM

MT18VDDT3272D – 256MB

MT18VDDT6472D – 512MB

MT18VDDT12872D – 1GB

MT18VDDT25672D – 2GB

For the latest data sheet, ple ase refer to the Micron



Web

site: www.micron.com/products/modules

Features

• 184-pin, dual in-line memor y modules (DIMM)

• Fast data transfer rates: PC1600, PC2100, and

PC2700

• Registered input s with one-cloc k delay

• Phase-lock loop (PLL) clock driver to reduce loading

• U t ilizes 200 MT/s, 266 MT/s DDR SDRAM

components

• Supports ECC error detection and correction

• 256MB (32 Meg x 72), 512MB (64 Meg x 72), 1GB

(128 Meg x 72), and 2G B (256 Meg x 72)

•V

DD= VDDQ= +2 .5V

•V

DDSPD = +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs (256MB); 7.8125 µs (512MB, 1GB, 2GB)

maximum average periodic refresh interval

• Serial Presence-Detect (SPD) with EEPROM

• Programmable READ CAS latency

•Gold edge contacts

Figure 1: 184-Pin DIMM (MO-206)

NOTE: 1. Contact Micron for product availability.

2. CL = Device CAS (READ) Latency; registered

mode adds one clock cycle to CL.

OPTIONS MARKING

• Oper ating Temperature Ran g e

Commer c i al No M ar k

Industrial1I

•Package

184-pin DIMM (standard) G

184-pin DIMM (lead-free)1Y

• Memory Clock, Speed, CAS Latency2

7.5ns (13 3 MH z), 266 MT/s, CL = 2 -2621

7.5ns (13 3 MH z), 266 MT/s, CL = 2 -26A1

7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265

10ns (100 MH z) , 200 MT/s, CL = 2 -202

•PCB

Standard 1.7in. (43.18mm) See page 2 note

Lo w Prof ile 1.2in. (30.48mm)1See page 2 note

Standard PCB 1.7in. (43.18mm)

Low Profile PCB 1.2in. (30.48mm)

Table 1: Addr ess Table

256MB 512MB 1GB 2GB

Refresh Count 4K 8K 8K 8K

Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) 16K (A0–A13)

Device Bank Addressing 4 (BA0, B A1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA 0, BA1)

Base Device Configuratio n 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)

Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11) 2K (A0–A9, A11)

Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#)

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

NOTE:

1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

current revision codes. Example: MT18VDDT3272DG-265A1.

2. Contact Micron for product availability.

Table 2: Part Numbers and Timing Parameters

PART NUMBER1MODULE

DENSITY CONFIGURATION MODULE

BANDWIDTH MEMORYCLOCK/

DATA RATE LATENCY

(CL - tRCD - tRP)

MT18VDDT3272D(I)G-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT3272D(I)Y-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT3272D(I)G-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT3272D(I)Y-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT3272D(I)G-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT3272D(I)Y-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT3272D(I)G-202__ 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT3272D(I)Y-202__ 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT6472D(I)G-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT6472D(I)Y-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT6472D(I)G-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT6472D(I)Y-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT6472D(I)G-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT6472D(I)Y-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT6472D(I)G-202__ 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT6472D(I)Y-202__ 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT12872D(I)G-262__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT12872D(I)Y-262__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT12872D(I)G-26A__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT12872D(I)Y-26A__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT12872D(I)G-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT12872D(I)Y-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT12872D(I)G-202__ 1GB 128 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT12872D(I)Y-202__ 1GB 128 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT25672D(I)G-262__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT25672D(I)Y-262__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT18VDDT25672D(I)G-26A__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT25672D(I)Y-26A__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT25672D(I)G-265__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT25672D(I)Y-265__22GB 256 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT25672D(I)G-202__22GB 256 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT25672D(I)Y-202__22GB 256 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

NOTE:

1. Pin 115 is no connect (NC) for 256MB, or A12 for 512MB, 1GB, and 2GB.

2. Pin 167 is NC for 256MB, 512MB, and 1GB, or A13 for 2GB module.

Figure 2: Pin Locations (184-Pin DIMM)

Table 3: Pin Assignment

(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 24 DQ17 47 DQS8 70 VDD

2DQ025 DQS2 48 A0 71 NC

SS 26 VSS 49 CB2 72 DQ48

4DQ127 A9 50 VSS 73 DQ49

5DQS028 DQ18 51 CB3 74 VSS

6DQ229 A7 52 BA1 75 DNU

DD 30 VDDQ53 DQ32 76 DNU

8DQ331DQ1954 VDDQ77VDDQ

9NC32 A5 55 DQ33 78 DQS6

10 RESET# 33 DQ24 56 DQS4 79 DQ50

11 VSS 34 VSS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 VSS 81 VSS

13 DQ9 36 DQS3 59 BA0 82 NC

14 DQS1 37 A4 60 DQ35 83 DQ56

15 VDDQ38 VDD 61 DQ40 84 DQ57

16 DNU 39 DQ26 62 VDDQ85 VDD

17 DNU 40 DQ27 63 WE# 86 DQS7

18 VSS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 VSS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 VSS 89 VSS

21 CKE0 44 CB0 67 DQS5 90 NC

22 VDDQ45 CB1 68 DQ42 91 SDA

23 DQ16 46 VDD 69 DQ43 92 SCL

Table 4: Pin Assignment

(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

93 VSS 116 VSS 139 VSS 162 DQ47

94 DQ4 117 DQ21 140 DM8 163 NC

95 DQ5 118 A11 141 A10 164 VDDQ

96 VDDQ 119 DM2 142 CB6 165 DQ52

97 DM0 120 VDD 143 VDDQ166 DQ53

98 DQ6 121 DQ22 144 CB7 1672NC/A13

99 DQ7 122 A8 145 VSS 168 VDD

100 VSS 123 DQ23 146 DQ36 169 DM6

101 NC 124 VSS 147 DQ37 170 DQ54

102 NC 125 A6 148 VDD 171 DQ55

103 NC 126 DQ28 149 DM4 172 VDDQ

104 VDDQ127 DQ29 150 DQ38 173 NC

105 DQ12 128 VDDQ151 DQ39 174 DQ60

106 DQ13 129 DM3 152 VSS 175 DQ61

107 DM1 130 A3 153 DQ44 176 VSS

108 VDD 131 DQ30 154 RAS# 177 DM7

109 DQ14 132 VSS 155 DQ45 178 DQ62

110 DQ15 133 DQ31 156 VDDQ179 DQ63

111 CKE1 134 CB4 157 S0# 180 VDDQ

112 VDDQ 135 CB5 158 S1# 181 SA0

113 NC 136 VDDQ 159 DM5 182 SA1

114 DQ20 137 CK0 160 VSS 183 SA2

1151NC/A12 138 CK0# 161 DQ46 184 VDDSPD

PIN 1 PIN 52 PIN 53 PIN 92

U1 U2 U3 U4

U11

U12

U5 U6 U7 U8 U9

U10

U14 U15 U17 U18U16

U13

U19 U20 U21 U22

Indicates a VDD or VDDQ pin Indicates a VSS pin

Front View

Low Profile 1.2in. (30.48mm)

Back View

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1

U1 U2 U3 U4 U5 U6 U7 U8 U9

U14 U15 U16 U17 U18 U19 U20 U21 U22

PIN 52 PIN 53 PIN 92

Back View

U10

U11 U12

Front View

Standard 1.7in. (43.18mm)

U13

PIN 93

PIN 144

PIN 145

PIN 184

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

63, 65, 154 WE#, CAS#,

RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

137, 138 CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS) is refer- enced to the crossings of CK and CK#.

21, 111 CKE0–CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clo ck, inpu t b uf fers, and output drivers. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH

operations (all device banks idle), or ACTIVE POWER-DOWN (row

ACTIVE in any device bank). CKE is synchronous for POWER-

DOWN entry and exit, and for SELF REFR ESH entry. CKE is

asynchronous for SELF REFRESH exit and for disablin g the outputs.

CKE must be maintained HIGH throughout read and write

accesses. Input buffers (excluding CK, CK# and CKE) are disabled

during PO WER-DOWN. Input b uf fers (exclud ing CK E) are di sabled

during SELF REFRESH. CKE is an SSTL_2 input but will detect an

LVCMOS LOW level after VDD is applied and until CKE is first

brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2

input only.

157, 158 S0#–S1# Input Chip Select: S# enables (registered LOW) and disables (registered

HIGH) t he command decode r. All comm and s are ma sk ed wh en S#

is registered HIGH. S# is considered part of the command code.

52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

27, 29, 32, 37, 41, 43,

48, 115 (A12), 118, 122,

125, 130, 141, 167 (A13)

A0–A11

(256MB)

A0–A12

(512MB, 1GB)

A0–A13

(2GB)

Input Address Inputs: Provide the row address for ACTIVE commands,

and the column address and auto precharge bit (A10) for READ/

WRITE comma nds, to select one l ocation o ut of the memory a rray

in the respective device bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one

device bank (A10 LOW, device bank selected by BA0, BA1) or all

device banks (A10 HIGH). The address inputs also provide the op-

code during a MODE REGISTER SET command. BA0 and BA1

define which mode register (mode register or extended mode

10 RESET# Input Asynchronously forces all register outputs LOW when RESET# is

LOW. This signal can be used during power-up to ensure CKE is

LOW a nd SDRAM DQ i s High-Z.

5, 14, 25, 36, 47, 56, 67,

78, 86, 97, 107, 119, 129,

140, 149, 159, 169, 177

DQS0–DQS17 Input/

Output Data Strobe: DQS0–DQS8, Output with READ data, input with

WRITE data. DQS is edge-aligned with READ data, centered in

WRITE data. Used to capture data. Data Mask: DQS9–DQS17

function as DM0–DM8 to mask WRITE data when when HIGH.

44, 45, 49, 51, 134, 135,

142, 144 CB0–CB7 Input/

Output Check bits.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

2, 4, 6, 8, 12, 13, 19, 20, 23,

24, 28, 31, 33, 35, 39, 40,

53, 55, 57, 60, 61, 64, 68,

69, 72, 73, 79, 80, 83, 84,

87, 88, 94, 95, 98, 99, 105,

106, 109, 110, 114, 117,

121, 123, 126, 127, 131,

133, 146, 147, 150, 151,

153, 155, 161, 162, 165,

166, 170, 171, 174, 175,

178, 179

DQ0–DQ63 Input/

Output Data I/Os: Data bus.

92 SCL Input Serial Cloc k for P resence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

181, 182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure

the p resenc e-detect device.

91 SDA Input/

Output Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect

portion of the module.

REF Supply SSTL_2 reference voltage.

15, 22, 30, 54, 62, 77, 96,

104, 112, 128, 136, 143,

156, 164, 172, 180

VDDQ Supply DQ Power Supply: +2.5V ±0.2V.

7, 38, 46, 70, 85, 108, 120,

148, 168 VDD Supply Power Supply: +2.5V ±0.2V.

3, 11, 18, 26, 34, 42, 50, 58,

66, 74, 81, 89, 93, 100, 116,

124, 132, 139, 145, 152,

160, 176

VSS Supply Ground.

184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

9, 71, 82 , 90, 101, 1 02, 103,

113, 115 (256MB), 163,

167 (256MB, 512MB, 1GB),

173

NC – No Connect: These pins should be left unconnected.

16, 17, 75, 76 DNU – Do Not Use: These pins are not connected on this module but are

assigned pins on other modules in this product family.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

Figure 3: Functional Block Diagram

SA0

SERIAL PD

SDA

SA1

SA2

S0#

S1#

BA0, BA1

A0-A11 (256MB)

A0-A12 (512MB, 1GB)

A0-A13 (2GB)

RAS#

CAS#

CKE0

CKE1

WE#

RS0#, Rank 0

RS1#, Rank 1

RBA0, RBA1: DDR SDRAMS

RA0-RA11: DDR SDRAMS

RA0-RA12: DDR SDRAMS

RA0-RA13: DDR SDRAMS

RRAS#: DDR SDRAMS

RCAS#: DDR SDRAMS

RCKE0: DDR SDRAMS, Rank 0

RCKE1: DDR SDRAMS, Rank 1

RWE#: DDR SDRAMS

RESET#

CK#

REF

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U17

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U19

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U21

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

RS0#

PLL

DDR SDRAM X 2

SCL

U22

U20

RS1#

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DQS0 DM4

DQS4

DM1

DQS1 DM5

DQS5

U16

DM CS# DQS

DM2

DQS2 DM6

DQS6

DM CS# DQS

U15

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3 DM7

DQS7

DM CS# DQS

U14

DM CS# DQS

DM8

DQS8

U18

DM CS# DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DDQ

DDR SDRAMS

CK0

CK0#

120

U11, U13

U10

U12

SPD

DDSPD

NOTE:

1. All resistor values are 22Ω unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grad es, as re ferenced in the module part number guide at

www.micron.com/numberguide.

Standard mo dules use the following DDR SDRAM devi ces:

MT46V16M8TG (256MB); MT46V32M8TG (512MB); MT46V64M8TG (1GB);

MT46V128M8TG (2G B)

Lead-free modules use:

MT46V16M8P (256MB); MT46V32M8P (512MB); MT46V64M8P (1GB)

MT46V128M8P (2GB)

Contact Micron for availability of IT DIMMs.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

General D e scrip tion

The MT18VDDT3272D, MT18VDDT6472D,

MT18VDDT12872D, and MT18VDDT25672D are high-

speed CMOS, dynamic random-access, 256MB,

512MB, 1GB, and 2GB registered memory modules

organized in a x72 (ECC) configuration. DDR SDRAM

modules use internally configured quad-bank DDR

SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. The double

data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single

re ad or write ac cess for the DDR SDRAM module eff ec-

tively consists of a single 2n-bit wide, one-clock-cycle

data transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM during READs and by the memor y

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

DDR SDRAM modules operate from a differential

clock (CK and CK#); the crossing of CK going HIGH

and CK# going LOW will be referred to as the positive

edge of CK. Commands (address and control signals)

are registered at every positive edge of CK. Input data

is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both

edges of CK.

Read and write accesses to DDR SDRAM modules

are burst o rien ted; acce sses start at a s electe d locat ion

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of a n ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed (BA0, BA1 select device bank; A0–A11

(256MB) or A0–A12 (512MB, 1GB), or A0–A13 (2GB)

select device row ). The address bits registered coinci-

dent with the READ or WRITE command are used to

select the device bank and the starting device column

location f o r the burst access.

DDR SDRAM modules provide for programmable

read or write burst lengths of 2, 4, or 8 locations. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst ac cess.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding

row precharge and activa tion time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more

inform ation regarding DDR SDRAM operation, refer to

the 128Mb, 256Mb, 512Mb, or 1Gb DDR SDRAM com-

pone nt data sheets.

PLL and Register Operation

DDR SDRAM modules operate in registered mode

where the control/address input signals are latched in

the register on one rising clock edge and sent to the

DDR SDRAM devices on the following rising clock

edge (data access is delayed by one clock). A phase-

lock loop (PLL) on the module is used to redrive the

differential clock signals CK and CK# to the DDR

SDRAM devices to minimize system clock loading.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for

use by the customer. System READ/WRITE operations

between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA (2:0), which provide eight unique

DIMM/EEPROM addresses. Write protect (WP) is tied

to ground on the module, permanently disabling hard-

ware write protect.

Mode Regis t e r Definition

The mode register is used to define the specific

mode of operation of DDR SDRAM devices. This defi-

nition includes the selection of a burst length, a burst

type, a CAS latency and an operating mode, as shown

in Figure 4, Mode Register Definition Diagram, on

page 8. The mode register is programmed via the

MODE REGISTER SET command (with BA0 = 0 and

BA1 = 0 ) and will retain the store d informat ion until it

is programmed agai n or the device lose s power (except

for bi t A8, which is self-clearing).

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Reprogramming the mod e register will not al ter th e

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

progress, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

Mode register bits A0–A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-

leaved), A4–A6 specify the CAS latency, and A7–A11

(256MB), or A7–A12 (512MB and 1GB), or A7–A13

(2GB) specify the operating mode.

Bur s t Le ng th

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Figure 4, Mode Register Definition

Diagram. The burst length determines the maximum

number of column lo cations tha t can be acce ssed for a

given READ or WRITE command. Burst lengths of 2, 4,

or 8 locations are available for both the sequential and

the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four and by

A3–Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration. See Note 5 of Table 6, Burst Definition

Table, on page 9). The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. The programmed burst length

applies to both read and write bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequent ia l or interl eaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length , the burs t ty p e an d the sta rt-

ing column address, as shown in Table 6, Burst

Definition Table, on page 9.

Figure 4: Mode Register Definition

Diagram

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A12 A11

BA0

BA1

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

512MB and 1GB Modules

256MB Module

M3 = 0

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

M6-M0

M8 M7

Operating Mode

A10A12 A11BA0BA1

10111214

* M15 and M14 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

A13

M13

* M14 and M13 (BA0 and BA1) must be “0, 0” to select the

base mode register (vs. the extended mode register).

2GB Module

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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NOTE:

1. For a burst length of two, A1-Ai select the two-data-ele-

ment block; A0 selects the first access within the block.

2. For a burst length of four, A2-Ai select the four-data-

element block; A0-A1 select the first access within the

block.

3. For a burst length of eight, A3-Ai select the eight-data-

element block; A0-A2 select the first access within the

block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

5. i = 9 (256MB, 512MB)

i = 9, 11 (1GB, 2GB)

Figure 5: CAS Latency Diagram

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS

Laten c y Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nomina lly coincident with clock edge n + m. Figure 7,

CAS Latency (CL) Table, indicates the operating fre-

quencies at which each CAS latency setting can be

used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Operati ng Mo de

The nor mal operatin g mode is s elected by issuin g a

MODE REGISTER SET command with bits A7–A11

(256MB), or A7–A12 (512MB, 1GB), or A7–A13 (2GB)

each set to zero, and bits A0–A6 set to the desired val-

ues. A DLL reset is ini tiat ed by issuing a MO DE R EGIS-

TER SET comman d with bits A7 an d A9–A11 (256MB),

A7 and A9–A12 (512MB, 1GB), or A7 and A9–A13 (2GB)

each set to zero, bit A8 set to one, and bits A0–A6 set to

the desired values. Although not required by the

Micron device, JEDEC specifications recommend

when a LOAD MODE REGISTER command is issued to

Table 6: Burst Definition Table

BURST

LENGTH STARTING

COLUMN

ADDRESS

ORDER O F ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL TYPE =

INTERLEAVED

2A0

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7: CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED CL = 2 CL = 2.5

-262 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-265 75 ≤ f ≤ 100 75 ≤ f ≤ 133

-202 75 ≤ f ≤ 100 N/A

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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reset the DLL, it should always be followed by a LOAD

MODE REGISTER command to select normal operat-

ing mode.

All other combinations of values for A7–A11

(256MB), or A7–A12 (512MB, 1GB), or A7–A13 (2GB)

are reserved for future use and/or test modes. Test

modes and reserved states should not be used because

unknown operatio n or incompat ibility with future ver-

sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in Figure 6, Extended Mode Register

Definition Diagram. The extended mode register is

programmed via the LOAD MODE REGISTER com-

mand to the mode register (with BA0 = 1 and BA1 = 0)

and will retain the stored information until it is pro-

grammed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both low) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these r equir em ents coul d r es ult in uns pecif ied oper -

ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits se lf r efr es h mode , the DLL

is enabled automatically.) Any time the DLL is

enabled, 200 clock cycles must occur before a READ

command can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E13 and E12 for 256MB; E14 and E13 for

512MB, 1GB; E15 and E14 for 2GB) must be “0, 1” to

select the Extended Mode Register (vs. the base Mode

2. The QFC# option is not supported.

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11A12

BA1BA0

1314

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11

BA1BA0

256MB Module

512MB and 1GB Modules

Operating Mode

Reserved

–

–Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

0Drive Strength

Normal

E2 E0

E1,

Operating Mode

A10A11A12BA1BA0

1011121415

E3E4

–

–0

–

E6 E5

E7E8E9

–

E10E11

–

E12

–

E13

A13

2GB Module

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Commands

Table 8, Commands Truth Table, and Table 9, DM

Operation Truth Table, provide a general reference of

available commands. For a more detailed description

of commands and operations, refer to the 128Mb,

256Mb, 512Mb, or 1Gb DDR SDRAM component data

sheet.

NOTE:

1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11 (256MB), A0–A12 (512MB, 1GB), or A0–A13 (2GB) provide row

address.

3. BA0–BA1 provide device bank address; A0–A9 (256MB, 512MB) or A0–A9, A11 (1GB, 2GB) provide column address; A10

HIGH enables the auto precharge feature (nonpersistent), and A10 LO W disables t he auto precharge feature.

4. Applies only to read bursts with auto precharge d isabled; th is command is und efined (an d should no t be used) for R EAD

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–

BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (256MB), A0–A12

(512MB, 1GB), or A0–A13 (2GB) provide the op-code to be written to the selected mode register.

Table 8: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) HXXX X 1

NO OPERATI ON (NOP) LHHH X 1

ACTIVE (Select bank and activate row) L L H H Bank/Row 2

READ (Select bank and column, and start READ burst) LHLHBank/Col 3

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LHHL X 4

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6, 7

LOAD MODE REGISTER LLLLOp-Code 8

Table 9: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION) DM DQS

WRITE Enable L Valid

WRITE Inhibit HX

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended peri ods may affec t reliab il it y.

Voltage on VDD Supply

Rel a ti ve to VSS. . . . . . . . . . . . . . . . . . . . .-1V to +3.6V

Voltage on VDDQ Supp l y

Rel a ti ve to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs

Rel a ti ve to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Rel a ti ve to VSS. . . . . . . . . . . . . -0.5V to VDDQ +0.5V

Operatin g Temperatu re

TA (ambient - commercial) . . . . . . . .. 0°C to +70°C

TA ambient - (indust rial) . . . . . . . .. -40°C to +85°C

Storage Te mperature (plastic) . . . . . .-55°C to +150°C

Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 32, 36

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39

I/O Reference Voltage VREF 0.49 × VDDQ0.51 × VDDQV 6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤

1.35V (All other pins not under test = 0V)

Command/Address

RAS#, CAS#, WE#,

CKE, S# II-5 5 µA 47

CK, CK# -10 10

DM -4 4

OUTPUT LEAKAGE CURRENT: Dual-Rank DIMM

(DQ are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS IOZ -10 10 µA 47

OUTPUT LEVELS

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA 33, 34

IOL 16.8 – mA

Table 11: AC Input Operating Conditions

Notes: 1–5, 14, 49; notes appear pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 35

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 35

I/O Reference Voltage VREF(AC)0.49 × VDDQ0.51 × VDDQV 6

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Table 12: IDD Specifications and Conditions – 256MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -262

-26A/

-265/

-202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once every

two clock cycles

IDD0a1,017 972 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and

control inputs changing once per clock cycle

IDD1a1,107 1,107 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks

idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

IDD2Pb54 54 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK

MIN; CKE = HIGH; Ad dress and o ther control inputs changing once

per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb810 720 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active;

Power-do wn mode;

CK =

CK (MIN)

; CKE = LOW IDD3Pb450 360 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge ; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

andDQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

IDD3Nb900 810 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

active; Address and control inputs changing once per clock cycle; tCK

= tCK (MIN); IOUT = 0mA

IDD4Ra1,197 1,152 mA 20, 42

OPERATING CURRENT: Burst = 2 ; Writes; Co ntinuous burst; One devi ce

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per

clock cycle

IDD4Wa1,152 1,107 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b3,960 3,960 mA 24, 44

tREFC = 15.625µs IDD5Ab90 90 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b54 36 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE commands

IDD7a2,997 2,952 mA 20, 43

NOTE:

a: Value calcu lat ed as o ne mod ule ran k in this o perati ng c onditi on, an d all other m odul e ranks in I

(CKE LOW ) mod e.

b: Value calcula ted refle c ts all mo dul e r an ks in t his op er a t in g conditio n.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Table 13: IDD Specifications and Conditions – 512MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -262

-26A/

-265/-

202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge ;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once every

two clock cycles

IDD0a1,161 1,116 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge; Burst

= 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control

inputs changing once per clock cycle

IDD1a1,476 1,341 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;

Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb72 72 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK

MIN; CKE = HIGH; Address and other control inputs changing once per

clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb810 810 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active;

Power-down mode;

CK =

CK (M IN); CKE = LOW

IDD3Pb450 450 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;

Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS

inputs changing tw ice per cloc k cycle; Address and o ther control inpu ts

changing once per clock cycle

IDD3Nb900 900 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

active; Address and control inputs changing once per clock cycle; tCK =

tCK (MIN); IOUT = 0mA

IDD4Ra1,386 1,386 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing once per clock cycle;

tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock

cycle

IDD4Wa1,386 1,386 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b4,2 30 4,230 mA 24, 44

tREFC = 7.8125µs IDD5Ab108 108 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b72 72 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE commands

IDD7a3,186 3,186 mA 20, 43

NOTE:

a: V alue calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Va lue calculated reflects all modu le ranks in this operating condition.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Table 14: IDD Specifications an d C o nditions – 1GB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -262

-26A/

-265/

-202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge ;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per cl ock cyle; Addre ss and control inputs changing

once every two clock cycles

IDD0a1,215 1,080 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD1a1,485 1,350 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb90 90 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =

tCK MIN; CKE = HIGH; Address and other control inputs changing

once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb810 720 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN); CKE = LOW

IDD3Pb630 540 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3Nb900 810 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,530 1,350 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,440 1,260 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b5,220 5,040 mA 24, 44

tREFC = 7.8125µs IDD5Ab180 180 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b90 90 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL =

4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address

and control inputs change only during Active READ, or WRITE

commands

IDD7a3,645 3,195 mA 20, 43

NOTE:

a: V alue calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Va lue calculated reflects all modu le ranks in this operating condition.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Table 15: IDD Specifications an d C o nditions – 2GB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -262

-26A/

-265/

-202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge ;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per cl ock cyle; Addre ss and control inputs changing

once every two clock cycles

IDD0a1,215 1,395 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD1a1,485 1,710 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb90 180 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =

tCK MIN; CKE = HIGH; Address and other control inputs changing

once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2Fb810 1,080 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN); CKE = LOW

IDD3Pb630 540, mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3Nb810 810 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4Ra1,530 1,890 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4Wa1,440 1,980 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5b5,220 5,940 mA 24, 44

tREFC = 7.8125µs IDD5Ab180 180 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b90 162 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL =

4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address

and control inputs change only during Active READ, or WRITE

commands

IDD7a3,645 4,455 mA 20, 43

NOTE:

a: V alue calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b: Va lue calculated reflects all modu le ranks in this operating condition.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Table 16: Capacitance

Note: 11; notes appear on pages 21–24

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQ, DQS, DM CIO 810 pF

Input Capacitance: Command and Address, S#, CKE CI1 2.5 3.5 pF

Input Capacitance: Command and Address, CK, CK# CI2 –4 pF

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

DDR SDRAM Components Only

Notes: 1–5, 8, 12–15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -262

PARAMETER

SYMBOL MIN MAX UNITS NOTES

Access window of DQs from CK/CK# tAC -0.75 +0.75 ns

CK high-level width tCH 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 7. 5 13 ns 40, 46

CL = 2 tCK (2) 7.5/10 13 ns 40, 46

DQ and DM input hold time relative to DQS tDH 0.5 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.5 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 ns 27

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 ns

DQS input high pulse width tDQSH 0.35 tCK

DQS input low pulse width tDQSL 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 tCK

Half clock period tHP tCH, tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.75 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.75 ns 16, 37

Address and control input hold time (fast slew rate) tIHF0.90 ns 12

Address and control input setup time (fast slew rate) tISF0.90 ns 12

Address and control input hold time (slow slew rate) tIHS1ns12

Address and control input setup time (slow slew rate) tISS1ns12

Address and Control input pulse width (for each input) tIPW 2.20 ns

LOAD MODE REGISTER command cycle time tMRD 15 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -

tQHS ns 22, 23

Data hold skew factor tQHS 0.75 ns

ACTIVE to PRECHARGE command tRAS 40

120,000

ns 31

ACTIVE to READ with Auto precharge command tRAP 15 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 ns

AUTO REFRESH command period 256MB,

512MB, 1GB tRFC 75 ns 44

2GB 120

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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ACTIVE to READ or WRITE delay tRCD 15 ns

PRECHARGE command period tRP 15 ns

DQS read preamble tRPRE 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 tCK 38

ACTIVE bank a to ACTIVE bank b command tRRD 15 ns 38

DQS write preamble tWPRE 0.25 tCK

DQS write preamble setup time tWPRES 0 ns

DQS write postamble tWPST 0.4 0.6 tCK 18, 19

Wr i t e recovery time tWR 15 ns 17

Internal WRITE to READ command delay tWTR 1 tCK

Data valid output window na tQH - tDQSQ ns

REFRESH to REFRESH command interval 256MB tREFC 140.6 µs 21

512MB, 1GB,

2GB 70.3 µs

Average periodic refresh interval 256MB tREFI 15.6 µs 21

512MB, 1GB,

2GB 7.8 µs

Terminating voltage delay to VDD tVTD 0 ns 21

Exit SELF REFRESH to non-READ command 256MB,

512MB tXSNR 75 ns 21

1GB 127.5 ns

Exit SE LF REFRE SH to READ command tXSRD 200 tCK 21

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

(Continued)

DDR SDRAM Components Only

AC CHARACTERISTICS -262

PARAMETER

SYMBOL MIN MAX UNITS NOTES

Table 18: DDR SDRAM Comp onent Electrical Characteristics and

Recommended AC Operating Conditions

Notes: 1–5, 8, 12–15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -26A/-265 -202

PARAMETER

SYM

MIN MAX

MIN

MAX

UNITS NOTES

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 7.50 13.00 8 13 ns 40, 46

CL = 2 tCK (2) 7.50/10 13.00 10 13 ns 40, 46

DQ and DM input hold time relative to DQS tDH 0.5 0.6 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.5 0.6 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns 27

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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DQS-DQ skew, DQS to last DQ valid, per group, per

access tDQSQ 0.50 0.60 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.20 0.20 tCK

DQS falling edge from CK rising - hold time tDSH 0.20 0.20 tCK

Half clock period tHP tCH,tCL tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.75 +0.80 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.75 -0.80 ns 16, 37

Address and control input hold time (fast slew rate) tIHF0.90 1.10 ns 12

Address and control input setup time (fast slew rate) tISF0.90 1.10 ns 12

Address and control input hold time (slow slew rate) tIHS11.10ns12

Address and control input setup time (slow slew rate) tISS11.10ns12

Address and Con tro l input pul se wid th (for each inpu t) tIPW 2.20 2.20 ns

LOAD MODE REGISTER command cycle time tMRD 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per

access tQH tHP -

tQHS

tHP -

tQHS

ns 22, 23

Data hold skew factor tQHS 0.75 1 ns

ACTIVE to PRECHARGE command tRAS 40

120,000

ns 31

ACTIVE to READ with Auto precharge command

tRAP 20 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command period

tRC 65 70 ns

AUTO REFRESH command period 256MB, 512MB,

1GB tRFC 75 80 ns 44

2GB 120 120

ACTIVE to READ or WRITE delay tRCD 20 20 ns

PRECHARGE command period tRP 20 20 ns

DQS read pream ble tRPRE 0.90 1.10 0.90 1.10 tCK 38

DQS read postamble tRPST 0.40 0.60 0.40 0.60 tCK 38

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns

DQS write pr eam ble tWPRE 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 ns 18, 19

DQS write postamble tWPST 0.40 0.60 0.40 0.60 tCK 17

Write recovery time tWR 15 15 ns

Internal WRITE to READ command delay tWTR 11

tCK

Data valid output window na tQH -tDQSQ

QH -

DQSQ

ns 22

REFRESH to REFRESH command

interval 256MB tREFC 140.60 140.60 µs 21

512MB, 1GB,

2GB 70.30 70.30 µs

Table 18: DDR SDRAM Comp onent Electrical Characteristics and

Recommended AC Operating Conditions (Continued)

Notes: 1–5, 8, 12–15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -26A/-265 -202

PARAMETER

SYM

MIN MAX

MIN

MAX

UNITS NOTES

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Average periodic refresh interval 256MB tREFI 15.62 15.62 µs 21

512MB, 1GB,

2GB 7.81 7.81 µs

Terminating voltage delay to VDD tVTD 00ns

Exit SELF REFR ESH to non-READ

command 256MB, 512MB tXSNR 75 75 ns 21

1GB 127.5 127.5 ns

Exit SELF REFRESH to READ command tXSRD 200 200 tCK

Table 18: DDR SDRAM Comp onent Electrical Characteristics and

Recommended AC Operating Conditions (Continued)

Notes: 1–5, 8, 12–15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -26A/-265 -202

PARAMETER

SYM

MIN MAX

MIN

MAX

UNITS NOTES

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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Notes

1. All voltages reference d to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

er enc e/ s upp l y volta ge level s, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fica ti ons are guara nteed fo r the spec ified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL(AC)

and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will r emain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of th e tra nsmit-

ting devic e and to trac k variation s in the DC le vel

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

neares t VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent upon output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 2 for -262, -26A, and -202,

CL = 2.5 for -265 with the output s open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized , and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz,

TA= 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to

peak) = 0.2V. DM input is grouped with I/O pins,

reflecting that they are matched in loading.

12.

For slew rates < 1V/ns and

≥

0.5Vns. If slew rate is <

0.5V/ns, timing must be derated:

IS has an addi-

tional 50ps per each 100 mV/ns reduction in slew

rate from 500 mV/ns, while

IH is unaff ected. If slew

rate exceeds 4.5 V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inpu ts are not r ecogniz ed as val i d un ti l VREF stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is

VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

para meters ar e not refer enced t o a spec ific v oltag e

level, but specify when the device output is no

longer dr iving (HZ) or begins driving (LZ).

17. The Don’t Care state after completion of the post-

amble means that the DQS-driven signal should

either be high, low, or high-Z, and that any signal

transistions within the input switching region

must follow valid input requirements. If DQS

transactions high, above VIH (DC) (MIN), then it

must not transition low, below VIH (DC) (MIN),

prior to tDQSH (MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LO W) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

ple of tCK that meets the maximum absolute

value for tRAS.

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (256MB) or 7.8125µs

(512MB, 1GB, 2GB). However, an AUTO REFRESH

Output

(VOUT)Reference

Point

50Ω

VTT

30pF

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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command must be asserted at least once every

140.6µs (256MB) or 70.3µs (512MB, 1GB, 2GB);

burst refreshing or posting by the DDR SDRAM

controller greater than eight refresh cycles is not

allowed.

22. The valid data window is derived by achieving

other s pe cification s: tHP (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data val id windo w derates

directly porportionally with the clock duty cycle

and a practical data valid window can be derived.

The clock is allowed a maximum duty cycle varia-

tion of 45/55, beyond which functionality is

uncertain. Figure 7, Derating Data Valid Window

(tQH - tDQSQ), shows derating curves duty cycles

ranging between 50/50 and 45/55.

23. E ac h byte lane has a correspondin g DQS .

24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

A C l evel t hro u gh to th e target AC le vel , VIL (A C)

or VIH (AC).

b. Reach at least the t arget AC level.

c. After the AC target level i s reached, conti nu e to

maintain at least the target DC level, VIL (DC)

or VIH (DC).

26. CK and CK# input slew rate must be ≥ 1V/ns (2V/

ns differentially).

27.

DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/

DM/DQS slew rate is less than 0.5 V/ns, timing

must be derated: 50ps must be added to

DS and

DH for each 100 mv/ns reduction in slew rate. If

slew rate exceeds 4 V/ns, functionality is uncer-

tain.

Figure 7: Derating Data Valid Window

(tQH - tDQSQ)

3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250

3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

-26A/-265 @ tCK = 10ns

-202 @ tCK = 10ns

-26A/-265 @ tCK = 7.5ns

-202 @ tCK = 8ns

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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28. VDD must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

30. tHP min is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK/ inputs, colle ctively during ban k active.

31. READs and WRITEs with auto precharge are not

allowed to be issue d un til tRA S(MI N) ca n be sa tis-

fied prior to the internal precharge command

being issued.

32. A ny positive glitch in the nom i nal voltage mu st be

less than 1/3 of the clock and not more than

+400mV or 2.9V, whichever is less. Any negative

glitc h must be less th an 1/3 of the cl ock cycle an d

not exceed either -300mV or 2.2V, whichever is

mor e positi ve . H owever, the DC av erage cannot be

below 2.3V minimum.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 8,

Pull-Down Characteristics.

b. The variation in driver pull-down current

within nomin al limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure 8, Pull-Down Characteristic s.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 9,

Pull-Up Characteris tics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner boun ding lines of the V-I cur ve of Figure

9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0V, and

at the same voltage and temperature.

34. The full variation in the ratio of the nominal pull-

up to p ull-down current should be unity ±10 p er-

cent, for device drain-to-source voltages from

0.1V to 1.0V. The voltage levels used are derived

from a minimum VDD level and the referenced

test load. In practice, the voltage levels obtained

from a properly terminated bus will provide sig-

nific antly different voltage values.

35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. VIL u ndershoot:

VIL(MIN) = -1.5V for a pulse width ≤ 3ns and the

pulse width can not be greater than 1/3 of the

cycle rate.

36. VDD and VDDQ must track each ot her.

37. tHZ (MAX) will prevail over tDQSCK (MAX) +

tRPST (MAX) condition. tLZ (MIN) will prevail

over tDQSCK (MIN) + tRPRE (M AX) condition.

38. tRPST end point and tRPRE begin point are not

referenced to a specific voltage level but specify

when the device output is no longer driving

(tRPST), or begins driving (tRPRE).

Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

00.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

-20

IOUT (mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-2000.0 0.5 1.0 1.5 2.0 2.5

VDDQ - VOUT (V)

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

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39. During initialization, VDDQ, VTT, and VREF must

be equa l to or less th an VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0 volts, provided a mini-

mum of 42Ω of series resistance is used between

the VTT supply and the input pin.

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As

such, future die may not reflect this option.

41. For -262, -265, and -26A speed grades, IDD3N is

specified to be 35mA per DDR SDRAM device at

100 MHz.

42. Random addressing changing and 50 percent of

data changing at every transfer.

43. Random addressing changing and 100 percent of

data changing at every transfer.

44. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

tREF later.

45. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

46. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

47. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes .

48.When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or logic LOW.

49. The -335 speed grade will operate with tRAS (MIN)

= 40ns and tRAS (MAX) = 120,000ns at any slower

frequency.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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Initialization

To ensure device operation the DRAM must be ini-

tialized as described below:

1. Simult aneousl y apply power to VDD and VDDQ.

2. Apply VREF and th en VTT power.

3. Asse rt and hold CKE at a LVCMOS logic low.

4. Provide stab le CLOCK signal s.

5. Wait at least 200µs.

6. Bring CKE high and provide at least one NOP or

DESELECT command. At this point the CKE input

changes from a LVCMOS input to a SSTL2 input

only and will remain a SSTL_2 input unless a

power cy cle oc c urs.

7. Perform a PRECHARGE ALL command.

8. Wait at least tRP time, during this time NOPs or

DESELECT commands must be given.

9. Using the LMR command program the Extended

Mode Reg ister (E0 = 0 to enable the DLL and E1 =

0 for normal drive or E1 = 1 for reduced drive, E2

through En must be set to 0; where n = most sig-

nific ant bit).

10. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

11. Using the LMR command program the Mode Reg-

ister to set operating parameters and to reset the

DLL. Note at least 200 clock cycles are required

between a DLL reset and any READ command.

12. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

13. Issue a PR EC HARGE ALL comma nd .

14. Wait at least tRP time, only NOPs or DESELECT

commands are allowed.

15. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

16. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

17. Issue an AUTO REFRESH command (Note this

may be moved prior to step 13).

18. Wait at least tRFC time, only NOPs or DESELECT

commands are allowed.

19. Although not required by the Micron device,

JEDEC requires a LMR command to clear the DLL

bit (set M8 = 0). If a LMR command is issued the

same operating parameters should be utilized as

in step 11.

20. Wait at least tMRD time, only NOPs or DESELECT

commands are allowed.

21. At this point the DRAM is ready for any valid com-

mand. Note 200 clock cycles are required between

step 11 (DLL Reset) and any READ comma nd.

Figure 10: Init ialization Flow Diagr a m

and V

Q Ramp

Apply V

REF

and V

CKE must be LVCMOS Low

Apply stable CLOCKs

Bring CKE High with a NOP command

Wait at least 200us

PRECHARGE ALL

Assert NOP or DESELECT for tRP time

Configure Extended Mode Register

Configure Load Mode Register and reset DLL

Assert NOP or DESELECT for tMRD time

PRECHARGE ALL

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRFC time

Optional LMR command to clear DLL bit

Assert NOP or DESELECT for tMRD time

DRAM is ready for any valid command

Step

Assert NOP or DESELECT commands for tRFC

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRP time

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NOTE:

1. The timing and switching specifications for the register listed above ar e critic al for prop er operation of DDR SDRAM Re g-

istered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed

information for this register is available in JEDEC Standard JESD82.

2. Data inputs must be low a minimum time of tact max, after RESET# is taken HIGH.

3. Data and clock in puts must be held at vali d levels (not floating) a m inimum tim e of tinact max, after R ES ET# is t a ken L O W.

4. For data signal input slew rate ≥ 1 V/ns.

5. For data signal input slew rate ≥ 0.5 V/ns and < 1V/ns.

6. CK, CK# signals input slew rate ≥ 1V/ns.

Table 19: Register Timing Requirements and Switching Characteristics

Note: 1

0°C ≤ TA ≤ +70°C

VDD = +2.5V ±0.2V

UNITS NOTESMIN MAX

SSTL

(bit pattern

by JESD82-3

or JESD82-4)

fclock Clock Frequency - 200 MHz

tpd Clock to Output Time 30pF to GND and

50Ω to VTT 1.1 2.8 ns

tPHL Reset to Output Time - 5 ns

twPulse Duration CK, CK# HIGH or

LOW 2.5 - ns

tact Dif fere ntial Inputs Active

Time -22ns 2

tinact Dif f ere nt ial Inpu ts Inac tiv e

Time -22ns 3

tsu Setup Ti me, Fast Slew Rate Data Before CK

HIGH, CK# LOW 0.75 - ns 4, 6

Setup Time, Slow Slew Rate 0.9 - ns 5, 6

thHold Time, Fast Slew Rate Data After CK

HIGH, CK# LOW 0.75 - ns 4, 6

Hold Time, Slow Slew Rate 0.9 - ns 5, 6

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NOTE:

1. The timing and switching spe cifica tions for the PLL listed abo ve ar e cr itic al for pro per ope ration of the DDR S DRAM Re g-

istered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed

information for this PLL is available in JEDEC Standard JESD82.

2. The PLL must be able to handle spread spectrum induced skew.

3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to

meet the other timing parameters. (Used for low speed system debug.)

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its ref-

erence signal after power up.

5. Static Phase Offset does not include Jitter.

6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each

other.

7. The Output Slew Rate is determined from the IBIS model:

Table 20: PLL Clock Driver Timing Requirements and Switching Characteristics

Note: 1

PARAMETER SYMBOL

0°C ≤ TA ≤ +70°C

VDD = +2.5V ±0.2V

UNITS NOTESMIN NOMINAL MAX

Operating Clock Frequency fCK 60 - 170 MHz 2 , 3

Input Duty Cycle tDC 40 - 60 %

Stabilization Time tSTAB --100ms4

Cycle to Cycle Jitter tJITCC -75 - 75 ps

Static Phase Offset t∅-50 0 50 ps 5

Output Clock Skew tSKO--100ps

Period Jitter tJITPER -75 - 75 ps 6

Half-Period Jitter tJITHPER -100 - 100 ps 6

Input Clock Slew Rate tLSI1.0 - 4 V/ns

Output Clock Slew Rate tLSO1.0 - 2 V/ns 7

GND

CDCV857

R=60

Ω

ΩΩ

Ω

R=60

Ω

ΩΩ

Ω

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Figure 11: Component Case Temperature Vs. Air Flow

NOTE:

1. Micron Technology, Inc., recommends a minimum air flow of 1 meter/second (~197 LFM) across modules when installed

in a system.

2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered

memory modules. Case temperatures charted represent worst-case component locations on modules installed in the

internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case an d m ounte d in a Eiffel-typ e low air spe ed win d tun nel. P eriphe ral dev ic es in stalled on the system moth erboa rd

for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test

chamber.

4. The memory dia gnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

max

- memory stress software

ave

- 3D gaming software

ave

- memory stress software

Minimum Air Flow

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SPD Clock and Data Conventions

Data sta tes on th e SDA line ca n change only dur ing

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (as

shown in Figure 12, Data Validity, and Figure 13, Defi-

nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successf ul data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Fig-

ure 14, Acknowledge Response From Receiver).

The SPD device will always respond with an

ackn owledg e af ter recogn ition of a start co ndition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 12: Data Validity Figure 13: Definitio n of Start and Stop

Figur e 14: Acknowle dge Respon se From Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

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Figure 15: SPD EEPROM Timing Diagram

Table 21: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1010SA2SA1SA0RW

Protection Register Select Code 0110SA2SA1SA0RW

Table 22: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0V

IH or VIL 1START, Device Select, RW = ‘0’, Address

IH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ≥ 1 Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL ≤ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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NOTE:

1. To avoid spurious START and STOP condition s, a minimu m delay i s placed betwe en SCL = 1 and the falling or rising edge

of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM inte rnal erase/ program cycle . Durin g the WRITE cycle, the EEP ROM bus interface circuit is disabled, SDA remains

HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 23: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDDSPD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD + 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT:

SCL = SDA = V

- 0.3V; All other inputs = V

or V

ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2mA

Table 24: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequenc y fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

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Table 25: Serial Presence-Detect Matrix – 256MB, 512MB, and 1GB

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 33

BYTE DESCRIPTION ENTRY (VERSION)

MT18VDDT3272D MT18VDDT6472D

MT18VDDT12872D

0Number of SPD Bytes Used by

Micron 128 80 80 80

1Total Number of Bytes In SPD Device 256 08 08 08

2Fundamental Memory Type SDRAM DDR 07 07 07

3Number of Row Addresses on

Assembly 13 0C 0D 0D

4Number of Column Addresses on

Assembly 10 or 11 0A 0A 0B

5Number of Physical Ranks on DIMM 2020202

6Module Data Width 72 48 48 48

7Module Data Width (Continued) 0000000

Module Voltage Interface Levels

SSTL 2.5V 04 04 04

9SDRAM Cycle Time, tCK (CAS

Latency = 2.5) (See note 1) 7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

10 SDRAM Access from Clock, tAC (CAS

Laten c y = 2.5)

0.75ns (-262/-26A/-265)

0.8ns (-202) 75

80 75

11 Module Configuration Type ECC 02 02 02

12 Refresh Rate/Type

15.62µs, 7.81µs/SELF

80 82 82

13 SDRAM Device Width (Primary DDR

SDRAM) 8080808

Error-checking DDR SDRAM Data

Width

8080808

15 Minimum Clo ck Dela y, Back-to-Back

Random Column Access 1 clock 01 01 01

16 Burst Lengths Supported 2, 4, 8 0E 0E 0E

17 Number of Banks on DDR SDRAM

Device 4040404

18 CAS Latencies Supported 2, 2.5 0C 0C 0C

19 CS Latency 0010101

20 WE Latency 1020202

21 SDRAM Module Attributes Registered/Diff. Clock 26 26 26

22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0

23 SDRAM Cycle Time, tCK (CAS

Laten c y = 2) 7.5ns (- 262/-26A)

10ns (-265/-202) 75

A0 75

24 SDRAM Access from CK, tAC (CAS

Laten c y = 2)

0.75ns (-262/-26A/-265)

0.8ns (-202) 75

80 75

25 SDRAM Cycle Time, tCK (CAS

Laten c y = 1.5) N/A 00 00 00

26 SDRAM Access from CK, tAC (CAS

Laten c y = 1.5) N/A 00 00 00

27 Minimum Row Precharge Time, tRP 15ns (-262)

20ns (-26A/- 265 /-20 2) 3C

50 3C

28 Minimum Row Active to Row

Active, tRRD

15ns (-262/-26A/-265/-202)

3C 3C 3C

29 Minimum RAS# to CAS# Delay, tRCD 15ns (-262)

20ns (-26A/- 265 /-20 2) 3C

50 3C

30 Minimum RAS# Pulse Width, tRAS

(See note 2) 45ns (-262/-26 A/-26 5)

40ns (-202) 2D

28 2D

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NOTE:

1. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

31 Module Rank Density 128MB, 256MB,

512MB 20 40 80

32 Address And Command Se tup Tim e,

tISs (See note 3) 1n s (262/-26A/-26 5)

1.1ns (-202) A0

B0 A0

33 Address And Command Hold Time,

tIHs (See note 3) 1ns (-262/-26A/-265)

1.1ns (-202) A0

B0 A0

34 Data/ Data Mask Input Setup Time,

tDS

0.50ns (-262/-26A/-265)

0.6ns (-202) 50

60 50

35 Data/ Data Mask Input Hold T i me,

tDH

0.50ns (-262/-26A/-265)

0.6ns (-202) 50

60 50

36-40 Reserved 00 00 00

41 Min Active Auto Refresh Time tRC 60ns (-262)

65ns (-26A/-265)

70ns (-202)

42 Minimum Auto Refresh to Active/

Auto Refresh Command Period,

tRFC

75ns (-262/-26 A/-26 5)

80ns (-202) 4B

50 4B

43 SDRAM Device Max Cycle Time

tCKMAX

13ns (-262/-26A/-265/-202)

34 34 34

44 SDRAM De vice Max DQS- DQ Skew

Time tDQSQ 0.5ns (-262/-26A/-265)

0.6ns (-202) 32

3C 32

45 SDRAM Device Max Read Data Hold

Skew Factor tQHS

0.75ns (-262/-26A/-265)

1.0ns (-202) 75

A0 75

46 Reserved 00 00 00

47 DIMM Height 10/01 10/01 10/01

48–61 Reserved 00 00 00

62 SPD Revision Release 1.0 10 10 10

63 Checksum for Bytes 0-62

(Standard/Low-profile) -262

-26A

-265

-202

BF/B0

EC/DD

1C/0D

B7/A8

E2/D3

0F/00

3F/30

DA/CB

23/14

50/41

80/71

1B/0C

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Par t Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code 1-9 01-09 01-09 01-09

92 Identification Code (Continued) 0000000

93 Year of Manufacture in BCD Variable Data Variable Data Variable Data

94 Week of Manufacture in BCD Variable Data Varia ble Data Variable Data

95-98 Modul e Serial Number Variable Data Variable Data Variable Data

99-127

Manufacturer-Specific Data (RSVD) –––

Table 25: Serial Presence-Detect Matrix – 256MB, 512MB, and 1GB (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 33

BYTE DESCRIPTION ENTRY (VERSION)

MT18VDDT3272D MT18VDDT6472D

MT18VDDT12872D

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

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Table 26: Serial Presence-Detect Matrix – 2GB

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 33

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT25672D

0Number of SPD Bytes Used by Micron 128 80

1Total Number of Bytes In SPD Device 256 08

2Fundame ntal Mem ory Type SDRAM DDR 07

3Number of Row Addresses on Assembly 14 0E

4Number of Column Addresses on Assembly 11 0B

5Number of Physical Ranks on DIMM 202

6Module Data Width 72 48

7Module Data Width (Continued) 000

Module Voltage Interface Levels

SSTL 2.5V 04

9SDRAM Cycle T ime, tC K (CAS L aten cy = 2.5) (S ee note 1) 7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

10 SDRAM Access from Clock, tAC (CAS Latency = 2.5) 0.75ns (-262/-26A/-265)

0.8ns (-202) 75

11 Module Configuration Type ECC 02

12 Refresh Rate/Type 7.8µs/SELF 82

13 SDRAM Device Width (Primary DDR SDRAM) 808

Error-c hecking DDR SDRAM Data Widt h

808

15 Minimum Clock Delay, Back-to-Back Random Column

Access 1 clock 01

16 Burst Lengths Supported 2, 4, 8 0E

17 Number of Banks on DDR SDRAM Device 404

18 CAS Latencies S upported 2, 2.5 0C

19 CS Latency 001

20 WE Latency 102

21 SDRAM Module Attributes Unbuffered/Diff. Clock 26

22 SDRAM Device Attributes: General Fast/Concurrent AP C0

23 SDRAM Cycle Time, tCK (CAS Late ncy = 2) 7.5ns (-262/-26A)

10ns (-265/-20 2) 75

24 SDRAM Access from CK, tAC (CAS Latency = 2)

0.75ns (-262/-26A/-265)

0.8ns (-202) 75

25 SDRAM Cycle Time, tCK (CAS Late ncy = 1.5) N/A 00

26 SDRAM Access from CK, tAC (CAS Latency = 1.5) N/A 00

27 Minimum Row Precharge Time, tRP 15ns (-262)

20ns (-26A/-265/-202) 3C

28 Minimum Row Active to Row Active, tRRD 15ns (-262/-26 A/-26 5/-2 02) 3C

29 Minimum RAS# to CAS# Delay, tRCD 15ns (-262)

20ns (-26A/-265/-202) 3C

30 Minimum RAS# Pulse Width, tRAS

(See note 2) 45ns (-262/-26A/-265)

40ns (-202) 2D

31 Module Rank Density 1GB 01

32 Addr ess A nd Comman d Setu p Time, tISs (See note 3) 1ns (262/-26A/-265)

1.1ns (-202) A0

33 Address And Command Hold Time, tIHs (See note 3) 1ns (-262/-26A/-265)

1.1ns (-202) A0

34 Data/ Data Mask Input Setup Time, tDS

0.50ns (-262/-26A/-265)

0.6ns (-202) 50

35 Data/ Data Mask Input Hold Time, tDH

0.50ns (-262/-26A/-265)

0.6ns (-202) 50

36-40 Reserved 00

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

NOTE:

1. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

41 Min Active Auto Refresh Time tRC 60ns (-262)

65ns (-26A/-265)

70ns (-202)

42 Minimum Auto Refresh to Active/ Auto Refresh

Command Period, tRFC 120ns 8

43 SDRAM Device Max Cycle Time tCKMAX 13n s (-262/-26 A/ -26 5/-2 02) 34

44 SDRAM Device Max DQS-DQ Skew Time tDQSQ 0.5ns (-262/-26A/-265)

0.6ns (-202) 32

45 SDRAM Device Max Read Data Hold Skew Factor tQHS 0.75n s (-2 62/-26A/-265)

1.0ns (-202) 75

46 Reserved 00

47 DIMM Height Standard/Low-Profile 10/01

48–61 Reserved 00

62 SPD Revision Release 1.0 10

63 Checksum for Bytes 0-62

(Standard/Low-profile) -262

-26A

-265

-202

D2/C3

FF/F0

2F/20

C5/B6

64 Manufacturer’s JEDEC ID Code MICRON 2C

65-71 Manufacturer’s JE DEC ID Code (Continued) FF

72 Manufacturing Location 01–12 01–0C

73-90 Module Part Number (ASCII) Variable Data

91 PCB Identification Code 1–9 01-09

92 Identification Code (Continued) 000

93 Year of Manufacture in BCD Variable Data

94 Week of Manufacture in BCD Variable Data

95-98 Module Serial Number Variable Data

99-127

Manufacturer-Specific Data (RSVD) –

Table 26: Serial Presence-Detect Matrix – 2GB (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 33

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT25672D

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Techn ology, Inc., reserves the right to ch ange products or spec ifica tio ns w ith out notice.

Figure 16: 184-Pin DIMM Dimensions (Standard)

NOTE:

All dimensions are in inches (millimeters); or typical where noted.

1.705 (43.31)

1.695 (43.05)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

0.054 (1.37)

0.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

0.394 (10.00)

TYP.

0.125 (3.175)

MAX

BACK VIEW

PIN 184 PIN 93

U1 U2 U3 U4 U5

U11 U12

U6 U7

U13

U8 U9

U10

U14 U15 U16 U17 U18 U19 U20 U21 U22

MAX

MIN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Interne t: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

256MB , 512MB, 1GB, 2GB (x72, ECC, PLL, DR)

184-PIN DDR SDRAM RDIMM

pdf: 09005aef80e1141d, source: 09005aef80e11353 Micron Tech no lo gy , Inc., reserv es the ri ght to chan ge pro duc ts or specifications without notice..

Figure 17: 184-Pin DIMM Dimensions (Low-Profile)

NOTE:

All dimensions are in inches (millimeters); or typical where noted.

Data Sheet Designation

Re l e a s e d ( N o Ma r k ) : Th is dat a s heet cont ains mini-

mum and max imum limit s speci fied o ver th e comple te

power supply and temperature range for production

devices. Although considered final, these specifica-

tions are subject to change, as further product devel-

opment and data characterization sometimes occur.

U1 U2 U3 U4

U11

U12

U5 U6 U7 U8 U9

U14 U15 U16 U17 U18

U13

U10

U19 U20 U21 U22

0.054 (1.37)

0.046 (1.17)

0.125 (3.175)

MAX

1.205 (30.61)

1.195 (30.35)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

0.394 (10.00)

TYP.

BACK VIEW

PIN 184 PIN 93

MAX

MIN