K4S283233E-FE75 - Samsung - Datasheet.Directory

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

GENERAL DESCRIPTIONFEATURES

1M x 32Bit x 4 Banks SDRAM in 90FBGA

FUNCTIONAL BLOCK DIAGRAM

• 3.0V & 3.3V power supply

• LVCMOS compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (1, 2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• EMRS cycle with address key programs.

-. PASR(Partial Array Self Refresh)

-. Internal TCSR(Temperature Compensated Self Refresh)

• All inputs are sampled at the positive going edge of the system

clock

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle).

• Extended Temperature Operation (-25°C ~ 85°C).

• Commercial Temperature Operation (-25°C ~ 70°C).

• 90Balls Monolithic FBGA(9mm x 13mm)

• Pb for -FXXX, Pb Free for -HXXX.

Bank Select

Data Input Register

1M x 32

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row DecoderCol. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS RAS CAS WE DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

1M x 32

Timing Register

* Samsung Electronics reserves the right to change products or specification without notice.

The K4S283233E is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 1,048,576 words by 32

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock and I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst lengths and programmable latencies allow the

same device to be useful for a variety of high bandwidth and

high performance memory system applications.

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S283233E-F(H)E/N/G/C/L/F60 166MHz(CL=3)

LVCMOS 90FBGA

(Pb Free)

K4S283233E-F(H)E/N/G/C/L/F75 133MHz(CL=3)

105MHz(CL=2)

K4S283233E-F(H)E/N/G/C/L/F1H 105MHz(CL=2)

K4S283233E-F(H)E/N/G/C/L/F1L 105MHz(CL=3)*1

- F(H)E/N/G : Normal/Low Power, Extended Temp.

- F(H)C/L/F : Normal/Low Power, Commercial Temp.

1. In case of 40MHz Frequency, CL1 can be supported.

Note :

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

90Ball(6x15) CSP

123789

ADQ26 DQ24 VSS VDD DQ23 DQ21

BDQ28 VDDQ VSSQ VDDQ VSSQ DQ19

CVSSQ DQ27 DQ25 DQ22 DQ20 VDDQ

DVSSQ DQ29 DQ30 DQ17 DQ18 VDDQ

E VDDQ DQ31 NC NC DQ16 VSSQ

FVSS DQM3 A3 A2 DQM2 VDD

GA4 A5 A6 A10 A0 A1

HA7 A8 NC NC BA1 A11

JCLK CKE A9 BA0 CS RAS

KDQM1 NC NC CAS WE DQM0

LVDDQ DQ8 VSS VDD DQ7 VSSQ

MVSSQ DQ10 DQ9 DQ6 DQ5 VDDQ

NVSSQ DQ12 DQ14 DQ1 DQ3 VDDQ

PDQ11 VDDQ VSSQ VDDQ VSSQ DQ4

RDQ13 DQ15 VSS VDD DQ0 DQ2

Pin Name Pin Function

CLK System Clock

CS Chip Select

CKE Clock Enable

A0 ~ A11 Address

BA0 ~ BA1Bank Select Address

RAS Row Address Strobe

CAS Column Address Strobe

WE Write Enable

DQM0 ~ DQM3Data Input/Output Mask

DQ0 ~ 31 Data Input/Output

VDD/VSS Power Supply/Ground

VDDQ/VSSQ Data Output Power/Ground

Package Dimension and Pin Configuration

< Bottom View*1 >

< Top View*2 >

*2: Top View

5 2 16 3489 7

D/2

EE/2

Substrate(2Layer)

#A1 Ball Origin Indicator

*1: Bottom View

K4S283233E-XXXX

SAMSUNG Week

Symbol Min Typ Max

A1.00 1.10 1.20

A10.27 0.32 0.37

E-9.00 -

E1-6.40 -

D-13.00 -

D1-11.20 -

e-0.80 -

b0.40 0.45 0.50

z- - 0.10

[Unit:mm]

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Notes :

1. VIH (max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.

4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD 2.7 3.0 3.6 V

VDDQ 2.7 3.0 3.6 V

Input logic high voltage VIH 2.2 3.0 VDDQ+0.3 V1

Input logic low voltage VIL -0.3 00.5 V2

Output logic high voltage VOH 2.4 - - VIOH = -2mA

Output logic low voltage VOL - - 0.4 VIOL = 2mA

Input leakage current ILI -10 -10 uA 3

ABSOLUTE MAXIMUM RATINGS

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1W

Short circuit current IOS 50 mA

CAPACITANCE (VDD = 3.0V & 3.3, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Pin Symbol Min Max Unit Note

Clock CCLK -4.0 pF

RAS, CAS, WE, CS, CKE, DQM0~ DQM3CIN -4.0 pF

Address(A0 ~ A11, BA0 ~ BA1)CADD -4.0 pF

DQ0 ~ DQ31 COUT -6.0 pF

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter Symbol Test Condition Version Unit Note

-60 -75 -1H -1L

Operating Current

(One Bank Active) ICC1 Burst length = 1

tRC ≥ tRC(min)

IO = 0 mA 100 85 85 80 mA 1

Precharge Standby Current

in power-down mode ICC2PCKE ≤ VIL (max), tCC = 10ns 0.5 mA

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞0.5

Precharge Standby Current

in non power-down mode

ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 16

ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 8

Active Standby Current

in power-down mode ICC3PCKE ≤ VIL (max), tCC = 10ns 5mA

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞5

Active Standby Current

in non power-down mode

(One Bank Active)

ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns 26 mA

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 22 mA

Operating Current

(Burst Mode) ICC4

IO = 0 mA

Page burst

4Banks Activated

tCCD = 2CLKs

110 85 80 80 mA 1

Refresh Current ICC5 tRC ≥ tRC(min) 180 160 150 130 mA 2

Self Refresh Current ICC6 CKE ≤ 0.2V

-F(H)E/C 1500 uA 4

-F(H)N/L 800 5

Internal TCSR Max 40 Max 85/70 °C3

-F(H)G/F

4 Banks 500 800

uA 6

2 Banks 460 650

1 Bank 440 550

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Internal TCSR can be supported.

In Commercial Temp : Max 40°C/Max 70°C, In Extended Temp : Max 40°C/Max 85°C

4. K4S283233E-F(H)E/C** (85/70°C, Full Banks)

5. K4S283233E-F(H)N/L** (85/70°C, Full Banks)

6. K4S283233E-F(H)G/F**

7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)

Notes :

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

OPERATING AC PARAMETER

AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4 / 0.4 V

Input timing measurement reference level 0.5 x VDDQ V

Input rise and fall time tr/tf = 1/1 ns

Output timing measurement reference level 0.5 x VDDQ V

Output load condition See Fig. 2

VDDQ

1200Ω

870Ω

Output

30pF

VOH (DC) =2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Vtt = 0.5 x VDDQ

50Ω

Output

30pF

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum 2RDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and

precharge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Notes :

(AC operating conditions unless otherwise noted)

Parameter Symbol Version Unit Note

- 60 - 75 -1H -1L

Row active to row active delay tRRD(min) 12 15 19 19 ns 1

RAS to CAS delay tRCD(min) 18 19 19 24 ns 1

Row precharge time tRP(min) 18 19 19 24 ns 1

Row active time tRAS(min) 42 45 50 60 ns 1

tRAS (max) 100 us

Row cycle time tRC(min) 60 64 69 84 ns 1

Last data in to row precharge tRDL(min) 2CLK 2,3

Last data in to Active delay tDAL (min) tRDL + tRP -3

Last data in to new col. address delay tCDL(min) 1CLK 2

Last data in to burst stop tBDL(min) 1CLK 2

Col. address to col. address delay tCCD(min) 1CLK 4

Number of valid output data

CAS latency=3 2

ea 5

CAS latency=2 -1

CAS latency=1 -0

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol - 60 - 75 -1H -1L Unit Note

Min Max Min Max Min Max Min Max

CLK cycle time

CAS latency=3

tCC

6.0

1000

7.5

1000

9.5

1000

9.5

1000 ns 1

CAS latency=2 -9.5 9.5 12

CAS latency=1 ---25

CLK to valid output

delay

CAS latency=3

tSAC

5.4 677

ns 1,2

CAS latency=2 -778

CAS latency=1 ---20

Output data hold time

CAS latency=3

tOH

2.5 2.5 2.5 2.5

ns 2

CAS latency=2 -2.5 2.5 2.5

CAS latency=1 ---2.5

CLK high pulse width tCH 2.5 2.5 3 3 ns 3

CLK low pulse width tCL 2.5 2.5 3 3 ns 3

Input setup time tSS 2.0 2.0 2.5 2.5 ns 3

Input hold time tSH 1.0 1.0 1.5 1.5 ns 3

CLK to output in Low-Z tSLZ 1111ns 2

CLK to output in Hi-Z

CAS latency=3

tSHZ

5.4 677

CAS latency=2 -778

CAS latency=1 ---20

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,

A9 ~ A 0Note

Refresh

Auto Refresh HHL L L HXX3

Self

Refresh

Entry L 3

Exit LHLHHHXX3

HX X X 3

Bank Active & Row Addr. HXL L HHX V Row Address

Read &

Column Address Auto Precharge Disable HXLHLHX V LColumn

Address

(A0~A7)

Auto Precharge Enable H4, 5

Write &

Column Address Auto Precharge Disable HXLHL L X V LColumn

Address

(A0~A7)

Auto Precharge Enable H4, 5

Burst Stop HXLHHLXX6

Precharge Bank Selection HXL L HLXVLX

All Banks XH

Clock Suspend or

Active Power Down Entry HLHX X X XXLV V V

Exit LHX X X X X

Precharge Power Down Mode

Entry HLHX X X X

LH H H

Exit LHHX X X X

LV V V

DQM HX VX7

No Operation Command HXHX X X X X

LH H H

Notes :

1. OP Code : Operand Code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency

is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

A. MODE REGISTER FIELD TABLE TO PROGRAM MODES

Address BA1 BA0 A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function Mode Select RFU*1 PASR

Normal MRS Mode

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0Sequential 0 0 0 1 1

0 1 Reserved 0 0 1 11Interleave 0 0 1 2 2

1 0 Reserved 0 1 0 2Mode Select 0 1 0 4 4

1 1 Reserved 0 1 1 3BA1 BA0 Mode 0 1 1 8 8

Write Burst Length 1 0 0 Reserved

0 0 Setting for

Normal

MRS

1 0 0 Reserved Reserved

A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved

Address BA0 ~ BA1 A11 ~ A10/AP A9*2 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function "0" Setting for

Normal MRS RFU*1 W.B.L Test Mode CAS Latency BT Burst Length

* Full Page Length

64Mb : x16(256) / x32(256), 128Mb : x16(512) / x32(256), 256Mb : x16(512) / x32(512), 512Mb : x16(1024) / x32(512)

Extended MRS for PASR(Partial Array Self Refresh)

Notes : 1. RFU(Reserved for future use) should stay "0" during MRS cycle.

2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

3. In case of 1 Bank Partial Refresh, one bank(BA1=BA0=0) is selected.

In case of 2 Banks Partial Refresh, two banks(BA1=0) are selected.

Mode Select PASR *3

BA1 BA0 Mode A2 A1 A0 # of Banks

0 0 Normal MRS 0 0 0 4 Banks(All Banks)

0 1 Reserved 0 0 1 2 Banks(1/2 of All Banks)

1 0 EMRS for Mobile SDRAM 0 1 0 1 Bank(1/4 of All Banks)

1 1 Reserved 0 1 1 Reserved

Reserved Address*1 1 0 0 Reserved

A11~A10/AP A9 A8 A7 A6 A5 A4 A3 1 0 1 Reserved

0 0 0 0 0 0 0 0 1 1 0 Reserved

1 1 1 Reserved

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

Partial Array Self Refresh

1. In order to save power consumption, Mobile SDRAM has PASR option.

2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode ; 4 Banks(128Mb), 2 Banks(64Mb), 1 Bank(32Mb).

- 4 Banks - 2 Banks - 1 Bank

Partial Self Refresh Area

Temperature Compensated Self Refresh

1. In order to save power consumption, Mobile SDRAM has includes the Internal temperature sensor and control units to

control the self refresh cycle automatically according to the two temperature range : Max 40°C and Max 85°C(for Extended),

Max 70°C(for Commercial).

2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.

Temperature Range

Self Refresh Current (Icc 6)

Unit

-G/F

4 Banks 2 Banks 1 Bank

Max 85/70

C800 650 550 uA

Max 40

C500 460 440

BA1=0 BA1=0

BA1=1 BA1=1

BA0=0 BA0=1

BA1=0 BA1=0

BA1=1 BA1=1

BA0=0 BA0=1

BA1=0 BA1=0

BA1=1 BA1=1

BA0=0 BA0=1

1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.

- Apply VDD before or at the same time as VDDQ.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

6. Issue an extended mode register set command to define PASR operating type of the device after normal MRS.

EMRS cycle is not mandatory and EMRS command needs to be issued only when PASR is used.

The default state without EMRS command issued is all 4banks refreshed.

The device is now ready for the operation selected by EMRS.

For operating with PASR, set PASR mode in EMRS setting stage.

In order to adjust another mode in the state of PASR mode, additional EMRS set is required but power up sequence is

not needed again at this time, In that case, all banks have to be in idle state prior to adjusting EMRS set.

B. Power Up Sequence

K4S283233E-F(H)E/N/G/C/L/F

May. 2003

Mobile-SDRAM

C. BURST SEQUENCE

1. BURST LENGTH = 4

Initial Address Sequential Interleave

A1A0

0 0 0 1 2 3 0 1 2 3

0 1 1 2 3 0 1 0 3 2

1 0 2 3 0 1 2 3 0 1

1 1 3 0 1 2 3 2 1 0

2. BURST LENGTH = 8

Initial Address Sequential Interleave

A2A1A0

0000123456701234567

0011234567010325476

0102345670123016745

0113456701232107654

1004567012345670123

1015670123454761032

1106701234567452301

1117012345676543210