DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
1.2-A HIGH-EFFICIENCY PWM POWER DRIVER
1
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FEATURES
D1.22-A DC (82% Duty Cycle) Output Current
(TJ ≤ 89°C)
D1-A DC (100% Duty Cycle) Output Current
(TJ ≤ 89°C)
DLow Supply Voltage Operation from 2.7 V
to 5.5 V
DHigh Efficiency Generates Less Heat
DOver-Temperature Protection
DShort-Circuit Protection
DPowerPADt SOIC and 4 × 4 mm MicroStar
Junior Packages
APPLICATIONS
DThermoelectric Cooler (TEC) Driver
DLaser Diode Biasing
DESCRIPTION
The DRV590 is a high-efficiency power amplifier ideal
for driving a wide variety of thermoelectric cooler
elements in systems powered from 2.7 V to 5.5 V . PWM
operation and low output stage on-resistance
significantly decrease power dissipation in the amplifier.
The DRV590 is internally protected against over
temperature conditions and current overloads due to
short circuits. The over temperature protection
activates at a junction temperature of 190°C and will
deactivate once the temperature is less than 130°C. If
the overcurrent circuitry is tripped, the amplifier will
automatically reset after 3–5 ms.
The gain of the DRV590 is controlled by two input
terminals, GAIN1 and GAIN0. The amplifier may be
configured for a gain of 6, 12, 18, and 23.5 dB.
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
OUT+
NC
PGND
NC
AREF
AGND
COSC
ROSC
OUT–
NC
PGND
C6 C7
C5
L1 L2
C1 C2
C9
220 pF
R6
C4
R5 C3
R4
J2 J3
R3
J1 R2
R1
J6
OUT–
J7
OUT+
J9
GND
J8
VDD
J4
IN+
J5
IN– (VCOM)
C8
120 kΩ
120 kΩ
1 kΩ
1 kΩ
120 kΩ1 µF
10 µF
10 µH10 µF10 µH
10 µF
1 µF1 µF10 µF
120 kΩ
1 µF
PVDD
VDD
PVDD
J8
VDD
Typical Circuit Schematic for Driving a Thermoelectric Cooler Element
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
PowerPAD and MicroStar Junior are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
2www.ti.com
AVAILABLE OPTIONS
T
PACKAGED DEVICES
TASOIC (DWP)†GQC‡
–40°C to 85°C DRV590DWP DRV590GQCR
†The PW package is available taped and reeled. To order a taped and
reeled part, add the suf fix R to the part number (e.g., DRV590PWR).
‡The GQC package is only available taped and reeled.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
PVDD
OUT+
NC
PGND
NC
AREF
AGND
COSC
ROSC
VDD
PVDD
OUT–
NC
PGND
DWP PACKAGE
(TOP VIEW)
NC – No internal connection
MicroStar Juniort (GQC) Package
(TOP VIEW)
AGND
PVDD
IN–
IN+
NOTE: The shaded terminals are used for thermal connections
to the ground plane.
AREF
COSC
OUT–
PGND
NC
ROSC
VDD
PVDD
PVDD
SHUTDOWN
GAIN0
GAIN1
PVDD
OUT+
(SIDE VIEW)
NC – No internal connection
A1
B1
C1
D1
E1
F1
G1
A7
B7
C7
D7
E7
F7
G7
A2 A6
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME GQC NO. DWP NO. I/O DESCRIPTION
AGND A3–A5, B2–B6
C2–C6, D2–D4 18 I Analog ground
AREF A6 19 O Connect capacitor to ground for AREF voltage filtering (1 µF).
COSC B7 17 I Connect capacitor to ground to set oscillation frequency (220 pF).
GAIN0 C1 5 I Bit 0 of gain control (TTL logic level)
GAIN1 D1 6 I Bit 1 of gain control (TTL logic level)
IN–A1 3 I Negative differential input
IN+ A2 2 I Positive differential input
NC A7 1, 9, 12, 20 Not connected
OUT–G7 13 O Negative BTL output
OUT+ G1 8 O Positive BTL output
PGND D5–D6, E2–E6
F2–F6, G2–G6 10, 11 IHigh-current grounds (2)
PVDD E1, E7, F1, F7 7, 14 IHigh-current power supplies (2)
ROSC C7 16 I Connect resistor to ground to set oscillation frequency (120 kΩ).
SHUTDOWN B1 4 I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminal,
and normal operation if a TTL logic high is placed on this terminal.
VDD D7 15 I Analog power supply
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
3
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VDD, PVDD –0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°CDERATING FACTOR TA = 70°C TA = 85°C
GQC 2.61 W 20.9 mW/°C1.67 W 1.36 W
DWP 3.66 W 29.3 mW/°C2.34 W 1.9 W
recommended operating conditions
MIN MAX UNIT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Supply voltage, VDD, PVDD
ÁÁÁ
2.7
ÁÁÁ
5.5
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
High-level input voltage, VIH
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
GAIN0, GAIN1, SHUTDOWN
ÁÁÁ
ÁÁÁ
2
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low-level input voltage, VIL
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
GAIN0, GAIN1, SHUTDOWN
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
0.7
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Operating free-air temperature, TA
ÁÁÁ
ÁÁÁ
–40
ÁÁÁ
ÁÁÁ
85
ÁÁÁ
ÁÁÁ
°C
Load impedance 1Ω
electrical characteristics at specified free-air temperature, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Á
|VOS|
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Output offset voltage (measured
differentially)
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
VI = 0 V, AV = any gain
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
ÁÁÁ
Á
Á
Á
ÁÁÁ
25
ÁÁÁ
Á
Á
Á
ÁÁÁ
mV
PSRR
ÁÁÁÁÁÁÁÁÁ
Power supply rejection ratio
ÁÁÁÁÁÁÁÁÁÁÁ
PVDD = 4.9 V to 5.1 V
ÁÁÁ
ÁÁÁ
77
ÁÁÁ
ÁÁÁ
dB
PSRR
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Power supply rejection ratio
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
PVDD = 3.2 V to 3.4 V
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
61
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
dB
|IIH|
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
High-level input current
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
VI = 3.3 V
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
µA
|IIL|
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Low-level input current
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
VI = 0 V
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
µA
IDD
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Supply current, no filter
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
4.5
ÁÁÁ
ÁÁÁ
6.5
ÁÁÁ
ÁÁÁ
mA
IDD(SD)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Supply current, shutdown mode
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
GAIN0, GAIN1, SHUTDOWN = 0 V
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
0.05
ÁÁÁ
ÁÁÁ
5
ÁÁÁ
ÁÁÁ
µA
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
GAIN0 = low, GAIN1 = low
ÁÁÁ
ÁÁÁ
5.1
ÁÁÁ
ÁÁÁ
6
ÁÁÁ
ÁÁÁ
6.5
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Gain
GAIN0 = high, GAIN1 = low
ÁÁÁ
ÁÁÁ
11
ÁÁÁ
ÁÁÁ
12
ÁÁÁ
ÁÁÁ
12.5
ÁÁÁ
ÁÁÁ
dB
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Gain GAIN0 = low, GAIN1 = high
ÁÁÁ
ÁÁÁ
17
ÁÁÁ
ÁÁÁ
18
ÁÁÁ
ÁÁÁ
19
ÁÁÁ
ÁÁÁ
dB
ÁÁÁÁÁÁÁÁÁ
GAIN0 = high, GAIN1 = high
ÁÁÁ
23
ÁÁÁ
23.5
ÁÁÁ
24
ÁÁÁ
f
Switching frequency
Single ended
R 120 kΩC 220 pF
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
250
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
kHz
fsSwitching frequency Differential Rosc = 120 kΩ, Cosc = 220 pF
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
500
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
kHz
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
4www.ti.com
operating characteristics, TA = 25°C, RL = 2 Ω, gain = 6 dB (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ÁÁÁÁ
ÁÁÁÁ
IO
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Maximum output current
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Duty cycle = 82%
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
1.22
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
A
ÁÁÁÁ
ÁÁÁÁ
PSRR
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Power supply rejection ratio
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
f = 1 kHz,
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
C(AREF) = 1 µF
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
70
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
dB
ÁÁÁÁ
ÁÁÁÁ
ZI
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Input impedance
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁ
>15
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
kΩ
V
Common mode input voltage range
PVDD = 5 V 1.2 3.8
V
VICR Common-mode input voltage range PVDD = 3.3 V 1.2 2.1 V
r
Output on resistance
PVDD = 5 V 0.5
Ω
rds(on) Output on-resistance PVDD = 3.3 V 0.65 Ω
η
Efficiency
PVDD = 5 V 64%
ηEfficiency PVDD = 3.3 V 60%
VnIntegrated noise floor f = 10 Hz to 5 kHz, Gain = 6 dB 23 µV rms
functional block diagram
Gate
Drive
_
+
Gate
Drive
_
+
_
+_
+
Gain
Adjust
Gain
Adjust
Start-Up
Protection
Logic
OC
Detect
Thermal VDD ok
Ramp
Generator
Biases
and
References
Gain 2
AGNDVDD
VDD
PVDD
IN–OUT–
PGND
PVDD
OUT+
PGND
IN+
SHUTDOWN
GAIN1
GAIN0
COSC
ROSC
AREF
SD
_
+
_
+
Deglitch
Logic
Deglitch
Logic
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
5
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Gain and phase vs Frequency 1
Efficiency vs Load resistance 2, 3
PSRR Power supply rejection ratio vs Frequency 4
r
Small signal drain source on state resistance
vs Supply voltage 5, 6
rds(on) Small-signal drain-source on-state resistance vs Ambient temperature 7, 8
IOMaximum output current vs Differential output voltage 9
–180
–152
–124
–96
–68
–40
–12
16
44
72
100
f – Frequency – Hz
–10
–8
–6
–4
–2
0
2
4
6
8
10
VI = 1.17 Vrms
VDD = 5 V
RL = 2 Ω
GAIN AND PHASE
vs
FREQUENCY
Phase
Gain
Gain – dBV
Phase – °
10 100 1k 100k10k
Figure 1
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
6www.ti.com
TYPICAL CHARACTERISTICS
Figure 2
RL – Load Resistance – Ω
50
55
60
65
70
75
80
85
90
2345678910
VDD = 3.3 V
Efficiency – %
EFFICIENCY
vs
LOAD RESISTANCE
PO = 0.25 W
PO = 0.5 W
Figure 3
RL – Load Resistance – Ω
60
65
70
75
80
85
90
2345678910
VDD = 5 V
Efficiency – %
EFFICIENCY
vs
LOAD RESISTANCE
PO = 1 W
PO = 0.5 W
PO = 2 W
Figure 4
f – Frequency – Hz
–80
–75
–70
–65
–60
–55
–50
–45
–40
PSRR – Power Supply Rejection Ratio – dB
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
1 10 10k100 1k
Figure 5
VDD – Supply Voltage – V
0.3
0.4
0.5
0.6
0.7
0.8
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
IO = 0.5 A
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
rds(on) Low Side
rds(on) High Side
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
7
www.ti.com
TYPICAL CHARACTERISTICS
Figure 6
VDD – Supply Voltage – V
0.3
0.4
0.5
0.6
0.7
0.8
0.9
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
IO = 1 A
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
rds(on) Low Side
rds(on) High Side
Figure 7
TA – Ambient Temperature – °C
0.38
0.42
0.46
0.50
0.54
0.58
0.62
25 35 45 55 65 75 85
IO = 0.5 A
VDD = 5 V
DWP Package
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
AMBIENT TEMPERATURE
rds(on) Low Side
rds(on) High Side
TA – Ambient Temperature – °C
0.38
0.42
0.46
0.50
0.54
0.58
0.62
25 35 45 55 65 75 85
IO = 1 A
VDD = 3.3 V
DWP Package
rds(on) – Small-Signal Drain-Source On-State Resistance – Ω
SMALL-SIGNAL DRAIN-SOURCE
ON-STATE RESISTANCE
vs
AMBIENT TEMPERATURE
rds(on) Low Side
rds(on) High Side
Figure 8
VOD – Differential Output Voltage – V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD = 5 V
IO – Maximum Output Current – A
MAXIMUM OUTPUT CURRENT
vs
DIFFERENTIAL OUTPUT VOLTAGE
TJ = 89°C
TJ = 102°C
TJ = 124°C
Figure 9
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
8www.ti.com
APPLICATION INFORMATION
driving TEC elements
Below is a typical application schematic.
NC
IN+
IN–
SHUTDOWN
GAIN0
GAIN1
OUT+
NC
PGND
NC
AREF
AGND
COSC
ROSC
OUT–
NC
PGND
C6 C7
C5
L1 L2
C1 C2
C9
220 pF
R6
C4
R5 C3
R4
J2 J3
R3
J1 R2
R1
J6
OUT–
J7
OUT+
J9
GND
J8
VDD
J4
IN+
J5
IN– (VCOM)
C8
120 kΩ
120 kΩ
1 kΩ
1 kΩ
120 kΩ1 µF
10 µF
10 µH10 µF10 µH
10 µF
1 µF1 µF10 µF
120 kΩ
1 µF
PVDD
VDD
PVDD
J8
VDD
output filter considerations
TEC element manufacturers provide electrical specifications for maximum dc current and maximum output
voltage for each particular element. The maximum ripple current, however, is typically only recommended to
be less than 10%. The maximum temperature differential across the element decreases as ripple current
increases and can be calculated using equation 1.
DT+1
(1)N2) DTmax
∆T = actual temperature differential
∆Tmax = maximum temperature differential (specified by manufacturer)
N = ratio of ripple current to dc current
According to this relationship, a 10% ripple current reduces the maximum temperature differential by 1%. A LC
network may be used to filter the current flowing to the TEC to reduce the amount of ripple and, more importantly,
protect the rest of the system from any electromagnetic interference (EMI).
(1)
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
9
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APPLICATION INFORMATION
driving TEC elements (continued)
filter component selection
The LC filter may be designed from a couple of different perspectives, both of which may help estimate the
overall performance of the system. The filter should be designed for the worst-case conditions during operation,
which is typically when the differential output is at 50% duty cycle. The following section serves as a starting
point for the design, and any calculations should be confirmed with a prototype circuit.
To simplify the design, half-circuit analysis may also be used. This should only be done if the TEC element is
close to the output of the filter . Any filter should always be placed as close to the DRV590 as possible to reduce
EMI.
TEC
C
C
CR
L
L
OUT+
OUT–
Figure 10. LC Output Filter
TEC
C2C R
L
OUT+
or
OUT–
Figure 11. LC Half-Circuit Equivalent
2
LC filter in the frequency domain
The transfer function for the second order low-pass filter in Figure 10 and Figure 11 is shown in equation 2.
HLP(jw)+1
–ǒw
w0Ǔ2
)1
Qjw
w0)1
w0+1
L 3C
Ǹ
Q = quality factor
ω = DRV590 differential switching frequency
For the DRV590, the differential output switching frequency is 500 kHz. The resonant frequency for the filter
should be chosen to be at least one order of magnitude lower than the switching frequency. Equation 2 may
then be simplified to give the following magnitude equation 3. These equations assume the use of the filter in
Figure 10, which effectively triples the capacitance.
ŤHLPŤdB +–40 logǒfs
foǓ
fo+1
2pL 3C
Ǹ
fs = 500 kHz (DRV590 differential switching frequency)
(2)
(3)
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
10 www.ti.com
APPLICATION INFORMATION
LC filter in the frequency domain (continued)
If L = 10 µH and C = 10 µF, the resonant frequency is 9.2 kHz, which corresponds to –69 dB of attenuation at
the 500-kHz switching frequency. For VDD = 5 V, the amount of ripple voltage at the TEC element will be
approximately 1.7 mV.
The average TEC element has a resistance of 1.5 Ω, so the ripple current through the TEC is approximately
1.13 mA. At the 1-A maximum output current of the DRV590, this 1.13 mA corresponds to 0.1 13% ripple current,
causing less than 0.0001% reduction of the maximum temperature differential of the TEC element (see
equation 1).
LC filter in the time domain
The ripple current of an inductor can be calculated using equation 4.
DIL+ǒVDD *VTECǓDTs
L
D = duty cycle (0.5 worst case)
Ts = 1/fs = 1/500 kHz
For VDD = 5 V, VTEC = 2.5 V, and L = 10 µH, the inductor ripple current is 250 mA. To calculate how much of
that ripple current will flow through the TEC element, however, the properties of the filter capacitor must be
considered.
For relatively small capacitors (less than 10 µF) with very low equivalent series resistance (ESR, less than
10 mΩ), such as ceramic capacitors, equation 5 may be used to estimate the ripple voltage on the capacitor
due to the change in charge.
DVC+p2
2(1–D)ǒfo
fsǓ2VTEC
fo+1
2pL 3C
Ǹ
D = duty cycle
fs = 500 kHz
For L = 10 µH and C = 10 µF, the cutoff frequency fo = 9.2 kHz. For a worst case duty cycle of 0.5 and VTEC
= 2.5, the ripple voltage on the capacitors is 2 mV. The ripple current may be simply calculated by dividing the
ripple voltage by the TEC resistance of 1.5 Ω, resulting in a ripple current through the TEC element of 1.33 mA.
Note that this is similar to the value calculated using the frequency domain approach.
For larger capacitors (greater than 10 µF) with relatively high ESR (greater than 100 mΩ), such as electrolytic
capacitors, the ESR drop dominates over the charging-discharging of the capacitor. Equation 6 can be used
to estimate the ripple voltage.
DVC+DIL RESR
∆L = inductor ripple current
RESR = filter capacitor ESR
For a 100-µF electrolytic capacitor, an ESR of 0.1 Ω is common. If the 10-µH inductor is used, delivering 250 mA
of ripple current to the capacitor (as calculated above), then the ripple voltage is 25 mV. This is over ten times
that of the 10-µF ceramic capacitor, as ceramic capacitors typically have negligible ESR.
(4)
(5)
(6)
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
11
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APPLICATION INFORMATION
LC filter in the time domain (continued)
For worst case conditions, the on-resistance of the output transistors has been ignored to give the maximum
theoretical ripple current. In reality, the voltage drop across the output transistors will decrease the maximum
VO as the output current increases. It can be shown using equation 4 that this will decrease the inductor ripple
current, and therefore the TEC ripple current.
general operation
oscillator components ROSC and COSC
The onboard ramp generator requires an external resistor and capacitor to set the oscillation frequency. For
proper operation, the resistor ROSC should be 120 kΩ with 1% tolerance. The capacitor COSC should be a
ceramic 220 pF with 10% tolerance. Both components should be grounded to AGND, which should be
connected to PGND at a single point, typically where the power and ground physically connect to the printed
circuit board.
AREF capacitor
The AREF terminal is the output of an internal mid-rail voltage regulator used for the on-board oscillator and
ramp generator. The regulator may not be used to provide power to any additional circuitry. A 1-µF ceramic
capacitor must be connected from AREF to AGND for stability (see the oscillator components ROSC and C OSC
section for AGND connection information).
gain settings
The differential output voltage may be calculated using equation 7.
VO+VOUT)–VOUT–+AvǒVIN)–VIN–Ǔ
Av is the voltage gain, which may be selected by configuring GAIN0 and GAIN1 according to the table below.
The input resistance also varies with the gain setting, as shown by the typical values in Table 1. Though these
values may vary by up to 30% due to process variations, the gain settings themselves vary little, as they are
determined by resistor ratios.
Table 1. Gain Settings
GAIN0 GAIN1 AMPLIFIER GAIN
(dB, TYPICAL) INPUT RESISTANCE
(kΩ, TYPICAL)
0 0 6 104
0 1 12 74
1 0 18 44
1 1 23.5 24
(7)
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
12 www.ti.com
APPLICATION INFORMATION
general operation (continued)
input configuration—differential and single-ended
If a differential input is used, it should be biased around the mid-rail of the DRV590 and must not exceed the
common-mode input range of the input stage (see the operating characteristics at the beginning of the data
sheet).
The most common configuration employs a single-ended input. The unused input should be tied to the mid-rail,
which may be simply accomplished with a resistive voltage divider. For the best performance, the resistor values
chosen should be at least an order of magnitude lower than the input resistance of the DRV590 at the selected
gain setting. This prevents the bias voltage at the unused input from shifting when the signal input is applied.
A small ceramic capacitor should also be placed from the input to ground to filter noise and keep the voltage
stable.
power supply decoupling
To reduce the effects of high-frequency transients or spikes, a small ceramic capacitor , typically 0.1 µF to 1 µF,
should be placed as close to each PVDD pin of the DRV590 as possible. For bulk decoupling, a 10-µF to 100-µF
tantalum or aluminum electrolytic capacitor should be placed relatively close to the DRV590.
SHUTDOWN operation
The DRV590 includes a shutdown mode that disables the outputs and places the device in a low supply current
state. The SHUTDOWN pin may be controlled with a TTL logic signal. When SHUTDOWN is held high, the
device operates normally . When SHUTDOWN is held low , the device is placed in shutdown. The SHUTDOWN
pin must not be left floating. If the shutdown feature is unused, the pin may simply be connected to VDD.
power dissipation and maximum ambient temperature
Though the DRV590 is much more efficient than traditional linear solutions, the IR drop across the on-resistance
of the output transistors generates some heat in the package, which may be calculated using equation 8.
PDISS +ǒIOUTǓ2
rds(on), total
For example, at the maximum output current of 1.2 A through a total on-resistance of 1 Ω, the power dissipated
in the package is 1.44 W.
The maximum ambient temperature can be calculated using equation 9.
TA+TJǒqJA PDISSǓ
Continuing the example above, the maximum ambient temperature driving 1.2 A without exceeding 89°C
junction temperature for a DRV590 in the DWP package (see the maximum output current vs duty cycle section)
is 39°C.
maximum output current vs duty cycle
At 100% duty cycle across the load, the reliability of the DRV590 is degraded if more than 1 A is driven through
the outputs. Furthermore, the junction temperature must not exceed 89°C at the maximum output current levels
to prevent further degradation. However , as the duty cycle across the load decreases, the maximum allowable
output current increases.
Table 2 shows the typical maximum output current, voltage across the load, and junction temperature versus
duty cycle. The dissipation and junction temperatures were calculated using equations 8 and 9. The total
on-resistance was assumed to be 1 Ω, the ambient temperature to be 25°C, and the θJA to be 34.1°C/W.
(8)
(9)
DRV590
SLOS365A – AUGUST 2001 – REVISED AUGUST 2002
13
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APPLICATION INFORMATION
maximum output current vs duty cycle (continued)
Table 2. Typical Maximum Output Specifications vs Duty Cycle (VDD = 5 V)
DUTY CYCLE MAX IO (A) MAX VLOAD (V) PDISS (W) TJ (°C)
100% 1 4 1 67.6
95% 1.05 3.69 1.11 72.2
90% 1.11 3.38 1.24 77.6
85% 1.17 3.07 1.39 83.9
84% 1.19 3.01 1.42 85.3
83% 1.2 2.94 1.45 86.8
82% 1.22 2.88 1.49 88.3
At duty cycles less than 82%, the power dissipated from the theoretical maximum current flowing through the
on-resistance causes the junction temperature to exceed 89°C. See Figure 9 for more details.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DRV590DWP ACTIVE SO PowerPAD DWP 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV590DWPG4 ACTIVE SO PowerPAD DWP 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DRV590GQCR OBSOLETE BGA
MICROSTAR
JUNIOR
GQC 48 TBD Call TI Call TI
DRV590ZQCR OBSOLETE BGA
MICROSTAR
JUNIOR
ZQC 48 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MPLG008D – APRIL 2000 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GQC (S-PBGA-N48) PLASTIC BALL GRID ARRAY
0,50
M
0,05
0,50
0,08
4200460/E 01/02
4,10
3,90
1,00 MAX
0,25
0,35
A
1
Seating Plane
3,00 TYP
B
C
D
E
F
2 3 4 5 6 7
G
0,77
SQ
0,25
0,15
A1 Corner Bottom View
3,00 TYP
0,71
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
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