5962-9206201MYC - CYPRESS SEMICONDUCTOR

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192-Macrocell MAX® EPLD

CY7C341B

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-03016 Rev. *C Revised April 22, 2004

Features

• 192 macrocells in 12 logic array blocks (LABs)

• Eight dedicate d in puts, 64 bidirectio na l I/O pins

• Advanced 0.65-micron CMOS technology to increase

performance

• Programmable interconnect array

• 384 expander product terms

• Available in 84-pin HLCC, PLCC, and PGA packages

Functional Description

The CY7C341B is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX® architecture is

100% user-configurable, allowing the devices to accom-

modate a variety of independent logic functions.

The 192 macrocells in the CY7C341B are divided into 12 Logic

Array Blocks (LABs), 16 per LAB. There are 384 expander

product terms, 32 per LAB, to be used and shared by the

macrocells within each LAB. Each LAB is interconnected with

a programmable interconn ect array, allowing all signa ls to be

routed throughout the chip.

The speed and density of the CY7C341B allows it to be used

in a wide range of applications, from replacement of large

amounts of 7400-series TTL logic, to complex controllers and

multifunction chips. With greater than 37 times the functionality

of 20-pin PLDs, the CY7C341B allows the replacement of over

75 TTL devices. By replacing large amounts of logic, the

CY7C341B reduces board space, part count, and increases

system reliability.

Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8

macrocells are connected to I/O pins and eight are buried,

while for LABs B, C, D, E, H, I, J, and K, four macrocells are

connected to I/O pins and 12 are buried. Moreover , in addition

to the I/O and buried macrocells, th ere are 32 single product

term logic expanders in each LAB. Their use greatly enhances

the capability of the macrocells without increasing the number

of product terms in each macrocell.

Selection Guide

7C341B-25 7C341B-35 Unit

Maximum Access T i me 25 35 ns

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Document #: 38-03016 Rev. *C Page 2 of 12

MACROCELL1

MACROCELL2

MACROCELL3

MACROCELL4

MACROCELL5

MACROCELL6

MACROCELL7

MACROCELL8

MACROCELL97

MACROCELL98

MACROCELL99

MACROCELL100

MACROCELL101

MACROCELL102

MACROCELL103

MACROCELL104

MACROCELL 9–16 MACROCELL 105–112

MACROCELL17

MACROCELL18

MACROCELL19

MACROCELL20

MACROCELL113

MACROCELL114

MACROCELL115

MACROCELL116

MACROCELL 21–32 MACROCELL 117–128

MACROCELL33

MACROCELL34

MACROCELL35

MACROCELL36

MACROCELL129

MACROCELL130

MACROCELL131

MACROCELL132

MACROCELL 37–48 MACROCELL 133–144

MACROCELL49

MACROCELL50

MACROCELL51

MACROCELL52

MACROCELL145

MACROCELL146

MACROCELL147

MACROCELL148

MACROCELL 53–64 MACROCELL 149–160

MACROCELL65

MACROCELL66

MACROCELL67

MACROCELL68

MACROCELL161

MACROCELL162

MACROCELL163

MACROCELL164

MACROCELL 69–80 MACROCELL 165–176

MACROCELL81

MACROCELL82

MACROCELL83

MACROCELL84

MACROCELL85

MACROCELL86

MACROCELL87

MACROCELL88

MACROCELL177

MACROCELL178

MACROCELL179

MACROCELL180

MACROCELL181

MACROCELL182

MACROCELL183

MACROCELL184

MACROCELL 89–96 MACROCELL 185–192

INPUT (C6) 84

INPUT (C7) 83

INPUT (L7) 44

INPUT (J7) 43

1 (A6) INPUT/CLK

2 (A5) INPUT

41 (K6) INPUT

42 (J6) INPUT

4(C5)

5(A4)

6(B4)

7(A3)

8(A2)

9(B3)

10 (A1)

11 (B2)

12 (C2)

13 (B1)

14 (C1)

15 (D2)

16 (D1)

17 (E3)

20 (F2)

21 (F3)

22 (G3)

23 (G1)

25 (F1)

26 (H1)

27 (H2)

28 (J1)

29 (K1)

30 (J2)

31 (L1)

32 (K2)

33 (K3)

34 (L2)

35 (L3)

36 (K4)

37 (L4)

38 (J5)

46 (L6)

47 (L8)

48 (K8)

49 (L9)

50 (L10)

51 (K9)

52 (L11)

53 (K10)

54 (J10)

55 (K11)

56 (J11)

57 (H10)

58 (H11)

59 (F10)

62 (G9)

63 (F9)

64 (F11)

65 (E11)

67 (E9)

68 (D11)

69 (D10)

70 (C11)

71 (B11)

72 (C10)

73 (A11)

74 (B10)

75 (B9)

76 (A10)

77 (A9)

78 (B8)

79 (A8)

80 (B6)

SYSTEMCLOCK

3, 24, 45, 66 (B5, G2, K7, E10)

18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7) V

GND () – PERTAIN TO 84-PIN PGA PACKAGE

LAB A

LAB B

LAB C

LAB D

LAB E

LAB F

LAB G

LAB H

LABI

LAB J

LAB K

LABL

Logic Block Diagram

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Pin Configurations

Figure 1. CY7C341B Internal Timing Model

I/O

Top View

PLCC/HLCC

9 8 67 5

11 10

4948

4746

34 35 3736 38 39 4241 43 44 4540

VCC

7C341B

84 83 8182 80

21 79 I/O

INPUT

I/O

INPUT/CLK

INPUT

GND

I/O

GND

I/O

VCC

INPUT

GND

INPUT

I/O

GND

I/O

VCC

I/O

VCC

INPUTINPUT/

CLK

GND

I/O I/O

VCC I/O

I/O I/O

GND GND

I/O I/O

I/OI/O

I/O

VCC

INPUT

I/O

GND

I/O

I/OI/O

VCC

I/O

I/OI/O

GNDGND

I/O

PGA

Bottom View

7C341B

INPUT

GND I/O I/O I/O

I/O I/O I/O I/O

1234567891011

I/O I/O

I/O

I/O INPUT INPUT

INPUTINPUTI/O

I/O

I/OI/O

I/O

53525150

I/O

57 I/O

I/O

7778 76 75

I/O

GND

INPUT

GND

I/O

LOGIC ARRAY

CONTROLDELAY

tLAC

EXPANDER

DELAY

tEXP

CLOCK

DELAY

tIC

tRD

tCOMB

tLATCH

INPUT

DELAY

tIN

PIA

DELAY

tPIA

OUTPUT

DELAY

tOD

tXZ

tZX

LOGIC ARRAY

DELAY

tLAD

LOGIC ARRAY

DELAY

tFD

I/O DELAY

tIO

INPUT/

OUTPUT

INPUT

SYSTEM CLOCK DELAY tICS

tRH

tRSU

tPRE

tCLR

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Logic Array Blocks

There are 12 logic arra y blocks in the CY7C341B. Each LAB

consists of a macrocell array containing 16 macrocells, an

expander product term array containing 32 expanders, and an

I/O block. The LAB is fed by the programmable interconnect

array and the dedicated input bus. All macrocell feedbacks go

to the macrocell array, the expander array, and the program-

mable interconnect array . Expanders feed themselves and the

macrocell array. All I/O feedbacks go to the programmable

interconnect array so that they may be accessed by macro-

cells in other LABs as well as the macrocells in the LAB in

which they are situated.

Externally, the CY7C341B provides eight dedicated inputs,

one of which may be used as a system clock. There are 64 I/O

pins that may be individually configured for input, output, or

bidirectional data flow.

Programmable Interconnect Array

The Programmable Interconnect Array (PIA) solves inter-

connect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA are the outputs of every

macrocell within the device and the I/O pi n fe edback of eve ry

pin on the device.

Unlike masked or programmable gate arrays, which induce

variable delay dependent on routing, the PIA has a fixed delay .

This eliminates undesired skews among logic signals, which

may cause glitches in internal or external logic. The fixed

delay, regardless of programmable interconnect a rray config-

uration, simplifies design by assuring that internal signal

skews or races are avoided. The result is ease of design imple-

mentation, often in a single pass, without the mu ltiple internal

logic placement and routing iterations required for a program-

mable gate array to achieve design timing objectives.

Design Recommendations

For proper operation, input and output pins must be

constrained to the range GND < (VIN or VOUT) < VCC.

Unused inputs must always be tied to an appropriate logic

level (either VCC or GND). Each set of VCC and GND pins

must be connected together directly at the device. Power

supply decoupling capacitors of at least 0.2 mF must be

connected between VCC and GND. For the most effective

decoupling, each VCC pin should be separately decoupled to

GND, directly at the device. Decoupling capacitors should

have good frequency response, such as monolithic ceramic

types.

Design Security

The CY7C341B contains a programmable design security

feature that controls th e access to the data programmed into

the device. If this programmable feature is used, a proprietary

design implemented in the device cannot be copied or

retrieved. This enables a high level of design control to be

obtained since programmed data within EPROM cells is

invisible. The bit that controls this function, along with all other

program data, may be reset simply by erasing the device.

The CY7C341B is fully functionally tested and guaranteed

through complete testing of each programmable EPROM bit

and all internal logic elements thus ensuring 100%

programming yield.

The erasable nature of these devices allows test programs to

be used and erased during early stages of the production flow .

The devices also contain on-board l ogic test circuitry to a llow

verification of function and AC specification once encapsu-

lated in non-windowed packages.

400

300

200

100

1 kHz 10 kHz 100 kHz 1 MHz

ICC

MAXIMUM FREQUENCY

10 MHz

050 MHz100 Hz

ACTIVE (mA) Typ.

VCC = 5.0V

Room Temp.

Typical ICC vs. fMAX

01 2 3 4

I OUTPUT CURRENT (mA) TYPICAL

OUTPUTVOLTAGE (V)

250

200

150

100

= 5.0V

Room Temp.

Output Drive Current

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Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................-65°C to +135°C

Ambient Temperature with

Power Applied.............. ........... ....................–65°C to +135°C

Maximum Junction Temperature

(Under Bias).................................................................150°C

Supply Voltage to Ground Potential[1].............. −2.0V to +7.0V

DC Output Current, per Pin[1]..................... −25 mA to +25 mA

DC Input Voltage[1]................................................−2.0V to +7.0V

Operating Range[3]

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 5%

Industrial –40°C to +85°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

VCC Output HIGH Voltage Maximum VCC r i se t i me i s 1 0 m s 4.75(4.5) 5.25(5.5) V

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA[2] 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8 mA[2] 0.45 V

VIH Input HIGH Level 2.0 VCC+ 0.3 V

VIL Input LOW Le ve l −0.3 0.8 V

IIX Input Current GND ≤ VIN ≤ VCC −10 +10 µA

IOZ Output Leakage Current VO = VCC or GND −40 +40 µA

tR (Recommended) Input Rise Time 100 ns

tF (Recommended) Input Fall Time 100 ns

Capacitance

Parameter Description Tes t Conditions Max. Unit

CIN Input Capacitance VIN = 0V, f = 1.0 MHz 10 pF

COUT Output Capacitance VOUT = 0V, f = 1.0 MHz 20 pF

AC Test Loads and Waveforms

Notes:

1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter

than 20 ns.

2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.

3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up .

3.0V

OUTPUT

R1 464Ω

250Ω

50 pF

INCLUDING

JIG AND

SCOPE

GND 90%

10%

90%

10%

<6ns <6ns

OUTPUT

R1 464Ω

250Ω

(a) (b)

OUTPUT 1.75V

Equivalent to: THÉ VENIN EQUIVALENT (commercial/military)

ALL INPUT PULSES

tRtF

5pF

163Ω

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External Switching Characteristics Over the Operating Range

Parameter Description 7C341B-25 7C341B-35 UnitMin. Max. Min. Max.

tPD1 Dedicated Input to Combinatorial Output Delay[4] Commercial 25 35 ns

tPD2 I/O Input to Combinatorial Output Delay[4] Commercial 40 55 ns

tSU Global Clock Set-up Time Commercial 15 25 ns

tCO1 Synchronous Clock Input to Output Delay[4] Commercial 14 20 ns

tHInput Hold Time fro m Synchronous Clock Input Commercial 0 0 ns

tWH Synchronous Clock Input High Time Commercial 8 12.5 ns

tWL Synchronous Cl o ck In pu t Lo w Time Commercial 8 12.5 ns

fMAX Maximum Register Toggle Frequency[5] Commercial 62.5 40.0 MHz

tACO1 Dedicated Asynchronous Clock Input to Output Delay[4] Commercial 25 35 ns

tAS1 Dedicated Input or Feedback Set-up Ti me to

Asynchronous Clock Input Commercial 5 10 ns

tAH Input Hold Time from Asynchronous Clock Input Commercial 6 10 ns

tAWH Asynchronous Clock Input HIGH Time[6] Commercial 11 16 ns

tAWL Asynchronous Clock Input LOW Time[6] Commercial 9 14 ns

tCNT Minimum Global Clock Period Commercial 20 30 ns

tODH Output Data Hold Time After Clock Commercial 2 2 ns

fCNT Maximum Internal Global Clock Frequency[7] Commercial 50 33.3 MHz

tACNT Minimum Internal Array Clock Frequency Commercial 20 30 ns

fACNT Maximum Internal Array Clock Frequency[7] Commercial 50 33.3 MHz

Internal Switching Characteristics Over the Operating Range

Parameter Description 7C341B-25 7C341B-35 UnitMin. Max Min. Max

tIN Dedicated Input Pad and Buffer Delay Commercial 511 ns

tIO I/O Input Pad and Buffer Delay Commercial 611 ns

tEXP Expander Array Delay Commercial 12 20 ns

tLAD Logic Array Data Delay Commercial 12 14 ns

tLAC Logic Array Control Delay Commercial 10 13 ns

tOD Output Buffer and Pad Delay[4] Commercial 5 6 ns

tZX Output Buffer Enable Delay[4] Commercial 10 13 ns

tXZ Output Buffer Disable Delay[8] Commercial 10 13 ns

tRSU Register Set-Up Time Relative to Clock

Signal at Register Commercial 612 ns

tRH Register Hold Time Relative to Clock

Signal at Register Commercial 4 8 ns

tLATCH Flow-Through Latch Delay Commercial 3 4 ns

tRD Register Delay Commercial 1 2 ns

tCOMB Transparent Mode Delay Commercial 3 4 ns

tIC Asynchronous Clock Logic Delay Commercial 14 16 ns

tICS Synchronous Clock Delay Commercial 3 1 ns

Notes:

4. C 1 = 35 pF.

5. The fMAX values represent the highest frequency for pipeline data.

6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.

7. This parameter is measur ed with a 16-bit counter programmed into each LAB.

8. C1 = 5 pF.

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tFD Feedback Delay Commercial 1 2 ns

tPRE Asynchronous Register Preset Time Commercial 5 7 ns

tCLR Asynchronous Register Clear Time Commercial 5 7 ns

tPIA Programmable Interconnect Array Delay Commercial 14 20 ns

Internal Switching Characteristics Over the Operating Range (continued)

Parameter Description 7C341B-25 7C341B-35 UnitMin. Max Min. Max

Switching Waveforms

External Combinatorial

DEDICATED INPUT/

I/O INPUT

COMBINATORIAL

OUTPUT

tPD1/tPD2

tWL

tSU tH

tWH

External Synchronous

CLOCK AT REGISTER

SYNCHRONOUS

LOGIC ARRAY

DATA FROM

REGISTERED

CLOCK PIN

OUTPUTS

tCO1

External Asynchronous

tAH

tAS1 tAWH tAWL

DEDICATED INPUTS OR

REGISTERED FEEDBACK

ASYNCHRONOUS

CLOCK INPUT

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Switching Waveforms (continued)

Internal Combinatorial tIN

tEXP

tLAC,t

LAD

tCOMB tOD

INPUT PIN

I/O PIN

LOGIC ARRAY

OUTPUT

INPUT

ARRAY DELAY

EXPANDER

OUTPUT

Internal Asynchronous

tIO tAWH tAWL tF

tIN

tIC

tRSU tRH

tRD,tLATCH tFD tCLR,tPRE tFD

CLOCK PIN

LOGIC ARRAY

CLOCK FROM

DATA FROM

CLOCK INTO

LOGIC ARRAY

TO ANOTHER LAB

tPIA

TO LOCAL LAB

LOGIC ARRAY

tIN tICS

tRSU tRH

SYSTEM CLOCK PIN

SYSTEM CLOCK

AT REGISTER

DATA FROM

LOGIC ARRAY

Internal Synchronous

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Ordering Information

Speed

(ns) Ordering Code Package Name Package Type Operating Range

25 CY7C341B-25HC/HI H84 84-lead Windowed Leaded Chip Carrier Commercial/Industrial

CY7C341B-25JC/JI J83 84-lead Plastic Leaded Chip Carrier

CY7C341B-25RC/RI R84 84-lead Windowed Pin Grid Array

35 CY7C341B-35HC/HI H84 84-lead Windowed Leaded Chip Carrier Commercial/Industrial

CY7C341B-35JC/JI J83 84-lead Plastic Leaded Chip Carrier

CY7C341B-35RC/RI R84 84-lead Windowed Pin Grid Array

Switching Waveforms (continued)

tXZ tZX

tOD

HIGH IMPEDANCE

STATE

CLOCK FROM

LOGIC ARRAY

DATA FROM

OUTPUT PIN

tRD

Internal Synchronous

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Package Diagrams

84-Leaded Windowed Leaded Chip Carrier H84

51-80081-**

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© Cypress Semi con duct or Cor po rati on , 20 04 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All product and company

names mentioned in this document are trademarks of their respective holders.

Package Diagrams (continued)

51-85006-*A

84-Lead Plastic Leaded Chip Carrier J83

84-Lead Windowed Pin Grid Array R84

51-80026-*B

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Document History Page

Document Title: CY7C341B 192-Macrocell MAX® EPLD

Document Number: 38-03016

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 106316 05/17/01 SZV Change from ecn #: 38-001 37 to 38-03016

*A 113613 04/11/02 OOR PGA package diagram dimensions were updated

*B 122227 12/28/02 RBI Power-up requirements added to Operating Range Information

*C 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”

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