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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
December 2015
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FDMD8580 Rev.1.0
Power 5 x 6
Top Bottom
Pin 1
Pin 1
G1
GR
D1
D1
D2/S1
D2/S1
D1
D2/S1
G2
S2
G1
GR
D1
D1
D2/S1
G2
D2/S1
D2/S1
FDMD8580
Dual N-Channel PowerTrench® MOSFET
Q1: 80 V, 82 A, 4.6 mΩ Q2: 80 V, 82 A, 4.6 mΩ
Features
Q1: N-Channel
Max rDS(on) = 4.6 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 6.0 mΩ at VGS = 8 V, ID = 14 A
Q2: N-Channel
Max rDS(on) = 4.6 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 6.0 mΩ at VGS = 8 V, ID = 14 A
Ideal for Flexible Layout in Primary Side of Bridge Topology
100% UIL Tested
Kelvin High Side MOSFET Drive Pin-out Capability
RoHS Compliant
General Description
This device includes two 80V N-Channel MOSFETs in a dual
power (5 mm X 6 mm) package. HS source and LS drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Applications
Synchronous Buck: Primary Switch of Half / Full Bridge
Converter for Telecom
Motor Bridge: Primary Switch of Half / Full Bridge Converter
for BLDC Motor
MV POL: 48V Synchronous Buck Switch
Half/Full Bridge Secondary Synchronous Rectification
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Q1 Q2 Units
VDS Drain to Source Voltage 80 80 V
VGS Gate to Source Voltage ±20 ±20 V
ID
Drain Current -Continuous TC = 25 °C (Note 5) 82 82
A
-Continuous TC = 100 °C (Note 5) 52 52
-Continuous TA = 25 °C 161a 161b
-Pulsed (Note 4) 482 482
EAS Single Pulse Avalanche Energy (Note 3) 337 337 mJ
PD
Power Dissipation TC = 25 °C 59 59 W
Power Dissipation TA = 25 °C 2.31a 2.31b
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction-to-Case 2.1 2.1 °C/W
RθJA Thermal Resistance, Junction-to-Ambient 551a 55 1b
Device Marking Device Package Reel Size Tape Width Quantity
FDMD8580 FDMD8580 Power 5 x 6 13 ’’ 12 mm 3000 units
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDMD8580 Rev.1.0
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Symbol Parameter Test Conditions Type Min. Typ. Max. Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V Q1
Q2
80
80 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C Q1
Q2 50
50 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V Q1
Q2
1
1μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V Q1
Q2
±100
±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μAQ1
Q2
2.0
2.0
3.4
3.4
4.5
4.5 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C Q1
Q2 -10
-10 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 10 V, ID = 16 A
Q1
3.5 4.6
mΩ
VGS = 8 V, ID = 14 A 4.2 6.0
VGS = 10 V, ID = 16 A, TJ = 125 °C 5.3 7.0
VGS = 10 V, ID = 16 A
Q2
3.5 4.6
VGS = 8 V, ID = 14 A 4.2 6.0
VGS = 10 V, ID = 16 A, TJ = 125 °C 5.3 7.0
gFS Forward Transconductance VDD = 10 V, ID = 16 A Q1
Q2
51
51 S
Ciss Input Capacitance
VDS = 40 V, VGS = 0 V
f = 1 MHz
Q1
Q2 4195
4195
5875
5875 pF
Coss Output Capacitance Q1
Q2 602
602
845
845 pF
Crss Reverse Transfer Capacitance Q1
Q2 19
19
38
38 pF
RgGate Resistance Q1
Q2
0.1
0.1
1.7
1.7
3.5
3.5 Ω
td(on) Turn-On Delay Time
VDD = 40 V, ID = 16 A
VGS = 10 V, RGEN = 6 Ω
Q1
Q2 25
25
40
40 ns
trRise Time Q1
Q2 19
19
34
34 ns
td(off) Turn-Off Delay Time Q1
Q2 31
31
50
50 ns
tfFall Time Q1
Q2 10
10
20
20 ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V
VDD = 40 V,
ID =16 A
Q1
Q2 57
57
80
80 nC
Qgs Gate to Source Charge Q1
Q2
21
21 nC
Qgd Gate to Drain “Miller” Charge Q1
Q2 12
12 nC
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDMD8580 Rev.1.0
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Type Min. Typ. Max. Units
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 16 A (Note 2) Q1
Q2 0.8
0.8
1.3
1.3 V
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2 A (Note 2) Q1
Q2
0.7
0.7
1.2
1.2 V
trr Reverse Recovery Time
IF = 16 A, di/dt = 100 A/μs
Q1
Q2 46
46
73
73 ns
Qrr Reverse Recovery Charge Q1
Q2 34
34
55
55 nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. Q1: EAS of 337 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 15 A, VDD = 80 V, VGS = 10 V. 100% tested at L = 0.1mH, IAS = 49 A.
Q2: EAS of 337 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 15 A, VDD = 80 V, VGS = 10 V. 100% tested at L = 0.1mH, IAS = 49 A.
4. Pulsed Id please refer to Fig 11 and Fig 24 SOA graph for more details.
5. Computed continuous current limited to max junction temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
a. 55 °C/W when mounted on
a 1 i n 2
pad of 2 oz copper
b. 55 °C/W when mounted on
a 1 i n 2
p a d o f 2 o z c o p p e r
c. 155 °C/W when mounted on
a minimum pad of 2 oz copper
d. 155 °C/W when mounted on
a minimum pad of 2 oz copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
G
DF
DS
SF
SS
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDMD8580 Rev.1.0
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
Figure 1.
0.0 0.5 1.0 1.5 2.0
0
30
60
90
120
150
180
VGS = 7 V
VGS = 6 V
VGS = 8 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 5.5 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
0 30 60 90 120 150 180
0.0
1.5
3.0
4.5
6.0
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 7 V
VGS = 8 V
VGS = 5.5 V
VGS = 10 V
N o r m a l i z e d O n - R e s i s t a n c e
vs. Drain Current and Gate Voltage
F i g u r e 3 . N o r m a l i z e d O n R e s i s t a n c e
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
ID = 16 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
vs. Junction Temperature
Figure 4.
45678910
0
5
10
15
20
25
TJ = 125 oC
ID = 16 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
O n- Res is ta nce v s. Ga te t o
Source Voltage
Figure 5. Transfer Characteristics
2345678910
0
30
60
90
120
150
180
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
S ou rce to Dr ai n Di od e
Forward Voltage vs. Source Current
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com
FDMD8580 Rev.1.0
Figure 7.
0 1224364860
0
2
4
6
8
10
ID = 16 A
VDD = 50 V
VDD = 40 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30 V
Gate Charge Characteristics Figure 8.
0.1 1 10 80
1
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
C a p a c i t a n c e v s . D r a i n
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100 1000
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
U n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10.
25 50 75 100 125 150
0
18
36
54
72
90
VGS = 8 V
RθJC = 2.1 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
M a x i m u m C o n t i n u o u s D r a i n
Current vs. Case Temperature
Figure 11.
0.1 1 10 100 300
0.1
1
10
100
1000
10 μs
CURVE BENT TO
MEASURED DATA
100 μs
10 ms
100 ms
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.1 oC/W
TC = 25 oC
F or wa r d B ia s Sa fe
Operating Area
Figure 12.
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000
SINGLE PULSE
RθJC = 2.1 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Single P ul se M axi m um P owe r
Dissipation
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com
FDMD8580 Rev.1.0
Figure 13.
10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 2.1 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
PDM
t1
t2
Junction-to-Case Transient Thermal Response Curve
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com
FDMD8580 Rev.1.0
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.
Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs. Drain
Current and Gate Voltage
Figure 16. Normalized On-Resistance
vs. Junction Temperature
Figure 17. On-Resistance vs. Gate to
Source Voltage
Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode
Forward Voltage vs. Source Current
0.00.51.01.52.0
0
30
60
90
120
150
180
VGS = 7 V
VGS = 6 V
VGS = 8 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 5.5 V
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0 30 60 90 120 150 180
0.0
1.5
3.0
4.5
6.0
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 7 V
VGS = 8 V
VGS = 5.5 V
VGS = 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
ID = 16 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
45678910
0
5
10
15
20
25
TJ = 125 oC
ID = 16 A
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2345678910
0
30
60
90
120
150
180
TJ = 150 oC
VDS = 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com
FDMD8580 Rev.1.0
Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted.
Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain
to Source Voltage
Figure 22. Unclamped Inductive
Switching Capability
F i g u r e 2 3 . M a x i m u m C o n t i n u o u s D r a i n
Current vs. Case Temperature
F i g u r e 2 4 . F o r w a r d B i a s S a f e
Operating Area
Figure 25. Single Pulse Maximum Power
Dissipation
0 1224364860
0
2
4
6
8
10
ID = 16 A
VDD = 50 V
VDD = 40 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30 V
0.1 1 10 80
1
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.001 0.01 0.1 1 10 100 1000
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
18
36
54
72
90
VGS = 8 V
RθJC = 2.1 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.1 1 10 100 300
0.1
1
10
100
1000
10 μs
CURVE BENT TO
MEASURED DATA
100 μs
10 ms
100 ms
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.1 oC/W
TC = 25 oC
10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000
SINGLE PULSE
RθJC = 2.1 oC/W
TC = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.
Figure 26. Junction-to-Case Transient Thermal Response Curve
10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
ZθJC(t) = r(t) x RθJC
RθJC = 2.1 oC/W
Duty Cycle, D = t1 / t2
Peak TJ = PDM x ZθJC(t) + TC
FDMD8580 Dual N-Channel PowerTrench® MOSFET
©2015 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com
FDMD8580 Rev.1.0
www.onsemi.com
1
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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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