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GENERAL DESCRIPTION
The DS2155/DS2156 design kits are evaluation
boards for the DS2155 and DS2156. The
DS2155/DS2156 design kits are intended to be used
as daughter cards with either the DK2000 or the
DK101 motherboards. The boards are complete with
a single-chip transceiver (SCT), transformers,
termination resistors, configuration switches, line
protection circuitry, network connectors, and an
interface to the motherboard.
ORDERING INFORMATION
PART DESCRIPTION
DS2155DK DS2155 Design Kit Daughter Card
DS2156DK DS2156 Design Kit Daughter Card
FEATURES
Expedites New Designs by Eliminating First-
Pass Prototyping
Interfaces Directly to the DK101 or DK2000
Motherboards
Demonstrates Key Functions of the DS2156
and DS2155
High-Level Software Provides Visual Access
to Registers
Software-Controlled (Register Mapped)
Configuration Switches to Facilitate Clock
and Signal Routing
BNC Connections for 75Ω E1
Bantam and RJ48 Con n ectors for 120Ω E1
and 100Ω T1
Multitap Transformer to Facilitate True
Impedance Matching for 75Ω and 120Ω/100Ω
Paths
Network Interface Protection for Overvoltage
and Overcurrent Events
UTOPIA II Bus Connection for MPC8260
(DS2156 Only )
UTOPIA II Prototype Connectors (DS 2156
Only)
Test Points and Prototype Area Available for
Further Customization
DS2155DK/DS2156D
K
T1/E1/J1 Single-Chip Transceive
r
Desi
g
n Kit Dau
g
hter Cards
www.maxim-ic.com
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TABLE OF CONTENTS
COMPONENT LIST.....................................................................................................................3
BASIC OPERATION....................................................................................................................4
HARDWARE CONFIGURATION .................................................................................................................. 4
QUICK SETUP (DEMO MODE).................................................................................................................. 4
QUICK SETUP (REGISTER VIEW) ............................................................................................................. 4
SAMPLE UTOPIA II CONFIGURATION (DS2156 ONLY)............................................................................. 5
REGISTER MAP..........................................................................................................................5
CPLD REGISTER MAP ........................................................................................................................... 6
DS2155/DS2156 INFORMATION................................................................................................8
DS2155DK/DS2156DK INFORMATION......................................................................................8
TECHNICAL SUPPORT..............................................................................................................8
SCHEMATICS .............................................................................................................................8
LIST OF TABLES
Table 1. Daughter Card Address Map .........................................................................................5
Table 2. CPLD Register Map .......................................................................................................6
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COMPONENT LIST
DESIGNATION QTY DESCRIPTION SUPPLIER PART
C1–C5, C8–C12,
C15–C19, C21,
C22, C29–C34
23 0.1mF 10%, 16V ceramic capacitors (0603) Digi-Key 311-1088-1-ND
C7, C36 2 1mF 10%, 16V ceramic capacitors (1206) Digi-Key PCC1882CT-ND
C13, C14 2 0.1mF 10%, 16V ceramic capacitors (0805) Digi-Key 311-1142-1-ND
C23 1
0.1mF 10%, 25V ceramic capacitor (1206) Digi-Key PCC1883CT-ND
C24–C27 4
0.22mF, 50V ceramic capacitors Digi-Key UNK
C35 1
10mF 20%, 16V tantalum capacitor (B case) Digi-Key PCS3106CT-ND
DS1, DS4–DS18 16 LED, green, SMD Digi-Key P501CT-ND
DS2, DS3 2 LED, red, SMD Digi-Key P500CT-ND
F1–F6 6 250V, 1.25A fuse, SMT Teccor Electronics F1250T
J1, J2 2 Male 0.1, SMD, 50-pin, dual-row vertical Samtec TSM-125-01-T-DV
J3, J4 2 Bantam connectors SWK RTT34B02
J5, J6 2 Connector BNC RA 5-pin Kruvand UCBJR220
J7–J9 3 Socket, SMD, 50-pin, dual-row vertical Samtec TFM-125-02-S-D-
LC
JT10 1 Connector, 10-pin, dual-row vertical Digi-Key S2012-05-ND
L1 1
Choke, dual 4-line 24mH, 8-pin SO Pulse Engineering PE-65857
R1, R14, R21 3 51.1W 1%, 1/8W resistors (1206) Digi-Key P51.1FCT-ND
R2, R3, R58, R59 4 0W 5%, 1/8W resistors (1206) Digi-Key P0.0ETR-ND
R4, R5, R60 3 51.1W 1%, 1/10W resistors (0805) Digi-Key P51.1CCT-ND
R6, R9, R10, R13,
R15–R19, R22,
R23, R25–R29,
R32, R37, R38,
R44, R47–R49, R61
24 10kW 1%, 1/10W resistors (0805) Digi-Key P10.0KCCT-ND
R7, R8, R11, R12,
R30, R31, R35,
R36, R39–R43,
R45, R50–R53
18 330W 0.1%, 1/10W MF resistors (0805) Digi-Key P330ZCT-ND
R24 1
1.0kW 1%, 1/10W resistor (0805) Digi-Key P1.00KCCT-ND
R33, R34 2 NOPOP — NOPOP
R46 1
4.7kW 1%, 1/8W resistor (0805) Digi-Key 9C08052A4701FK
HFT
R54, R55 2 61.9W 1%, 1/8W resistors (1206) Digi-Key P61.9FCT-ND
R56, R57 2 49.9W 1%, 1/8W resistors (1206) Digi-Key P49.9FCT-ND
RJ1 1 RJ48 connector Molex 43223
SW1 1 Switch DPDT slide 6-pin TH Avnet SSA22
T1 1 XFMR 16-pin SMT Pulse Engineering TX1099
U11 1 T1/E1/J1 XCVR 100-pin QFP, 0°C to +70°C Dallas Semiconductor DS2156L
U1–U4, U6 5 BBUS switch 10-bit CMOS, 150-mil, 24-pin SO IDT IDTQS3R861Q
U5 1 144-pin macrocell CPLD Avnet XC95144XL-
10TQ100C
U7–U10 4 Quad bus switch, 150-mil, 16-pin SO IDT IDTQS3125Q
Z1, Z6–Z8 4 160V, 500A Sidactor Teccor Electronics P1800SCMC
Z2, Z3 2 58V, 500A Sidactor Teccor Electronics P0640SCMC
Z4, Z5 2 6V, 50A Sidactor Teccor Electronics P0080SAMC
Z9, Z10 2 25V, 500A Sidactor Teccor Electronics P0300SCMC
DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
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BASIC OPERATION
This design kit relies upon several supporting files, which can be downloaded from our website at www.maxim-
ic.com/DS2155DK.
Hardware Configuration
Using the DK101 processor board:
· Connect the daughter card to the DK101 processor board.
· Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector and the
TIM 5V supply headers are unused.)
· All processor board DIP switch settings should be in the ON position with exception for the flash programming
switch, which should be OFF.
· From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select
Programs®ChipView®ChipView.
Using the DK2000 processor board:
· Connect the daughter card to the DK2000 processor board.
· Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected
to connector J2.
· From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select
Programs®ChipView®ChipView.
General:
· Upon power-up the RLOS LED is lit, as well as the MCLK-2.048MHz and TCLK-2.048MHz LEDs.
· Due to the dual winding transformer, only the 120W line build-out configuration setting is needed to cover 75W
E1 and 120W E1.
Quick Setup (Demo Mode)
· The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select
Demo Mode.
· The program requests a configuration file, then select between the displayed files.
(DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg).
· The Demo Mode screen appears. Upon external loopback, the LOS and OOF indicators extinguish.
Quick Setup (Register View)
· The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select
Register View.
· The program requests a definition file, then select DS2155.def.
· The Register View screen appears, showing the register names, acronyms, and values.
· Predefined register settings for several functions are available as initialization files.
¾ INI files are loaded by selecting the menu File®Reg Ini File®Load Ini File.
¾ Load the INI file DS2155_T1_BERT_ESF.ini.
¾ After loading the INI file the following may be observed:
The RLOS LED extinguishes upon external loopback.
The DS2155/DS2156 begins transmitting a Daly pattern. When external loopback is applied, the BERT
bit-count registers BBC1–3 and BEC1–3 may be updated by clearing and setting BC1.LC and
clicking the Read All button.
Miscellaneous:
· Clock frequencies and certain pin bias levels are provided by a register-mapped CPLD, which is on the
DS2155/DS2156 daughter card.
· The definition file for this CPLD is named DS215x_35x_CPLD_V2.def. See the CPLD Register Map section for
definitions.
· All files referenced above are available for download at www.maxim-ic.com/DS2155DK.
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Sample UTOPIA II Configuration (DS2156 Only)
The following register settings configure the DS2156 daughter card for UTOPIA II, single CLAV, 8-bit mode on PHY
port 0. UTOPIA II bus connection is provided by header J1 (Tx) and header J2 (Rx).
After configuring the following registers toggle the MSTREG.URST bit to reset the UTOPIA II core.
UTOPIA II Setup, Register Settings for daughter card CPLD
NAME VALUE NAME VALUE
SWITCH 1 0x0F SWITCH 4 0x0F
SWITCH 2 0x03 LEVELS 0x07
SWITCH 3 0x0F
UTOPIA II Setup, Register Settings for DS2156 E1 Configuration
NAME VALUE NAME VALUE
MSTREG 0x02 LBCR 0x00
E1RCR1 0x68 TAF 0x9B
E1RCR2 0x00 TNAF 0xC0
E1TCR1 0x15 LIC1 0x11
E1TCR2 0x00 LIC2 0x90
CCR1 0x00 LIC3 0x00
CCR4 0x00 LIC4 0x00
IOCR1 0x00
IOCR2 0x00
UTOPIA II Setup, Register Settings for DS2156 UTOPIA II Configuration
NAME VALUE NAME VALUE
U_TCFR 0x01 U_RCR2 0x0
U_TCR1 0x05 U_TIUPB 0x0
U_TCR2 0x00 PCPR 0x22
U_RCFR 0x01 PCDR1, 2, 3, 4 0x0
U_RCR1 0x01
REGISTER MAP
The DK101 daughter card address space begins at 0x81000000.
The DK2000 daughter card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given in Table 1 are relative to the beginning of the daughter card address space.
Table 1. Daughter Card Address Map
OFFSET DEVICE DESCRIPTION
0X0000
to
0X0015
CPLD Board identification and clock/signal routing
0X1000
to 0X10ff
Single-Chip
Transceiver
Board is populated with one of the following:
DS2156, DS2155, DS21352, or DS21354.
Please see data sheet for details.
Registers in the CPLD can be easily modified using the ChipView.exe, a host-based user interface software along
with the definition file named DS215x_35x_CPLD_V2.def. Definition files for the SCT are named DS2155.def,
DS21352.def, or DS21354.def, depending on the board population option.
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CPLD Register Map
Table 2. CPLD Register Map
OFFSET NAME TYPE DESCRIPTION
0X0000 BID Read-Only Board ID
0X0002 XBIDH Read-Only High-Nibble Extended Board ID
0X0003 XBIDM Read-Only Middle-Nibble Extended Board ID
0X0004 XBIDL Read-Only Low-Nibble Extended Board ID
0X0005 BREV Read-Only Board FAB Revision
0X0006 AREV Read-Only Board Assembly Revision
0X0007 PREV Read-Only PLD Revision
0X0011 SWITCH1 Read-Write Pin to 1.544MHz
0X0012 SWITCH2 Read-Write Pin to 2.048MHz
0X0013 SWITCH3 Read-Write Pin-to-Pin Connect
0X0014 SWITCH4 Read-Write Pin-to-Pin Connect
0X0015 LEVELS Read-Write Set Level On Pin 1 = 3.3V
ID Registers
OFFSET NAME TYPE VALUE DESCRIPTION
0X0000 BID Read-Only 0xD Board ID
0X0002 XBIDH Read-Only 0x0 High-Nibble Extended Board ID
0X0003 XBIDM Read-Only 0x0 Middle-Nibble Extended Board ID
0X0004 XBIDL Read-Only 0x5 Low-Nibble Extended Board ID
0X0005 BREV Read-Only
Displays current
FAB revision Board FAB Revision
0X0006 AREV Read-Only
Displays current
assembly revision Board Assembly Revision
0X0007 PREV Read-Only
Displays current
PLD firmware
revision
PLD Revision
Control Registers
The control registers are used primarily to control several banks of FET switches that route clocks and backplane
signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4
both to 0 would drive MCLK with both 1.544MHz and 2.048MHz.
SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF
(MSB) (LSB)
— — — — MCLK TCLK RSYSCLK TSYSCLK
NAME POSITION FUNCTION
MCLK SWITCH1.3
0 = Connect MCLK to the 1.544MHz clock
1 = Open Switch 1.4
TCLK SWITCH1.2
0 = Connect TCLK to the 1.544MHz clock
1 = Open Switch 1.3
RSYSCLK SWITCH1.1
0 = Connect RSYSCLK to the 1.544MHz clock
1 = Open Switch 1.2
TSYSCLK SWITCH1.0
0 = Connect TSYSCLK to the 1.544MHz clock
1 = Open Switch 1.1
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SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3
(MSB) (LSB)
— — — — MCLK TCLK RSYSCLK TSYSCLK
NAME POSITION FUNCTION
MCLK SWITCH2.3
0 = Connect MCLK to the 2.048MHz clock
1 = Open Switch 2.4
TCLK SWITCH2.2
0 = Connect TCLK to the 2.048MHz clock
1 = Open Switch 2.3
RSYSCLK SWITCH2.1
0 = Connect RSYSCLK to the 2.048MHz clock
1 = Open Switch 2.2
TSYSCLK SWITCH2.0
0 = Connect TSYSCLK to the 2.048MHz clock
1 = Open Switch 2.1
SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF
(MSB) (LSB)
— — — — TSS_RS TCL_RC RSY_RC TSY_RC
NAME POSITION FUNCTION
TSS_RS SWITCH3.3
0 = Connect TSSYNC to RSYNC
1 = Open Switch 3.4
TCL_RC SWITCH3.2
0 = Connect TCLK to RCLK
1 = Open Switch 3.3
RSY_RC SWITCH3.1
0 = Connect RSYSCLK to RCLK
1 = Open Switch 3.2
TSY_RC SWITCH3.0
0 = Connect TSYSCLK to RCLK
1 = Open Switch 3.1
SWITCH4: PIN-TO-PIN CONNECT (Offset = 0X0014) INITIAL VALUE = 0x3
(MSB) (LSB)
— — — —
UTCLK_2048 UT_CLK_2048 RSER_TSER RSYNC_TSYNC
NAME POSITION FUNCTION
URCLK_2048 SWITCH4.3
0 = Connect UR_CLK (TSSYNC) to 2.048MHz
1 = Open Switch 4.4
UTCLK_2048 SWITCH4.2
0 = Connect UT_CLK (TCHCLK) to 2.048MHz
1 = Open Switch 4.3
RSER_TSER SWITCH4.1
0 = Connect RER to TSER
1 = Open Switch 4.2
RSYNC_TSYNC SWITCH4.0 0 = Connect RSYNC to TSYNC
1 = Open Switch 4.1
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
LEVELS: SET LEVEL ON PIN (Offset = 0X0015) INITIAL VALUE = 0x6
(MSB) (LSB)
— — — — — BP_EN PPCTDM_EN TUSEL
NAME POSITION FUNCTION
— LEVELS1.3 —
BP_EN LEVELS1.2
0 = Enable IDT switches that connect th e UTOPIA bus to
daughter card header
PPCTDM_EN LEVELS1.1
0 = Enable IDT switches that connect th e TDM bus to the
daughter card header
TUSEL LEVELS1.0
0 = Set DS2156.TUSEL to enable TDM backplane
1 = Set DS2156.TUSEL to enable UTOP IA backplane
Note: When the UTOPIA backplane is enabled (LEVELS.TUSEL = 1) there is a possibility for contention between
the UTOPIA bus master and TSYSCLK, TSER, and RSER. To avoid this, the following switches should be opened
when the UTOPIA backplane is enable d: SWITCH1.0, SWITCH2.0, SWITCH3.0, and SWITCH4.1
DS2155/DS2156 INFORMATION
For more information about the DS2155 and DS2156, please consult the DS2155 and DS2156 data sheets
available on our website at www.maxim-ic.com/DS2155 and www.maxim-ic.comDS2156. Software downloads are
also available for this design kit.
DS2155DK/DS2156DK INFORMATION
For more information about the DS2155DK and DS2156DK, including software d ownloads, please con sult the
DS2155DK/DS2156DK dat a sheet available on our website at www.maxim-ic.com/DS2155DK.
TECHNICAL S UPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS2155DK/DS2156DK schematics are featured in the following 13 pages.
DOCUMENT REVISION HISTORY
REVISION
DATE DESCRIPTION
032503 Initial DS2155DK/DS2156DK data shee t release.
060303 Updated the Title, General Description, Features, and Basic Operation
sections; “TIM” replaced with “daughter card.”
012705 Updated schematics (removed component values for Fuse and Sidactor; see
Component List).
110106 Updated schematics.
/
CONTENTS
DS2156, DS2155, DS2135Y DESIGN KIT
DS2156DK02A0
5. CPLD ADDRESS DATA CONNECTIONS, BIAS LEVELS FOR SCT
2. SCT POPULATION OPTION (DS2155, DS2156, DS21352 OR DS21354)
4. TIM ADDRESS AND DATA BUS
3. TX AND RX ANALOG PATHS
1. COVER PAGE
13. PART CROSS-REFERENCE
12. NETLIST CROSS-REFERENCE
6. UTOPIA: TIM HEADER AND BUS SWITCHES
7. TESTPOINTS FOR UTOPIA 2
8. UTOPIA: NETLIST ASSOCIATIONS
9. SWITCHING FOR CLOCKS AND TDM
10. SUPPLY DECOUPLING
11. SCT TESTPOINTS
STEVE SCULLY
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D_AD2
D_AD3
UOP3
UOP2
UOP1
UOP0
ESIBS1
ESIBS0
BPCLK
RMSYNC
A7
D_AD4
D_AD5
D_AD6
D_AD7
TSYSCLK
TLCLK
8XCLK
TTIP
LIUC
RCL
INT
A0
A1
D_AD0
CS
TCHBLK
RCHBLK
TSSYNC
TCLK
TLINK
RPOSI
TSIG
TCHCLK
TSYNC
TRING
TPOSO
TCLKI
TCLKO
TNEGO
JTRST
JTDO
TPOSI
RFSYNC
BTS
MUX
RSIG
RSER
TUSEL
TSER
ESIBRD
XTALD
N_P27
RDATA
A4
A3
JTMS
JTDI
JTCLK
RLOS_LOTC
RNEGI
TNEGI
RSYSCLK
RCLKI
RPOSO
RNEGO
RCLKO
MCLK
RSIGF
TSTRST
RD_DS
WR_RW
N_P28
RRING
A2
D_AD1
RLCLK
RCHCLK
RSYNC
A5
A6
RLINK
RCLK
RTIP
DS2156L
U11
13
66
67
68
69
70
71
72
73
3
11
75
56
57
58
59
62
63
64
65
44
61
81
83
45
60
80
84
76
36
54
25
4
7
10
2
5
12
21
55
26
27
28
1
92
6
82
88
89
74
85
97
79
78
99
96
87
90
86
91
17
95
94
93
98
100
16
18
19
20
24
33
53
46
40
41
50
49
34
35
39
42
38
43
32
47 48
52
14
37
51
29
31
30
8
9
15
23
77
22
TDATA
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8
V3_3
TQFP
DS2156
D/AD<2>
D/AD<3>
UOP3
UOP2
UOP1
UOP0
ESIBS<1>
ESIBS<0>
DVSS4
DVSS3
BPCLK
RMSYNC
ALE/AS/A<7>
D/AD<4>
D/AD<5>
D/AD<6>
D/AD<7>
TSYSCLK
TLCLK
8XCLK
TTIP
LIUC
RCL
INT*
A<0>
A<1>
D/AD<0>
CS*
TCHBLK
RCHBLK
TSSYNC
TDATA
TCLK
TLINK
RVDD
RPOSI
TESO
TSIG
TCHCLK
TSYNC
DVDD3
TRING
TPOSO
TCLKI
TCLKO
TNEGO
JTRST
JTDO
RVSS1
TVSS
TPOSI
RFSYNC
TVDD
DVDD1
DVDD2
DVSS1
DVSS2
BTS
MUX
RSIG
RSER
RVSS2
NC1
TSER
ESIBRD
XTALD
NC2
RDATA
A<4>
A<3>
JTMS
JTDI
JTCLK
RLOS/LOTC
RNEGI
TNEGI
RSYSCLK
RCLKI
RPOSO
RNEGO
RCLKO
MCLK
RSIGF
TSTRST
RD/DS*
WR/RW*
NC3
RRING
RVSS3
A<2>
D/AD<1>
RLCLK
RCHCLK
RSYNC
DVDD4
A<5>
A<6>
RLINK
RCLK
RTIP
/
13
10/04/02
STEVE SCULLY
DS2156DK02A0
3
1
7
11
2
1
C25
2
1
C24
2
1
R60
1
2
Z6
1
2
Z8
1
2
Z10
1
2
Z9
1
2
Z7
1
2
Z1
2
1
R2
2
1
R3
2
1
R59
2
1
R58
2
1
C23
6
54
3
2
1
SW1
2
1
R55
2
1
R54
2
1
R57
1
2
Z3
2
1
R56
1
2
Z4
1
2
3
4
16
15
14
T1
2
1
C26
2
1
C7
1
2
Z5
5
6
8
10
9
T1
2
Z2
2
1
C27
3
6
4 5
L1
2
1
F1
2
1
F6
1
2
J5
2
1
F2
1
8
2
7
L1
2
1
F4
2
1
F3
8
7
6
5
4
3
2
1
RJ1
2
5
J3
2
5
J4
2
1
F5
1
2
J6
49.9
0.22UF
24 UH
RRING
RTIP
TRING
TTIP
0
0
0
0
61.9
61.9
51.1
0.22UF
0.22UF
49.9
0.1UF
1UF
24 UH
0.22UF
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8
Z Z
Z
Z
Z
RJ48
1
2
3
4
5
6
8
7
Z
CONN_BANTAM_IPC
R
T
CONN_BANTAM_IPC
R
T
DPDT
Z
Z
1:1
1:0.8
Z
1:1
1:0.8
Z
CONN_BNC_5PIN
CONN_BNC_5PIN
J1X
JX
/
UNUSED
(TIM LSB)
13
STEVE SCULLY
DS2156DK02A0
4
10/04/02
J9
A3
A922
NIMD15
NIMD14
A11
SNIM_B4
A10
NIMD13
RESET_OUT
A1
PPC_RXCLK
PPC_TXCLK
A6
A12
A13
SNIM_B3
SNIM_B2
CLK16384_T
A15
A14
D_AD7
D_AD6
D_AD5
TIM5V
TIM5V
CLK1544_T
SNIM_B6
SNIM_B5
51.1
PPC_TXD
PPC_RXD
INT
A7
WE_T
RW_T
A8
A5
A0
PPC_RSYNC
A2
A4
D_AD0
D_AD2
D_AD3
D_AD4
CS_T
PPC_TSYNC
SNIM_B7
NIMD11
NIMD10
NIMD9
NIMD8
NIMD12
D_AD1
R1
1
2
J8
1
23 24
25 26
27
28
29
30
31
32
33 34
35 36
37
38
39
40
41
42
43 44
2
45 46
47
48
49 50
3
4
5 6
7
8
9
10
11
12
13 14
15 16
17 18
19
20
21
22
1
23
24
25
26
27 28
29
30
31
32
33
34
35
36
37 38
39
40
41
42
43
44
2
45
46
47 48
49
50
3
4
5 6
7
8
9
10
11
12
13 14
15 16
17 18
19
20
21
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
5049
48
47
4645
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2423
22
21
17
11
7
4
25 26
20
19
9
1
8
16
12
10
2
14
3
65
18
15
13
V3_3
5049
4847
4645
4443
42
41
40
39
3837
3635
3433
32
31
30
29
2827
2423
22
21
17
11
7
4
25 26
20
19
9
1
8
16
12
10
2
14
3
65
18
15
13
ALL UNMARKED BIAS RESISTORS ARE 10K
GREEN LEDS DS7 ..TO.. DS18
/
13
10/04/02
STEVE SCULLY
DS2156DK02A0
5
JT10
DS16
DS17
TSSYNC
A12
BP_EN
10K
1
2
R61
1
2
R44
1
2
R28
1
2
R47
1
2
R16
1
2
R23
2
1
R22
2
1
R49
2
1
R9
1
2
R6
1
2
R10
2
1
R38
2
1
R46
1
2
R24
10
9
8
7
65
4
3
2
1
1
2
R27
1
2
R26
1
2
R25
1
TP18
1
TP15
1
TP14
2
1
R11
2
1
DS3
2
1
R32
2
1
R48
2
1
R37
2
1
R19
2
1
R29
2
1
R18
2
1
R15
2
1
R17
2
1
R13
47
83
45
48
100
84
75
69
62
44
31
21
98
57
5
88
51
38
26
U5
R51
R52
1
R40
1
1
R42
R36
1
1
R31
R39
12
11
99
97
96
10
95
94
93
92
91
90
89
87
86
85
9
82
81
79
78
77
76
74
72
71
70
8
68
67
66
65
64
63
61
60
59
58
6
56
55
54
53
52
50
49
42
41
40
4
39
37
36
35
33
32
30
29
28
27
3
25
23
22
20
18
17
16
15
14
13
1
U5
1
R41
1
1
R35
R30
1
1
1
R45
R50
R43
1
R53
2
1
R8
2
1
DS2
1
TP17
1
TP12
1
TP13
BTS
INT_INDICATOR
RED
TSYSCLK
CLK16384_T
CLK2048
TUSEL
MUX
RESET_OUT
RW_T
CS_T
PPC_TDM_EN
WE_T
A11
INT
LIUC
TSIG
TLINK
A3
330
330
330
330
330
330
330
330
330
330
330
330
RED
10K
10K
1.0K
TCK
SW4_B2EN
SW4_B3EN
CS
A6
A5
A4
A2
A1
A0
RD_DS
WR_RW
BTS
A7
D_AD0
D_AD1
D_AD4
D_AD6
RLOS_LOTC
INT
SW3_B3EN
D_AD2
SW4_B0EN
SW4_B1EN
TCK
TDO
TDI
RSYNC
TSYNC
TCLK
TDO
TDI
TMS
ESIBRD
RPOSI
RNEGI
RCLKI
TNEGI
TCLKI
TSTRST
MUX
330
TMS
330
D_AD5
D_AD3
SW2_B3EN
SW2_B1EN
SW1_B2EN
SW1_B0EN
SW2_B2EN
330
D_AD7
SW3_B0EN
SW3_B1EN
SW3_B2EN
RLOS_LOTC_INDICATOR
TSER
TPOSI
RSYSCLK
4.7K
JTRST
330
SW2_B0EN
SW1_B3EN
SW1_B1EN
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V3_3
V3_3
4
2
8
10
3
1
5
9
CONN_10P
6
7
V3_3
TP TP TP
V3_3
XILINX_XC9572XL
TDI
TDO
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
3.3V2
TCK
TMS
NC<8-0>
2.5V_3.3V1
2.5V_3.3V2
2.5V_3.3V3
2.5V_3.3V4
3.3V1
3.3V3
V3_3
TP
XILINX_XC9572XL
GCK1
GCK2
GCK3
IO17
IO18
IO34
IO24
IO23
IO54
IO53
IO52
IO51
IO50
IO49
IO48
IO47
IO46
IO45
IO44
IO43
IO42
IO41
IO40
IO39
IO38
IO37
IO19
IO20
IO21
IO22
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO35
IO36
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO1
IO61
IO72
IO71
IO70
IO69
IO68
IO67
IO66
IO65
IO64
IO63
IO62
IO60
IO59
IO58
IO55
IO57
IO56
IO2
TP
TP
/
BP_EN IS BIT MAPPED TO
LOGIC 0 CLOSES SWITCHES
TIM J2X
PLD ADDRESS 0X15 BIT 2
DS2156DK02A0
STEVE SCULLY
10/04/02
6
13
24
1
12
23
13
14
15
16
17
18
19
20
21
22
11
10
9
8
7
6
5
4
3
2
U3
24
1
12
23
13
14
15
16
17
18
19
20
21
22
11
10
9
8
7
6
5
4
3
2
U4
22
21
20
19
1817
1615
1413
12
11
10
9
8
7
65
4
3
5049
48
47
4645
2
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2625
2423
1
J7
2
1
DS4
2
1
R12
24
1
12
23
13
14
15
16
17
18
19
20
21
22
11
10
9
8
7
6
5
4
3
2
U1
2
1
R4
24
1
12
23
13
14
15
16
17
18
19
20
21
22
11
10
9
8
7
6
5
4
3
2
U2
2
1
R5
TXDATA_4
BP_EN
RXPRTY
51.1
51.1
330
GREEN
UT_CLK
TXA_0
TXA_4_TXCLAV_3
TXENA
TXDATA_3
TXDATA_1
TXDATA_5
TXDATA_7
TXA_2_TXCLAV_1
BP_EN
TXA_4_TXCLAV_3
UR_CLK
RXA_2_RXCLAV_1
RXENA
RXDATA_1
RXDATA_5
RXDATA_3
RXDATA_7
RXA_0
RXA_4_RXCLAV_3
TXA_2_TXCLAV_1
GND
TXPRTY
GND
GND
GND
GND
GND
GNDGND
RXA_3_RXCLAV_2
TXCLAV_0
TXA_3_TXCLAV_2
TXSOC
TXDATA_0
TXDATA_2
TXDATA_6
TXA_1
TXA_3_TXCLAV_2
RXSOC
RXDATA_0
RXDATA_4
RXDATA_2
RXDATA_6
RXA_1
BP_EN
BP_EN
RXA_4_RXCLAV_3
RXA_2_RXCLAV_1
RXCLAV_0
RXA_3_RXCLAV_2
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
IDTQS3R861
NC1
GND
B0
VCC
BE*
B1
B3
B4
B6
B5
B7
B8
B9
B2
A0
A1
A3
A2
A4
A5
A6
A7
A8
A9
V3_3
IDTQS3R861
NC1
GND
B0
VCC
BE*
B1
B3
B4
B6
B5
B7
B8
B9
B2
A0
A1
A3
A2
A4
A5
A6
A7
A8
A9
IDTQS3R861
NC1
GND
B0
VCC
BE*
B1
B3
B4
B6
B5
B7
B8
B9
B2
A0
A1
A3
A2
A4
A5
A6
A7
A8
A9
V3_3
IDTQS3R861
NC1
GND
B0
VCC
BE*
B1
B3
B4
B6
B5
B7
B8
B9
B2
A0
A1
A3
A2
A4
A5
A6
A7
A8
A9
V3_3
5049
48
47
4645
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2423
22
21
17
11
7
4
25 26
20
19
9
1
8
16
12
10
2
14
3
65
18
15
13
V3_3
/
ADTECH RX ADTECH TX
13
7
10/04/02
STEVE SCULLY
DS2156DK02A0
WE_T
1
TP8
RESET_OUT
TP6
1
CS_T
TP7
1
A13
1
TP2
CLK16384_T
1
TP1
CLK1544_T
TP16
1
RW_T
1
TP9
A9
TP10
1
A8
TP11
1
A12
TP3
1
2
1
R21
22
21
20
19
1817
1615
1413
12
11
10
9
8
7
65
4
3
50
49
4847
46
45
2
44
43
42
41
40
39
3837
36
35
34
33
32
31
30
29
2827
26
25
24
23
1
J2
22
21
20
19
1817
1615
1413
12
11
10
9
8
7
65
4
3
5049
48
47
4645
2
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2625
2423
1
J1
1
2
R14
1
TP20
1
TP21
1
TP22
1
1
TP5
TP4
A11
A10
GND
UT_CLK
TXDATA_0
TXDATA_7
TXADDR4
TXADDR2
TXADDR0
TXENABLE
TXSOC
GND
TXDATA_4
RXDATA_1
RXADDR0
GND
GND
TXDATA_2
UR_CLK
RXSOC
RXDATA_3
RXDATA_6
RXDATA_2
RXDATA_0
GND
RXADDR4
GND
RXENB
RXADDR1
RXDATA_4
GND
RXCLAV0
RXADDR3
RXADDR2
GND
RXDATA_5
RXDATA_7
TXDATA_3
TXDATA_6
GND
TXADDR1
TXCLAV0
TXDATA_1
TXADDR3
GND
GND
TXDATA_5
51.1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
TP TP TP TP
TP TP TP TP
5049
4847
4645
4443
42
41
40
39
3837
3635
3433
32
31
30
29
2827
2423
22
21
18
17
1615
1413
12
11
9
7
2
4
5
3
25 26
10
8
6
1
CONN_50P1
20
19
5049
48
47
4645
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2423
22
21
1817
1615
1413
12
11
9
7
2
4
5
3
25 26
10
8
6
1
CONN_50P1
20
19
TP
TP TP TP
TP TP
TP
/
DS2156DK02A0
STEVE SCULLY
10/04/02
8
13
2
1
C13
2
1
R33
2
1
C14
2
1
R34
RXSOC
UR_SOC
UR_ENB
UOP3
TXA_1
TXA_2_TXCLAV_1
NOPOP
0.1UF
NOPOP
0.1UF
TXDATA_6TXDATA_6
TSIG
TSYSCLK
TXDATA_7TXDATA_7
TXENA
TXENABLE
UOP1
UOP0
TXSOCTXSOC
TSSYNC
UT_CLK
TCHCLK
UR_CLK
UT_DATA6
RXENA
RXENB
BPCLK
RXSOC
UT_DATA7
UT_ENB
UT_SOC
RCHBLK
TXA_0
TXADDR0
TCHBLK
TXADDR2
TLCLK
TXA_3_TXCLAV_2
TXADDR3
TLINK
TXA_4_TXCLAV_3
TXADDR4
UT_CLAVTXCLAV0
TPOSI
LIUC
UT_ADDR0
UT_ADDR1
UT_ADDR2
UT_ADDR3
UT_ADDR4
TXCLAV_0
TXDATA_0TXDATA_0
TNEGI
TXDATA_1TXDATA_1
TCLKI
TCLKO
TXDATA_2TXDATA_2
TXDATA_3TXDATA_3
TNEGO
TXDATA_4TXDATA_4
TPOSO
TSER
TXDATA_5TXDATA_5
UT_DATA0
UT_DATA1
UT_DATA2
UT_DATA3
UT_DATA4
UT_DATA5
RCHCLK
RXA_0
RXADDR0
RXA_1
RXADDR1
UR_ADDR0
RSIGF
RXA_2_RXCLAV_1
RXADDR2
RSIG
RXA_3_RXCLAV_2
RXADDR3
RMSYNC
RXA_4_RXCLAV_3
RXADDR4
RFSYNC
UR_ADDR1
UR_ADDR2
UR_ADDR3
UR_ADDR4
RXCLAV_0RXCLAV0
RSER
RXDATA_0RXDATA_0
RLINK
RXDATA_1RXDATA_1
UR_CLAV
UR_DATA0
RLCLK
RXDATA_2RXDATA_2
RPOSI
RXDATA_3RXDATA_3
RNEGI
RXDATA_4RXDATA_4
RCLKI
UR_DATA1
UR_DATA2
UR_DATA3
UR_DATA4
RXDATA_5RXDATA_5
RCLKO
RXDATA_6RXDATA_6
RNEGO
RXDATA_7RXDATA_7
RPOSO
UR_DATA5
UR_DATA6
UR_DATA7
TXADDR1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
LOGIC 1 OPENS SWITCH
/
PPC_TDM_EN IS BIT MAPPED TO
TO PLD REGISTER 0X14
SWITCH 4 IS MEMORY MAPPED
LOGIC 0 CLOSES SWITCH
TO PLD REGISTER 0X13
TO PLD REGISTER 0X12
LOGIC 0 CLOSES SWITCH
TO PLD REGISTER 0X11
LOGIC 1 OPENS SWITCH
LOGIC 0 CLOSES SWITCH
SWITCH 1 IS MEMORY MAPPED
LOGIC 1 OPENS SWITCH
LOGIC 0 CLOSES SWITCH
SWITCH 3 IS MEMORY MAPPED
LOGIC 1 OPENS SWITCH
SWITCH 2 IS MEMORY MAPPED
PLD ADDRESS 0X15 BIT 1
LOGIC 0 CLOSES SWITCHES
13
9
10/04/02
STEVE SCULLY
DS2156DK02A0
16
9
1
8
13
15
14
10
12
11
7
5
6
4
2
3
U10
16
9
1
8
13
15
14
10
12
11
7
5
6
4
2
3
U8
24
1
12
23
13
14
15
16
17
18
19
20
21
22
11
10
9
8
7
6
5
4
3
2
U6
2
1
DS1
2
1
R7
16
9
1
8
13
15
14
10
12
11
7
5
6
4
2
3
U9
16
9
1
8
13
15
14
10
12
11
7
5
6
4
2
3
U7
SW1_B1EN
SW4_B1EN
SW4_B0EN
SW1_B2EN
SW2_B2EN
SW2_B1EN
SW2_B0EN
MCLK
RSYSCLK
TSYSCLK
SW1_B3EN
TCLK
MCLK
PPC_TXD
PPC_TDM_EN
PPC_RXD
PPC_RXCLK
PPC_TSYNC
PPC_RSYNC
PPC_TXCLK
TSER
RSER
RCLK
TCLK
TSYNC
RSYNC
TSER
TSYNC
SW4_B3EN
SW4_B2EN
UT_CLK
UR_CLK
RSER
RSYNC
RCLK
RCLK
TSSYNC
TCLK
SW3_B3EN
SW3_B2EN
SW3_B1EN
SW3_B0EN
RCLK
RSYNC
RSYSCLK
TSYSCLK
CLK2048
CLK2048
GREEN
330
TCLK
RSYSCLK
TSYSCLK
SW2_B3EN
CLK1544_T
SW1_B0EN
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
IDTQS3125
2Y
1Y
4A
3A
4OE*
3OE*
2OE*
1OE*
3Y
4Y
2A
1A
NC2
GND
VCC
NC1
V3_3
IDTQS3125
2Y
1Y
4A
3A
4OE*
3OE*
2OE*
1OE*
3Y
4Y
2A
1A
NC2
GND
VCC
NC1
IDTQS3125
2Y
1Y
4A
3A
4OE*
3OE*
2OE*
1OE*
3Y
4Y
2A
1A
NC2
GND
VCC
NC1
V3_3
IDTQS3125
2Y
1Y
4A
3A
4OE*
3OE*
2OE*
1OE*
3Y
4Y
2A
1A
NC2
GND
VCC
NC1
V3_3
IDTQS3R861
NC1
GND
B0
VCC
BE*
B1
B3
B4
B6
B5
B7
B8
B9
B2
A0
A1
A3
A2
A4
A5
A6
A7
A8
A9
V3_3
/
DS2156DK02A0
STEVE SCULLY
10/04/02
10 13
1
TP24
1
TP25
1
TP26
1
TP27
1
TP28
1
TP29
1
TP23
1
TP30
1
TP33
1
TP38
1
TP37
1
TP36
1
TP35
1
TP34
1
TP32
1
TP31
2
1
C35
1
2
C36
2
1
C31
2
1
C32
2
1
C33
2
1
C34
2
1
C1
2
1
C22
2
1
C29
2
1
C30
2
1
C11
2
1
C10
2
1
C9
2
1
C8
2
1
C16
2
1
C15
2
1
C18
2
1
C19
2
1
C2
2
1
C4
2
1
C5
2
1
C3
2
1
C17
2
1
C12
2
1
C21
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
VCC
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
TP TP TP TP TP TP TP TP
TP TP TP TP TP TP TP TP
V3_3
/
13
11
10/04/02
DS2156DK02A0
STEVE SCULLY
22
77
23
15
9
8
30
31
29
51
37
14
52
48
47
32
43
38
42
39
35
34
49
50
41
40
46
53
33
24
20
19
18
16
100
98
93
94
95
17
91
86
90
87
96
99
78
79
97
85
74
89
88
82
6
92
1
28
27
26
55
21
12
5
2
10
7
4
25
54
36
76
84
80
60
45
83
81
61
44
65
64
63
62
59
58
57
56
75
11
3
73
72
71
70
69
68
67
66
13
1
RLINK
RSYNC
RSYSCLK
RDATA
RFSYNC
TCLK
TLINK
TSYNC
TSYSCLK
TLCLK
TDATA
TSSYNC
D_AD2
D_AD3
UOP3
UOP2
UOP1
UOP0
ESIBS1
ESIBS0
BPCLK
RMSYNC
A7
D_AD4
D_AD5
D_AD6
D_AD7
8XCLK
TTIP
LIUC
RCL
INT
A0
A1
D_AD0
CS
TCHBLK
RCHBLK
RPOSI
TSIG
TCHCLK
TRING
TPOSO
TCLKI
TCLKO
TNEGO
JTRST
JTDO
TPOSI
BTS
MUX
RSIG
RSER
TUSEL
TSER
ESIBRD
XTALD
N_P27
A4
A3
JTMS
JTDI
JTCLK
RLOS_LOTC
RNEGI
TNEGI
RCLKI
RPOSO
RNEGO
RCLKO
MCLK
RSIGF
TSTRST
RD_DS
WR_RW
N_P28
RRING
A2
D_AD1
RLCLK
RCHCLK
A5
A6
RCLK
RTIP
VALUE=NA
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
TQFP
DS2156
D/AD<2>
D/AD<3>
UOP3
UOP2
UOP1
UOP0
ESIBS<1>
ESIBS<0>
DVSS4
DVSS3
BPCLK
RMSYNC
ALE/AS/A<7>
D/AD<4>
D/AD<5>
D/AD<6>
D/AD<7>
TSYSCLK
TLCLK
8XCLK
TTIP
LIUC
RCL
INT*
A<0>
A<1>
D/AD<0>
CS*
TCHBLK
RCHBLK
TSSYNC
TDATA
TCLK
TLINK
RVDD
RPOSI
TESO
TSIG
TCHCLK
TSYNC
DVDD3
TRING
TPOSO
TCLKI
TCLKO
TNEGO
JTRST
JTDO
RVSS1
TVSS
TPOSI
RFSYNC
TVDD
DVDD1
DVDD2
DVSS1
DVSS2
BTS
MUX
RSIG
RSER
RVSS2
NC1
TSER
ESIBRD
XTALD
NC2
RDATA
A<4>
A<3>
JTMS
JTDI
JTCLK
RLOS/LOTC
RNEGI
TNEGI
RSYSCLK
RCLKI
RPOSO
RNEGO
RCLKO
MCLK
RSIGF
TSTRST
RD/DS*
WR/RW*
NC3
RRING
RVSS3
A<2>
D/AD<1>
RLCLK
RCHCLK
RSYNC
DVDD4
A<5>
A<6>
RLINK
RCLK
RTIP
V3_3
PPC_TXD 4C8<> 9A4<>
RCL 2C8> 11C7>
RDATA 2D6> 11D5>
PPC_TXCLK 4C8<> 9A4<>
NIMD11 4B2<>
NIMD12 4B2<>
NIMD13 4B2<>
NIMD14 4B2<>
NIMD15 4C2<>
N_P27 2A4< 11A4<
N_P28 2A3< 11A3<
PPC_RSYNC 4C8<> 9A4<>
PPC_RXCLK 4C8<> 9A4<>
PPC_RXD 4C8<> 9A4<>
PPC_TDM_EN 5C1<> 9A4<
PPC_TSYNC 4B8<> 9A4<>
NIMD10 4B2<>
NIMD9 4B2<>
NIMD8 4B2<>
RLCLK 2D6> 8B7> 11D5>
RFSYNC 2D6> 8C7> 11D5>
RESET_OUT 4B6<> 5B1<> 7B1<>
RD_DS 5C4<> 2A3< 11A3<
RCLKO 2C8> 8A7> 11C7>
RCLKI 8A7> 2C8< 5A8< 11C7<
RCLK 2D6> 9A6<> 9C1<> 9C1<> 9D1<> 11D6>
RCHCLK 2D6> 8D7> 11D5>
RCHBLK 2C3> 8D4> 11C3>
MUX 5C4<> 2A3< 5A8< 11A3<
MCLK 9B6<> 9C6<> 2A5< 11A5<
INT_INDICATOR 5A2<>
JTCLK 2A8< 11A7<
JTDI 2A8< 11A7<
JTDO 2A8> 11A7>
JTMS 2B8< 11B7<
A15 4B3<>
A14 4B3<>
A13 4B3<> 7B3<>
A10 4C3<> 7C3<>
D_AD2 2C3<> 4B6<> 5C1<> 11C3<>
D_AD3 2C3<> 4B6<> 5C1<> 11C3<>
D_AD4 2C3<> 4B6<> 5C1<> 11C3<>
D_AD5 2C3<> 4B6<> 5C1<> 11C3<>
D_AD6 2C3<> 4A6<> 5C1<> 11C3<>
D_AD7 2C3<> 4A6<> 5D1<> 11C3<>
ESIBRD 2A5<> 11A4<> 5A8<
ESIBS0 2A6<> 11A6<>
ESIBS1 2A6<> 11A5<>
INT 2C3> 4A8<> 5A2<> 11C3> 5A6<
JTRST 2B8< 5A8< 11A7<
LIUC 8B4> 2C8< 5A6< 11B7<
D_AD1 2C3<> 4B6<> 5C1<> 11B3<>
D_AD0 2B3<> 4B6<> 5C1<> 11B3<>
CS_T 4B8<> 5B1<> 7B3<>
CS 5B4<> 2C3< 11C3<
CLK16384_T 4B4<> 5D3<> 7B3<>
CLK2048 5D3<> 9B3<> 9B8<>
CLK1544_T 7B3<> 9D8<> 4B2<
BTS 5D4<> 2B3< 5A6< 11A3<
BP_EN 5C1<> 6B2< 6B6< 6C2< 6C6<
BPCLK 2A5> 8D4> 11A4>
A12 4C3<> 5C1<> 7B3<>
A11 4C3<> 5C1<> 7C3<>
SW4_B3EN 5B4<> 9B2<
TCHBLK 2D3> 8C4> 11C3>
TCHCLK 2D5> 11D4> 8A1<
TCK 5B8<> 5D8<
TCLK 9A6<> 9B6<> 9C3<> 9C6<> 2D5< 5A6<
TCLKI 8B4> 2B8< 5A8< 11B7<
TCLKO 2B8> 8A4> 11B7>
TDATA 2D5<> 11D4<>
TDI 5B8<> 5D7<
TDO 5B8<> 5C7<
TIM5V 4D3<> 4D8<>
TLCLK 2D5> 8C4> 11D4>
TLINK 8C4> 2D5< 5B6< 11D5<
TMS 5B8<> 5C7<
SW4_B2EN 5B4<> 9B2<
SW4_B1EN 5B4<> 9B3<
SW4_B0EN 5B4<> 9B3<
SW3_B3EN 5A3<> 9D1<
SW3_B2EN 5A3<> 9D1<
SW3_B1EN 5A3<> 9D3<
SW3_B0EN 5A3<> 9D3<
SW2_B3EN 5A3<> 9B6<
SW2_B2EN 5A3<> 9B6<
SW2_B1EN 5A3<> 9B8<
SW2_B0EN 5A3<> 9B8<
SW1_B3EN 5A3<> 9D6<
SW1_B2EN 5A3<> 9D6<
SW1_B1EN 5A4<> 9D8<
SW1_B0EN 5A4<> 9D8<
SNIM_B7 4C2<>
SNIM_B6 4C2<>
SNIM_B5 4C2<>
SNIM_B4 4C2<>
SNIM_B3 4C2<>
SNIM_B2 4C2<>
RXSOC 6B7<> 7B6<> 8D4> 8D5
RXPRTY 6B5<>
RXENB 7A6<> 8D5
RXENA 6A2<> 8D4>
RXDATA_7 6B2<> 7C8<> 8A7> 8A8
RXDATA_6 6B7<> 7C6<> 8A7> 8A8
RXDATA_5 6B2<> 7C8<> 8A7> 8A8
RXDATA_4 6B7<> 7C6<> 8A7> 8A8
RXDATA_3 6B2<> 7C6<> 8B7> 8B8
RXDATA_2 6B7<> 7C8<> 8B7> 8B8
RXDATA_1 6A2<> 7C6<> 8B7> 8B8
RXDATA_0 6B7<> 7C8<> 8B7> 8B8
RXCLAV_0 6A7<> 8C7>
RXCLAV0 7A8<> 8C8
RXA_4_RXCLAV_3 6A7<> 6B2<> 8C7>
RXA_3_RXCLAV_2 6A7<> 6C7<> 8C7>
RXA_2_RXCLAV_1 6A7<> 6B2<> 8D7>
RXA_1 6B7<> 8D7>
RXA_0 6B2<> 8D7>
RXADDR4 7B6<> 8C8
RXADDR3 7B8<> 8C8
RXADDR2 7B8<> 8D8
RXADDR1 7B6<> 8D8
RXADDR0 7B8<> 8D8
RW_T 4B6<> 5B1<> 7B1<>
RTIP 2C8< 3B8< 11C7<
RSYSCLK 9B6<> 9C3<> 9D6<> 2D6< 5A8< 11D5<
11D5<
5A6<
RSYNC 2D6<> 9A6<> 9B3<> 9C1<> 11D5<>A9 4B6<> 7B1<>
A8 4C6<> 7B1<>
8XCLK 2C8> 11C7>
A7 4C6<> 5C4<> 2B3< 11B3<
A6 4C6<> 5C4<> 2B3< 11B3<
A5 4C6<> 5C4<> 2B3< 11B3<
A4 4C6<> 5C4<> 2B3< 11B3<
A3 4C6<> 5C4<> 2B3< 11B3<
A2 4C6<> 5C4<> 2B3< 11B3<
A1 4C6<> 5C4<> 2B3< 11B3<
A0 4C6<> 5C4<> 2B3< 11B3<
*** Signal Cross-Reference for the entire design ***
RNEGO 2C8> 8A7> 11C7>
RPOSI 8B7> 2C8< 5A8< 11C7<
RPOSO 2C8> 8A7> 11C7>
RRING 2C8< 3B8< 11C7<
RSER 2A5> 8C7> 9A6<> 9B3<> 11A5>
RSIG 2A5> 8D7> 11A5>
RSIGF 2A5> 8D7> 11A4>
RNEGI 8B7> 2C8< 5A8< 11C7<
RMSYNC 2A5> 8C7> 11A5>
RLOS_LOTC_INDICATOR 5A2<>
RLOS_LOTC 2C3> 5B2<> 11C3>
RLINK 2D6> 8B7> 11D6>
UT_SOC 8B2
UT_ENB 8C2
UT_DATA7 8D2
UT_DATA5 8A5
UT_DATA4 8A5
UT_DATA3 8A5
UT_DATA2 8A5
UT_DATA0 8B5
UT_CLK 9B2<> 6C1< 7B4< 8A2<
UT_CLAV 8B4>
UT_ADDR4 8C5
UT_ADDR3 8C5
UT_ADDR1 8C5
UT_ADDR0 8D5
UR_SOC 8D5
UR_ENB 8D5
UR_DATA7 8A8
UR_DATA5 8A8
UR_DATA4 8A8
UR_DATA3 8B8
UR_DATA2 8B8
UR_DATA1 8B8
UR_DATA0 8B8
UR_CLAV 8C8
UR_ADDR4 8C8
UR_ADDR3 8C8
UR_ADDR2 8D8
UR_ADDR1 8D8
UR_ADDR0 8D8
UOP2 2A6> 11A5>
UOP1 2A6> 8C1> 11A5>
UOP0 2A6> 8B1> 11A5>
TXSOC 6C7<> 7B4<> 8B1> 8B2
TXPRTY 6C5<>
TXENABLE 7B4<> 8C2
TXDATA_7 6C2<> 7C5<> 8D1> 8D2
TXDATA_6 6C7<> 7C4<> 8D1> 8D2
TXDATA_5 6C2<> 7C5<> 8A4> 8A5
TXDATA_4 6C7<> 7C4<> 8A4> 8A5
TXDATA_3 6C2<> 7C4<> 8A4> 8A5
TXDATA_2 6C7<> 7C5<> 8A4> 8A5
TXDATA_0 6C7<> 7C5<> 8B4> 8B5
TXCLAV_0 6C7<> 8B5
TXCLAV0 7B5<> 8B5
TXA_4_TXCLAV_3 6C2<> 6C2<> 8C4>
TXA_3_TXCLAV_2 6C7<> 6C7<> 8C4>
TXA_2_TXCLAV_1 6B2<> 6C2<> 8C4>
TXA_0 6C2<> 8D4>
TXADDR4 7B4<> 8C5
TXADDR3 7B5<> 8C5
TXADDR2 7B4<> 8C5
TXADDR1 7B4<> 8C5
TXADDR0 7B5<> 8D5
TTIP 2B8> 11B7> 3C8<
TSYSCLK 8D1> 9B6<> 9D3<> 9D6<> 2D5< 5A8<
TSYNC 2D5<> 9A6<> 9B2<> 11D5<> 5A6<
TSTRST 2A5< 5A8< 11A4<
TSSYNC 9C3<> 2D5< 5B6< 8A1< 11D4<
TSIG 8D1> 2D5< 5B6< 11D4<
TSER 8A4> 9A6<> 9B2<> 2A5< 5A8< 11A4<
TRING 2B8> 11B7> 3C8<
TPOSO 2B8> 8A4> 11B7>
TPOSI 8C4> 2B8< 5A8< 11B7<
TNEGO 2B8> 8A4> 11B7>
TNEGI 8B4> 2B8< 5A8< 11B7<
11D4<
WR_RW 5C4<> 2A3< 11A3<
XTALD 2A5> 11A4>
TUSEL 5D2<> 2A4< 11A4<
TXA_1 6C7<> 8C4>
TXDATA_1 6C2<> 7C4<> 8B4> 8B5
TXENA 6C2<> 8C1>
UOP3 2A6> 8D4> 11A5>
UR_CLK 9B2<> 6A1< 7A8< 8A2<
UR_DATA6 8A8
UT_ADDR2 8C5
UT_DATA1 8B5
UT_DATA6 8D2
WE_T 4B6<> 5B1<> 7B1<>
/
STEVE SCULLY
DS2156DK02A0
10/04/02
12 13
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
J5 CONN_BNC_5PIN 3A3
J7 CONN_50P2 6D4
J8 CONN_50P2 4D3
JT10 CONN_10P 5C8
R1 RES1 4B2
R3 RES 3B7
R4 RES 6A2
R6 RES1 5A7
J4 CONN_BANTAM_IPC 3C1
J1 CONN_50P1 7D5
J2 CONN_50P1 7D7
J3 CONN_BANTAM_IPC 3B1
F6 FUSE 3A3
F5 FUSE 3D4
F4 FUSE 3C4
F3 FUSE 3D4
F2 FUSE 3B4
F1 FUSE 3B4
DS18 LED 5A3
DS17 LED 5B5
DS16 LED 5B5
DS15 LED 5A3
DS14 LED 5A3
DS13 LED 5A3
DS12 LED 5A3
DS11 LED 5A4
DS10 LED 5A3
DS9 LED 5A4
DS8 LED 5A4
DS7 LED 5A3
DS6 LED 5A4
DS5 LED 5A3
DS4 LED 6D5
DS3 LED 5A2
DS2 LED 5A2
DS1 LED 9B4
C36 CAP 10B6
C35 CAP 10B6
C34 CAP 10B5
C33 CAP 10B5
C32 CAP 10B5
C31 CAP 10B6
C30 CAP 10B4
C29 CAP 10B4
C27 CAP 3D5
C26 CAP 3A5
C25 CAP 3B5
C24 CAP 3C5
C23 CAP 3A6
C22 CAP 10B5
C21 CAP 10B2
C19 CAP 10B3
C18 CAP 10B3
C17 CAP 10B2
C16 CAP 10B3
C15 CAP 10B3
C14 CAP 8A1
C13 CAP 8A1
C12 CAP 10B2
TP6 TSTPNT_SNG 7B2
TP7 TSTPNT_SNG 7B2
TP8 TSTPNT_SNG 7B2
TP9 TSTPNT_SNG 7B2
TP10 TSTPNT_SNG 7B2
TP11 TSTPNT_SNG 7B2
TP12 TSTPNT_SNG 5D2
TP13 TSTPNT_SNG 5D2
TP14 TSTPNT_SNG 5A6
TP15 TSTPNT_SNG 5A6
TP16 TSTPNT_SNG 7B2
TP17 TSTPNT_SNG 5D2
TP18 TSTPNT_SNG 5A6
TP20 TSTPNT_SNG 7B2
TP21 TSTPNT_SNG 7B1
TP5 TSTPNT_SNG 7C2
TP4 TSTPNT_SNG 7C2
TP3 TSTPNT_SNG 7B2
TP2 TSTPNT_SNG 7B2
TP1 TSTPNT_SNG 7B2
T1 XFMR_2IN_4OUT_U 3B5 3D5
SW1 SWITCH_DPDT_SLIDE_6P 3A6
RJ1 RJ48_CON 3C3
R61 RES1 5A7
R60 RES 3A5
R59 RES 3C7
R58 RES 3D7
R57 RES 3B6
R56 RES 3B5
R55 RES1 3B6
R54 RES1 3B6
R53 RES 5A3
R52 RES 5B4
R51 RES 5B4
R50 RES 5A3
R49 RES1 5A7
R48 RES1 5A6
R47 RES1 5A7
R46 RES1 5B7
R45 RES 5A3
R44 RES1 5A7
R43 RES 5A3
R42 RES 5A4
R41 RES 5A3
R40 RES 5A4
R39 RES 5A3
R38 RES 5A7
R37 RES1 5A6
R36 RES 5A3
R35 RES 5A3
R34 RES1 8A1
R33 RES1 8A1
R32 RES1 5A6
R31 RES 5A3
R30 RES 5A3
R29 RES1 5A6
R28 RES1 5A7
R27 RES1 5D8
R26 RES1 5D8
R25 RES1 5D7
R24 RES1 5B8
R23 RES1 5A7
R22 RES1 5A7
R21 RES1 7A8
R19 RES1 5A6C11 CAP 10B4
C10 CAP 10B4
C9 CAP 10B4
C8 CAP 10B4
C7 CAP 3D6
C5 CAP 10B2
C4 CAP 10B2
C3 CAP 10B2
C2 CAP 10B3
C1 CAP 10B5
1 DS2156_TQFP 11D7
*** Part Cross-Reference for the entire design ***
R12 RES 6D5
R13 RES1 5B6
R14 RES1 7B4
R15 RES1 5B6
R16 RES1 5A7
R17 RES1 5B6
R18 RES1 5A6
R11 RES1 5A2
R10 RES1 5A7
R9 RES1 5A7
R8 RES1 5A2
R7 RES 9B4
Z10 SIDACTOR_2 3B4
Z9 SIDACTOR_2 3C4
Z8 SIDACTOR_2 3A4
Z7 SIDACTOR_2 3C4
Z6 SIDACTOR_2 3A4
Z4 SIDACTOR_2 3B5
Z3 SIDACTOR_2 3A5
Z2 SIDACTOR_2 3D5
Z1 SIDACTOR_2 3C4
U11 DS2156_TQFP 2D7
U10 IDTQS3125_U 9B7
U8 IDTQS3125_U 9D7
U7 IDTQS3125_U 9D3
U6 IDTQS3R861_U 9B5
U5 XILINX_XC9572XL 5D4 5D7
U3 IDTQS3R861_U 6B6
U2 IDTQS3R861_U 6D3
U1 IDTQS3R861_U 6B3
TP38 TSTPNT_SNG 10A5
TP36 TSTPNT_SNG 10A5
TP35 TSTPNT_SNG 10A5
TP34 TSTPNT_SNG 10A5
TP33 TSTPNT_SNG 10A5
TP31 TSTPNT_SNG 10A4
TP30 TSTPNT_SNG 10A7
TP29 TSTPNT_SNG 10A7
TP27 TSTPNT_SNG 10A7
TP26 TSTPNT_SNG 10A7
TP24 TSTPNT_SNG 10A8
TP23 TSTPNT_SNG 10A7
TP22 TSTPNT_SNG 7B1
TP25 TSTPNT_SNG 10A7
TP28 TSTPNT_SNG 10A7
TP32 TSTPNT_SNG 10A4
TP37 TSTPNT_SNG 10A5
U4 IDTQS3R861_U 6D6
U9 IDTQS3125_U 9B3
Z5 SIDACTOR_2 3C6
R5 RES 6C2
R2 RES 3B7
L1 CHOKE_DUAL_T1 3B4 3C4
J9 CONN_50P2 4D7
J6 CONN_BNC_5PIN 3D2
/
STEVE SCULLY
DS2156DK02A0
10/04/02
13 13
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
