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FSL206MR Green Mode Fairchild Power Switch (FPSTM) Features Description Internal Avalanche-Rugged SenseFET: 650V No Need for Auxiliary Bias Winding The FSL206MR integrated Pulse-Width Modulator (PWM) and SenseFET is specifically designed for highperformance offline Switched-Mode Power Supplies (SMPS) while minimizing external components. This device integrates high-voltage power regulators that combine an avalanche-rugged SenseFET with a Current-Mode PWM control block. Precision Fixed Operating Frequency: 67kHz No-Load <150mW at 265VAC without Bias Winding; <25mW with Bias Winding for FSL206MR, <30mW with Bias Winding for FSL206MRBN Frequency Modulation for Attenuating EMI Line Under-Voltage Protection (LUVP) Pulse-by-Pulse Current Limiting Low Under-Voltage Lockout (UVLO) Ultra-Low Operating Current: 300A Built-In Soft-Start and Startup Circuit Various Protections: Overload Protection (OLP), Over-Voltage Protection (OVP), Thermal Shutdown (TSD), Abnormal Over-Current Protection (AOCP) Auto-Restart Mode for All Protections Applications SMPS for STB, DVD, and DVCD Player SMPS for Auxiliary Power The integrated PWM controller includes: a 7.8V regulator, eliminating the need for auxilliary bias winding; Under-Voltage Lockout (UVLO) protection; Leading-Edge Blanking (LEB); an optimized gate turnon/turn-off driver; EMI attenuator; Thermal Shutdown (TSD) protection; temperature-compensated precision current sources for loop compensation; soft-start during startup; and fault-protection circuitry such as Overload Protection (OLP), Over-Voltage Protection (OVP), Abnormal Over-Current Protection (AOCP), and Line Under-Voltage Protection (LUVP). The internal high-voltage startup switch and the BurstMode operation with very low operating current reduce the power loss in Standby Mode. As a result, it is possible to reach a power loss of 150mW with no bias winding and 25mW (for FSL206MR) or 30mW (for FSL206MRBN) with a bias winding under no-load conditions when the input voltage is 265VAC. Related Resources Fairchild Power Supply WebDesigner - Flyback Design and Simulation - In Minutes at No Expense AN-4137 -- Design Guidelines for Offline Flyback Converters Using FPSTM AN-4141 -- Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147 -- Design Guidelines for RCD Snubber of Flyback AN-4150 -- Design Guidelines for Flyback Converters Using FSQ-Series Fairchild Power Switch (FPSTM) (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) September 2012 Output Power Table(1) Part Number Operating Top Mark Temperature FSL206MRN -40 ~ 115C FSL206MRL FSL206MRBN FSL206MR 230VAC 85 ~ Packing (2) 15% 265V AC Method Current RDS(ON),MAX Limit Open Open Frame(3) Frame(3) PKG 8-DIP Rail 8-LSOP L206MRB 0.6A 19 12W 7W 8-DIP Notes: 1. The junction temperature can limit the maximum output power. 2. 230VAC or 100/115VAC with doubler. The maximum power with CCM operation. 3. Maximum practical continuous power in an open-frame design at 50C ambient. Application Diagram AC IN AC IN DC OUT VSTR LS VFB DC OUT VSTR Drain LS PWM VCC VFB GND (a) With Bias Winding Drain PWM VCC GND FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Ordering Information (b) Without Bias Winding Figure 1. Typical Application Internal Block Diagram Figure 2. (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 Internal Block Diagram www.fairchildsemi.com 2 Figure 3. Pin Configuration Pin Definitions Pin # Name 1 GND Ground. SenseFET source terminal on primary side and internal control ground. VCC Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (VSTR) via an internal switch during startup (see Internal Block Diagram section). It is not until VCC reaches the UVLO upper threshold (8V) that the internal startup switch opens and device power is supplied via the auxiliary transformer winding. 3 VFB Feedback Voltage. Non-inverting input to the PWM comparator, with a 0.11mA current source connected internally and a capacitor and opto-coupler typically connected externally. There is a delay while charging external capacitor CFB from 2.4V to 5V using an internal 2.7A current source. This delay prevents false triggering under transient conditions, but allows the protection mechanism to operate under true overload conditions. 4 LS Line Sense Pin. This pin is used to protect the device when the input voltage is lower than the rated input voltage range. If this pin is not used, connect to ground. 5 VSTR Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and charges an external storage capacitor placed between the VCC pin and ground. Once VCC reaches 8V, all internal blocks are activated. After that, the internal highvoltage regulator (HV REG) turns on and off irregularly to maintain VCC at 7.8V. 6, 7, 8 Drain Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance. 2 Description (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Pin Configuration www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25C unless otherwise specified. Symbol Parameter Min. Max. Unit VSTR VSTR Pin Voltage -0.3 650.0 V VDS Drain Pin Voltage -0.3 650.0 V VCC Supply Voltage 26 V VLS LS Pin Voltage -0.3 Internally Clamped Voltage(4) V VFB Feedback Voltage Range -0.3 Internally Clamped Voltage(4) V IDM Drain Current Pulsed(5) 1.5 A (6) EAS Single-Pulsed Avalanche Energy 11 mJ PD Total Power Dissipation 1.3 W TJ Operating Junction Temperature +150 C TA TSTG ESD -40 Operating Ambient Temperature -40 +125 C Storage Temperature -55 +150 C Human Body Model, JESD22-A114 4 Charged Device Model, JESD22-C101 2 KV Notes: 4. VFB is clamped by internal clamping diode (13V ICLAMP_MAX < 100A). After shutdown, before VCC reaching VSTOP, VSD < VFB < VCC. 5. Repetitive rating: pulse-width limited by maximum junction temperature. 6. L=21mH, starting TJ=25C. FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Absolute Maximum Ratings Thermal Impedance TA=25C unless otherwise specified. Symbol JA Parameter (7) Junction-to-Ambient Thermal Impedance Value Unit 93 C/W Notes: 7. JEDEC recommended environment, JESD51-2 and test board, JESD51-10 with minimum land pattern for 8DIP and JESD51-3 with minimum land pattern for 8LSOP. (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com 4 TA = 25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit SenseFET Section BVDSS Drain-Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current VCC = 0V, ID = 250A 650 V VDS = 650V, VGS = 0V (8) VDS = 520V, VGS = 0V, TA = 125C 50 A 250 A 19 Drain-Source On-State Resistance(9) VGS = 10V, ID = 0.3A 14 CiSS Input Capacitances VGS = 0V, VDS = 25V, f = 1MHz 162 COSS Output Capacitance VGS = 0V, VDS = 25V, f = 1MHz 14.9 pF CRSS Reverse Transfer Capacitance VGS = 0V, VDS = 25V, f = 1MHz 2.7 pF tr Rise Time VDS = 325V, ID = 0.5A, RG = 25 6.1 ns tf Fall Time VDS = 325V, ID = 0.5A, RG = 25 43.6 ns RDS(ON) pF Control Section fOSC fOSC Switching Frequency VFB = 4V, VCC = 10V Switching Frequency Variation 61 -25C < TJ < 85C (8) 67 73 KHz 5 10 % fM Frequency Modulation DMAX Maximum Duty Cycle VFB = 4V, VCC = 10V 66 72 78 % DMIN Minimum Duty Cycle VFB = 0V, VCC = 10V 0 0 0 % VFB = 0V, VCC Sweep 7 8 9 V VSTART VSTOP 3 UVLO Threshold Voltage KHz After Turn On 6 7 8 V IFB Feedback Source Current VFB= 0V, VCC = 10V 90 110 130 A tS/S Internal Soft-Start Time VFB = 4V, VCC = 10V 10 15 20 ms FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Electrical Characteristics Burst Mode Section VBURH Burst-Mode HIGH Threshold Voltage VCC = 10V, VFB Increase FSL206MR 0.66 0.83 1.00 V FSL206MRB 0.40 0.50 0.60 V VBURL Burst-Mode LOW Threshold Voltage VCC = 10V, VFB Decrease FSL206MR 0.59 0.74 0.89 V FSL206MRB 0.28 0.35 0.42 HYSBUR Burst-Mode Hysteresis V FSL206MR 90 mV FSL206MRB 150 mV Protection Section ILIM Peak Current Limit tCLD Current Limit Delay(8) VSD Shutdown Feedback Voltage IDELAY tLEB VFB = 4V, di/dt = 300mA/s, VCC = 10V 0.54 VCC = 10V 4.5 5.0 5.5 V VFB = 4V 2.1 2.7 3.3 A 0.60 0.66 100 Shutdown Delay Current (8) Leading-Edge Blanking Time ns 250 (8) A ns VAOCP Abnormal Over-Current Protection VOVP Over-Voltage Protection VFB = 4V, VCC Increase 23.0 24.5 26.0 V VLS_OFF Line-Sense Protection On to Off VFB = 3V, VCC = 10V, VLS Decrease 1.9 2.0 2.1 V VLS_ON Line-Sense Protection Off to On VFB = 3V, VCC = 10V, VLS Increase TSD HYSTSD 0.7 Thermal Shutdown Temperature(8) TSD Hysteresis Temperature(8) V 1.4 1.5 1.6 V 125 135 150 C 60 C Continued on the following page... (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com 5 TA = 25C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units High Voltage Regulator Section VHVR HV Regulator Voltage VFB = 0V, VSTR = 40V 7.8 V Total Device Section IOP1 Operating Supply Current (Control Part Only, without Switching) VCC = 15V, 0V<VFB<VBURL 0.3 0.5 mA IOP2 Operating Supply Current (Control Part Only, without Switching) VCC = 8V, 0V<VFB<VBURL 0.25 0.45 mA IOP3 Operating Supply Current (While Switching) 1.3 mA ICH (8) VCC = 15V, VBURL<VFB<VSD Startup Charging Current VCC = 0V, VSTR > 40V 1.9 2.2 mA ISTART Startup Current VCC = Before VSTART, VFB = 0V 100 150 A VSTR Minimum VSTR Supply Voltage VCC = VFB = 0V, VSTR Increase 26 Notes: 8. Though guaranteed by design, not 100% tested in production. 9. Pulse test: pulse width=300ms, duty cycle=2%. (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 1.6 V FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Electrical Characteristics (Continued) www.fairchildsemi.com 6 HV Regulator Voltage (V HVR) Operating Frequency (fOSC) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 40 Figure 4. 25 0 25 50 75 90 40 110 115 Operating Frequency vs. Temperature Figure 5. 25 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0 25 50 75 90 40 110 Figure 6. Start Threshold Voltage vs. Temperature 25 Feedback Source Current (IFB) 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0 25 50 75 90 40 110 Figure 8. Feedback Source Current vs. Temperature (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 90 110 0 25 50 75 90 110 Peak Current Limit (ILIM) 1.4 25 75 Figure 7. Stop Threshold Voltage vs. Temperature 1.4 40 50 Stop Theshold Voltage (VSTOP) 1.4 25 25 HV Regulator Voltage vs. Temperature Start Theshold Voltage (VSTART) 1.4 40 0 FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Typical Performance Characteristics Figure 9. 25 0 25 50 75 90 110 Peak Current Limit vs. Temperature www.fairchildsemi.com 7 Startup Charging Current (ICH) Operating Supply Current (Iop1) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 40 25 0 25 50 75 90 40 110 25 0 25 50 75 90 110 Figure 10. Startup Charging Current vs. Temperature Figure 11. Operating Supply Current 1 vs. Temperature Operating Supply Current (Iop2) OverVoltage Protection (VOVP) 1.4 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 40 25 0 25 50 75 90 110 40 Figure 12. Operating Supply Current 2 vs. Temperature 25 0 25 50 75 90 FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Typical Performance Characteristics (Continued) 110 Figure 13. Over-Voltage Protection Voltage vs. Temperature Suntdown Delay Current (IDELAY) 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 40 25 0 25 50 75 90 110 Figure 14. Shutdown Delay Current vs. Temperature (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com 8 Startup Feedback Control At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (CA) connected to the VCC pin, as illustrated in Figure 15. An internal high-voltage regulator (HV REG) located between the VSTR and VCC pins regulates the VCC to 7.8V and supplies operating current. Therefore, FSL206MR needs no auxiliary bias winding. FSL206MR employs Current-Mode control, as shown in Figure 17. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5V; the optocoupler LED current increases, feedback voltage VFB is pulled down, and the duty cycle is reduced. This typically occurs when input voltage is increased or output load is decreased. VDC,link VSTR 2 VCC 3 7.8V ICH HV/REG ISTART CA VREF Figure 15. UVLO Startup Block Oscillator Block The oscillator frequency is set internally and the FPSTM has a random frequency fluctuation function. Fluctuation of the switching frequency can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the range of the frequency variation. The range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of an external feedback voltage and internal free-running oscillator. This randomly chosen switching frequency effectively spreads the EMI noise near switching frequency and allows the use of a cost-effective inductor instead of an AC input line filter to satisfy world-wide EMI requirements. Figure 17. Pulse-Width-Modulation (PWM) Circuit Leading-Edge Blanking (LEB) At the instant the internal SenseFET is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically cause a high-current spike through the SenseFET. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in the Current-Mode PWM control. To counter this effect, the FPS employs a leading-edge blanking (LEB) circuit (see Figure 17). This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. Protection Circuits Figure 16. Frequency Fluctuation Waveform (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Line Under-Voltage Protection (LUVP), Abnormal Over-Current Protection (AOCP), and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC reaches the UVLO stop voltage VSTOP (7V), the protection is reset and the internal highvoltage current source charges the VCC capacitor via the VSTR pin. When VCC reaches the UVLO start voltage VSTART (8V), the FPS resumes normal operation. In this manner, auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. www.fairchildsemi.com FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Functional Description Abnormal Over-Current Protection (AOCP) When the secondary rectifier diodes or the transformer pin are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the LEB time. Even though the FPS has overload protection, it is not enough to protect the FPS in that abnormal case, since severe current stress is imposed on the SenseFET until OLP triggers. The FPS includes the internal AOCP (Abnormal Over-Current Protection) circuit shown in Figure 20. When the gate turn-on signal is applied to the power sense, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing-resistor voltage is greater than the AOCP level, the set signal is applied to the latch, resulting in the shutdown of the SMPS. Figure 18. Auto-Restart Protection Waveforms Overload Protection (OLP) Overload is defined as the load current exceeding a preset level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS is operating normally, the overload protection (OLP) circuit can be activated during the load transition or startup. To avoid this undesired operation, the OLP circuit is activated after a specified time to determine whether it is a transient situation or a true overload situation. The Current-Mode feedback path limits the current in the SenseFET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (VO) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, increasing the feedback voltage (VFB). If VFB exceeds 2.4V, the feedback input diode is blocked and the 2.7A current source (IDELAY) starts to charge CFB slowly up. In this condition, VFB increases until it reaches 5V, when the switching operation is terminated, as shown in Figure 19. The shutdown delay is the time required to charge CFB from 2.4V to 5V with 2.7A current source. FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Figure 20. Abnormal Over-Current Protection Thermal Shutdown (TSD) The SenseFET and control IC being integrated makes it easier to detect the temperature of the SenseFET. When the junction temperature exceeds ~135C, thermal shutdown is activated and the FPS is restarted after temperature decreases to 60C. Over-Voltage Protection (OVP) In the event of a malfunction in the secondary-side feedback circuit or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero (refer to Figure 17). Then VFB climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is activated. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the overload protection is activated, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an over-voltage protection (OVP) circuit is employed. In general, VCC is proportional to the output voltage and the FPS uses VCC instead of directly monitoring the output voltage. If VCC exceeds 24.5V, OVP circuit is activated, resulting in termination of the switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed to be below 24.5V. Figure 19. Overload Protection (OLP) (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com 10 Burst Operation If the input voltage of the converter is lower than the minimum operating voltage, the converter input current increases too much, causing components failure. If the input voltage is low, the converter should be protected. In the FSL206MR, the LUVP circuit senses the input voltage using the LS pin and, if this voltage is lower than 1.5V, the LUVP signal is generated. The comparator has 0.5V hysteresis. If the LUVP signal is generated, the output drive block is shut down and the output voltage feedback loop is saturated. To minimize power dissipation in Standby Mode, the FPS enters Burst Mode. As the load decreases, the feedback voltage decreases. As shown in Figure 23, the device automatically enters Burst Mode when the feedback voltage drops below VBURH. Switching continues until the feedback voltage drops below VBURL. At this point, switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH, switching resumes. The feedback voltage then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET and reduces switching loss in Standby Mode. VO Voset VFB Figure 21. Line UVP Circuit VBURH VBURL Soft-Start The FSL206MR has an internal soft-start circuit that slowly increases the feedback voltage, together with the SenseFET current, after it starts. The typical soft-start time is 15ms, as shown in Figure 22, where progressive increments of the SenseFET current are allowed during the startup phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps prevent transformer saturation and reduce the stress on the secondary diode. IDS VDS time t1 Figure 23. Figure 22. FSL206MR -- Green Mode Fairchild Power Switch (FPSTM) Line Under-Voltage Protection (LUVP) Switching disabled t2 t3 Switching disabled t4 Burst-Mode Operation Internal Soft-Start (c) 2011 Fairchild Semiconductor Corporation FSL206MR * Rev. 1.0.5 www.fairchildsemi.com 11 10.00 9.10 0.56 0.36 8 A 7.62 2.54 B 5 6.60 9.90 6.20 9.30 4 1 0.56 1.62 1.47 TOP VIEW 3.60 3.20 0.10 MIN 1.09 0.94 0.56 0.36 10.70 1.252 1.784 LAND PATTERN RECOMMENDATION 7.62 A 3.70 MAX 0.10 C 2.54 C 7.62 FRONT VIEW 0.35 0.20 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A. NO INDUSTRY STANDARD APPLIES TO THIS PACKAGE R0.20 B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, R0.20 MOLD FLASH, AND TIE BAR EXTRUSIONS GAGE PLANE D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-2009 8 E. DRAWING FILENAME: MKT-MLSOP08Arev2 0 9 0.25 SEATING PLANE 6.70 0.10 M C B A 0.10 M C B A 2.00 3 DETAIL A SCALE 2:1 1.12 0.72 1.60 REF [ 0.400 10.160 0.355 9.017 8 ] 5 [ 0.280 7.112 0.240 6.096 1 HALF LEAD STYLE 4X 0.031 [0.786] MIN MAX 0.210 [5.334] ] 4 FULL LEAD STYLE 4X 0.010 [0.252] MIN 0.195 4.965 0.115 2.933 [ ] [ 0.325 8.263 0.300 7.628 ] SEATING PLANE [ 0.150 3.811 0.115 2.922 ] C MIN 0.015 [0.381] 0.100 [2.540] (0.031 [0.786]) 4X [ ] 0.10 C 0.022 0.562 0.014 0.358 0.300 [7.618] 0.430 [10.922] MAX [ 0.070 1.778 0.045 1.143 FOR 1/2 LEAD STYLE ] 4X 8X FOR FULL LEAD STYLE NOTES: A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA WHICH DEFINES 2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE. B) CONTROLING DIMS ARE IN INCHES C) DIMENSION S ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSION S AND TOLERANCES PER ASME Y14.5M-2009 E) DRAWING FILENAME AND REVSION: MKT-N08MREV2. 0.015 [0.389] GAGE PLANE PIN 1 INDICATOR 9.83 9.00 8 5 6.670 6.096 1 4 8.255 7.610 TOP VIEW 1.65 1.27 (0.56) 7.62 3.683 3.200 5.08 MAX 3.60 3.00 0.33 MIN 0.560 0.355 2.54 0.356 0.200 7.62 9.957 7.870 FRONT VIEW SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS-001, VARIATION BA B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-2009 E. DRAWING FILENAME: MKT-N08Frev3 15 0 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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