Low Capacitance, Low Charge Injection, 15 V/+12 V iCMOS(R) Dual SPST Switches ADG1221/ADG1222/ADG1223 FEATURES FUNCTIONAL BLOCK DIAGRAM ADG1221 ADG1222 S1 S1 IN1 IN1 D1 D1 D2 IN2 S2 D2 IN2 S2 ADG1223 APPLICATIONS S1 IN1 Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems D1 D2 IN2 S2 06574-001 <0.5 pC charge injection over full signal range Off capacitance: 2 pF Off leakage: 20 pA Supply range: 33 V On resistance: 120 Fully specified at 15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 10-lead MSOP package SWITCHES SHOWN FOR A LOGIC 0 INPUT Figure 1. GENERAL DESCRIPTION 0.5 0.4 TA = 25C VDD = +15V VSS = -15V 0.3 0.2 0.1 0 VDD = 12V VSS = 0V -0.1 -0.2 -0.3 VDD = +5V VSS = -5V -0.4 The ADG1221/ADG1222/ADG1223 contain two independent single-pole/single-throw (SPST) switches. The ADG1221 and ADG1222 differ only in that the digital control logic is inverted. The ADG1221 switches are turned on with Logic 1 on the appropriate control input, and Logic 0 is required for the -0.5 -15 -10 -5 06574-041 The ultralow capacitance and exceptionally low charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the full signal range of the device. ADG1222. The ADG1223 has one switch with digital control logic similar to that of the ADG1221; the logic is inverted on the other switch. The ADG1223 exhibits break-before-make switching action for use in multiplexer applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. CHARGE INJECTION (pC) The ADG1221/ADG1222/ADG1223 are monolithic, complementary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS (industrial CMOS) process. iCMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs, capable of 33 V operation, in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. 0 5 10 15 INPUT VOLTAGE (V) Figure 2. Charge Injection vs. Input Voltage Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2009 Analog Devices, Inc. All rights reserved. ADG1221/ADG1222/ADG1223 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Terminology .......................................................................................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Test Circuits ..................................................................................... 13 Dual Supply ................................................................................... 3 Outline Dimensions ....................................................................... 15 Single Supply ................................................................................. 4 Ordering Guide .......................................................................... 15 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY 3/09--Rev. 0 to Rev. A Changes to Power Requirements, IDD, Digital Inputs = 5 V Parameter, Table 1............................................................................. 4 Changes to tON Parameter and Power Requirements, IDD, Digital Inputs = 5 V Parameter, Table 2...................................................... 5 2/07--Rev. 0: Initial Version Rev. A | Page 2 of 16 ADG1221/ADG1222/ADG1223 SPECIFICATIONS DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C Temperature -40C to +85C -40C to +125C VDD to VSS Unit V VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -1 mA (see Figure 23) 120 200 240 270 typ max VS = 10 V, IS = -1 mA On Resistance Match Between Channels, RON 2.5 6 10 12 typ max 83 typ max On Resistance Flatness, RFLAT(ON) VS = -5 V/0 V/+5 V; IS = -1 mA 20 64 76 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V (see Figure 24) 0.002 0.1 0.6 1 nA typ nA max 1 nA typ nA max 1 nA typ nA max 2.0 0.8 V min V max 0.1 A typ A max pF typ Drain Off Leakage, ID (Off ) VS = 10 V, VD = 10 V (see Figure 24) 0.002 0.1 0.6 Channel On Leakage, ID, IS (On) VS = VD = 10 V (see Figure 25) 0.01 0.2 0.6 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH VIN = VINL or VINH 0.005 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON 2.5 RL = 300 , CL = 35 pF, VS = 10 V (see Figure 26) 130 170 210 240 ns typ ns max tOFF RL = 300 , CL = 35 pF, VS = 10 V (see Figure 26) 85 105 130 140 ns typ ns max Break-Before-Make Time Delay (ADG1223 Only), tBBM RL = 300 , CL = 35 pF, VS1 = VS2 = 10 V (see Figure 27) 40 10 Charge Injection, QINJ Off Isolation Test Conditions/Comments 0.1 75 Rev. A | Page 3 of 16 ns typ ns min pC typ dB typ VS = 0 V, RS = 0 , CL = 1 nF (see Figure 28) RL = 50 , CL = 1 pF, f = 1 MHz (see Figure 29) ADG1221/ADG1222/ADG1223 Parameter Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise, THD + N -3 dB Bandwidth CS (Off ) 25C 90 Temperature -40C to +85C -40C to +125C Unit dB typ 0.15 % typ 960 MHz typ 1.7 2.2 pF typ pF max 1.7 2.2 pF typ pF max 3 4 pF typ pF max CD (Off ) RL = 50 , CL = 1 pF (see Figure 31) VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz CD, CS (On) VS = 0 V, f = 1 MHz POWER REQUIREMENTS IDD VDD = +16.5 V, VSS = -16.5 V 0.001 190 A typ A max A typ A max 1.0 5/16.5 A typ A max V min/max 1.0 140 ISS 0.001 VDD/VSS 1 Test Conditions/Comments RL = 50 , CL = 1 pF, f = 1 MHz (see Figure 30) RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Digital inputs = 0 V, 5 V, or VDD GND = 0 V Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C Temperature -40C to +85C -40C to +125C 0 V to VDD Unit V VDD = 10.8 V, VSS = 0 V, VS = 0 V to 10 V, IS = -1 mA (see Figure 23) 300 475 567 625 typ max VS = 0 V to 10 V, IS = -1 mA On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Test Conditions/Comments 4.5 16 60 0.002 0.1 26 0.6 27 1 typ max typ VS = 3 V/6 V/9 V, IS = -1 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V (see Figure 24) nA typ nA max Drain Off Leakage, ID (Off ) VS = 1 V/10 V, VD = 10 V/1 V (see Figure 24) 0.002 0.1 0.6 1 Rev. A | Page 4 of 16 nA typ nA max ADG1221/ADG1222/ADG1223 Parameter Channel On Leakage, ID, IS (On) 25C Temperature -40C to +85C -40C to +125C Unit 0.01 0.2 0.6 1 nA typ nA max 2.0 0.8 V min V max 0.1 A typ A max pF typ DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH VIN = VINL or VINH 0.001 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON 3 RL = 300 , CL = 35 pF, VS = 8 V (see Figure 26) 190 250 300 345 ns typ ns max tOFF RL = 300 , CL = 35 pF, VS = 8 V (see Figure 26) 120 150 190 225 ns typ ns max Break-Before-Make Time Delay (ADG1223 Only), tBBM RL = 300 , CL = 35 pF, VS1 = VS2 = 8 V (see Figure 27) 70 Charge Injection, QINJ 0.2 ns typ ns min pC typ Off Isolation 75 dB typ Channel-to-Channel Crosstalk 90 dB typ -3 dB Bandwidth CS (Off ) 550 MHz typ 2.1 2.6 pF typ pF max 2.1 2.6 pF typ pF max 3.8 4.6 pF typ pF max 0.001 A typ A max A typ A max V min/max 10 CD (Off ) VS = 6 V, f = 1 MHz 1.0 140 VDD 1 VS = 6 V, RS = 0 , CL = 1 nF (see Figure 28) RL = 50 , CL =1 pF, f = 1 MHz (see Figure 29) RL = 50 , CL = 1 pF, f = 1 MHz (see Figure 30) RL = 50 , CL = 1 pF (see Figure 31) VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz CD, CS (On) POWER REQUIREMENTS IDD Test Conditions/Comments VS = VD = 1 V or 10 V (see Figure 25) 190 5/16.5 Guaranteed by design, not subject to production test. Rev. A | Page 5 of 16 VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V VSS = 0 V, GND = 0 V ADG1221/ADG1222/ADG1223 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 3. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb free 1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA Table 4. Thermal Resistance Package Type 10-Lead MSOP (4-Layer Board) ESD CAUTION -40C to +125C -65C to +150C 150C 260C Overvoltages at IN, S, or D are clamped by internal diodes. Current must be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 16 JA 206 JC 44 Unit C/W ADG1221/ADG1222/ADG1223 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS S1 2 D1 3 D2 4 10 IN2 ADG1221/ ADG1222/ ADG1223 9 VDD 8 GND NC TOP VIEW S2 5 (Not to Scale) 6 VSS 7 NC = NO CONNECT 06574-002 IN1 1 Figure 3. 10-Lead MSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic IN1 S1 D1 D2 S2 VSS NC GND VDD IN2 Description Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. No Connect. Ground (0 V) Reference. Most Positive Power Supply Potential. Logic Control Input. Table 6. ADG1221/ADG1222 Truth Table ADG1221 INx 1 0 ADG1222 INx 0 1 Switch Condition On Off Switch 1 Condition Off On Switch 2 Condition On Off Table 7. ADG1223 Truth Table ADG1223 INx 0 1 Rev. A | Page 7 of 16 ADG1221/ADG1222/ADG1223 TERMINOLOGY tON The delay between applying the digital control input and the output switching on (see Figure 26). IDD The positive supply current. ISS The negative supply current. tOFF The delay between applying the digital control input and the output switching off (see Figure 26). VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. tBBM Off time or on time measured between the 90% points of both switches, when switching from one address state to another (ADG1223 only). RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. QINJ (Charge Injection) A measure of the glitch impulse transferred from the digital input to the analog output during switching. IS (Off) The source leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID (Off) The drain leakage current with the switch off. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID, IS (On) The channel leakage current with the switch on. -3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. VINL The maximum input voltage for Logic 0. On Response The frequency response of the on switch. VINH The minimum input voltage for Logic 1. Insertion Loss The loss due to the on resistance of the switch. IINL (IINH) The input current of the digital input. THD + N (Total Harmonic Noise Plus Distortion) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. CIN The digital input capacitance. Rev. A | Page 8 of 16 ADG1221/ADG1222/ADG1223 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 180 VDD = +13.5V VSS = -13.5V 160 200 140 ON RESISTANCE () 120 100 VDD = +15V VSS = -15V 80 VDD = +16.5V VSS = -16.5V 60 40 TA = +125C 150 TA = +85C 100 TA = +25C TA = -40C 06574-003 50 20 0 -18 -15 -12 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 0 -15 18 Figure 4. On Resistance as a Function of VS (VD), Dual Supply 06574-006 ON RESISTANCE () VDD = +15V VSS = -15V TA = 25C -10 -5 0 5 SOURCE OR DRAIN VOLTAGE (V) 15 Figure 7. On Resistance as a Function of VS (VD) for Different Temperatures, Dual Supply 450 600 TA = 25C VDD = 12V VSS = 0V 400 TA = +125C 500 350 TA = +85C VDD = +5.5V VSS = -5.5V 300 ON RESISTANCE () ON RESISTANCE () 10 250 200 150 400 300 200 TA = -40C 100 TA = +25C 50 0 -5 -4 -3 -2 -1 0 1 2 3 SOURCE OR DRAIN VOLTAGE (V) 4 0 5 06574-007 06574-004 100 0 Figure 5. On Resistance as a Function of VS (VD), Dual Supply 10 12 200 VDD = 12V VSS = 0V 100 LEAKAGE CURRENT (pA) VDD = 10.8V VSS = 0V 350 300 250 VDD = 13.2V VSS = 0V 200 150 100 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 0 -50 -100 -150 -200 -250 -300 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -400 -450 12 Figure 6. On Resistance as a Function of VS (VD), Single Supply 50 -350 06574-005 50 0 VDD = +15V VSS = -15V VBIAS = 10V 150 400 0 20 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 40 60 80 TEMPERATURE (C) 06574-018 TA = 25C ON RESISTANCE () 4 6 8 SOURCE OR DRAIN VOLTAGE (V) Figure 8. On Resistance as a Function of VS (VD) for Different Temperatures, Single Supply 450 0 2 100 120 Figure 9. Leakage Current as a Function of Temperature, Dual Supply Rev. A | Page 9 of 16 ADG1221/ADG1222/ADG1223 0.5 150 VDD = +5V VSS = -5V VBIAS = 4.5V 0.4 CHARGE INJECTION (pC) 0 -50 -100 -150 -250 0 40 0.2 0.1 0 -0.2 80 60 TEMPERATURE (C) 100 -0.5 -15 120 -5 0 5 10 15 Figure 13. Charge Injection vs. Input Voltage 300 VDD = 12V VSS = 0V VBIAS = 1/10V 250 15V DS tOFF 15V DS tON 12V SS t OFF 12V SS t ON 150 200 TIME (ns) 100 50 0 -50 0 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 20 40 50 80 60 TEMPERATURE (C) 100 120 0 -40 06574-045 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -150 -200 150 100 -100 06574-019 LEAKAGE CURRENT (pA) -10 INPUT VOLTAGE (V) 300 200 VDD = +5V VSS = -5V -0.4 Figure 10. Leakage Current as a Function of Temperature, Dual Supply 250 VDD = 12V VSS = 0V -0.1 -0.3 ID (OFF) + - ID (OFF) - + ID, IS (ON) - - 20 VDD = +15V VSS = -15V 06574-041 IS (OFF) + - IS (OFF) - + ID, IS (ON) + + -200 TA = 25C 0.3 50 06574-020 LEAKAGE CURRENT (pA) 100 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 11. Leakage Current as a Function of Temperature, Single Supply Figure 14. tON/tOFF vs. Temperature 120 0 IDD PER CHANNEL TA = 25C -10 100 -20 -30 ISOLATION (dB) 60 VDD = +15V VSS = -15V 40 0 2 4 6 -50 -60 8 10 12 06574-025 -80 VDD = 12V VSS = 0V 20 -40 -70 06574-049 IDD (A) 80 0 VDD = +15V VSS = -15V TA = 25C -90 -100 10k 14 LOGIC LEVEL, INx (V) Figure 12. IDD vs. Logic Level 100k 1M 10M FREQUENCY (Hz) 100M Figure 15. Off Isolation vs. Frequency Rev. A | Page 10 of 16 1G ADG1221/ADG1222/ADG1223 0 0 -20 VDD = +15V VSS = -15V TA = 25C -10 -20 VDD = +15V VSS = -15V Vp-p = 0.63V TA = 25C NO DECOUPLING CAPS ON PSRR (dB) CROSSTALK (dB) -30 -40 -60 -80 -40 -50 -60 DECOUPLING CAPS ON -70 -80 -90 06574-021 -120 10k 100k 1M 10M FREQUENCY (Hz) 100M -100 100k 1G 10M 100M Figure 18. ACPSRR vs. Frequency 10 0 -4 1M FREQUENCY (Hz) Figure 16. Crosstalk vs. Frequency -2 06574-052 -100 LOAD = 10k TA = 25C VDD = +15V VSS = -15V TA = 25C 1 THD + N (%) -8 -10 -12 -14 VDD = +5V, VSS = -5V, VS = +3.5V rms VDD = +15V, VSS = -15V, VS = +5V rms -16 0.1 -18 -22 -24 10k 100k 1M 10M 100M FREQUENCY (Hz) 100M 1G 0.01 10 Figure 17. Insertion Loss vs. Frequency 100 1k FREQUENCY (Hz) 10k Figure 19. THD + N vs. Frequency Rev. A | Page 11 of 16 100k 06574-053 -20 06574-029 INSERTION LOSS (dB) -6 5.0 4.5 4.5 4.0 4.0 3.5 3.5 3.0 2.5 2.0 1.5 1.0 VDD = +15V VSS = -15V TA = 25C 0.5 0 -15 -10 0 5 10 3.5 3.0 2.5 2.0 1.5 2 SOURCE OFF DRAIN OFF SOURCE/DRAIN ON 4 6 8 10 06574-036 CAPACITANCE (pF) 4.0 0 -4 -3 SOURCE OFF DRAIN OFF SOURCE/DRAIN ON -2 -1 0 1 2 3 Figure 22. Capacitance vs. Bias Voltage 4.5 0 VDD = +5V VSS = -5V TA = 25C BIAS VOLTAGE (V) 5.0 VDD = 12V VSS = 0V TA = 25C 1.5 0 -5 15 Figure 20. Capacitance vs. Bias Voltage 0.5 2.0 0.5 BIAS VOLTAGE (V) 1.0 2.5 1.0 SOURCE OFF DRAIN OFF SOURCE/DRAIN ON -5 3.0 12 BIAS VOLTAGE (V) Figure 21. Capacitance vs. Bias Voltage Rev. A | Page 12 of 16 4 06574-037 CAPACITANCE (pF) 5.0 06574-035 CAPACITANCE (pF) ADG1221/ADG1222/ADG1223 5 ADG1221/ADG1222/ADG1223 TEST CIRCUITS Sx A Dx ID (OFF) A VS IDS 06574-009 IS (OFF) VD Figure 24. Test Circuit 2--Off Leakage V1 ID (ON) Dx 06574-008 RON = V1/IDS VD Figure 25. Test Circuit 3--On Leakage VSS 0.1F 0.1F VDD VSS Sx VS A NC = NO CONNECT Figure 23. Test Circuit 1--On Resistance VDD Dx ADG1222 50% 50% VIN ADG1221 50% 50% VOUT Dx CL 35pF RL 300 ADG1221/ ADG1222 INx VIN 90% VOUT 90% GND tOFF tON 06574-011 VS Sx NC 06574-010 Sx Figure 26. Test Circuit 4--Switching Times VDD VSS VS2 VSS S1 D1 S2 D2 CL 35pF RL 300 IN1, IN2 VOUT2 RL 300 CL 35pF VOUT1 VOUT1 VOUT2 ADG1223 50% 0V 50% 90% 90% 0V 90% 90% 0V tD GND tD 06574-012 VDD VS1 VIN 0.1F 0.1F Figure 27. Test Circuit 5--Break-Before-Make Time Delay VS VSS VDD VSS Sx INx VIN Dx ADG1221/ ADG1222 GND ADG1222 ON VOUT CL 1nF VIN ADG1221 VOUT QINJ = CL x VOUT Figure 28. Test Circuit 6--Charge Injection Rev. A | Page 13 of 16 OFF VOUT 06574-013 RS VDD ADG1221/ADG1222/ADG1223 VDD VSS 0.1F VDD VSS 0.1F 0.1F NETWORK ANALYZER VSS VDD Sx 50 50 INx VS VS VOUT Dx VIN VOUT OFF ISOLATION = 20 LOG VS INSERTION LOSS = 20 LOG VOUT RL 50 VOUT WITH SWITCH VOUT WITHOUT SWITCH VSS 0.1F VDD VDD VSS VSS 0.1F 0.1F S1 Dx VDD 50 AUDIO PRECISION RS 50 VSS S2 ADG1221/ADG1222/ GND ADG1223 CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VOUT VS INx Sx VS V p-p Dx 06574-015 VS VOUT Figure 31. Test Circuit 9--Bandwidth 0.1F NETWORK ANALYZER RL 50 ADG1221/ADG1222/ ADG1223 GND Figure 29. Test Circuit 7--Off Isolation VDD 50 06574-014 RL 50 ADG1221/ADG1222/ ADG1223 GND Sx INx Dx VIN NETWORK ANALYZER VSS 06574-016 VDD VIN Figure 30. Test Circuit 8--Channel-to-Channel Crosstalk ADG1221/ADG1222/ ADG1223 GND RL 10k VOUT Figure 32. Test Circuit 10--Total Harmonic Distortion + Noise Rev. A | Page 14 of 16 06574-017 0.1F ADG1221/ADG1222/ADG1223 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.23 0.08 8 0 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 33. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model ADG1221BRMZ1 ADG1221BRMZ-REEL71 ADG1222BRMZ1 ADG1222BRMZ-REEL71 ADG1223BRMZ1 ADG1223BRMZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) Z = Pb-free part. Rev. A | Page 15 of 16 Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding S27 S27 S28 S28 S2J S2J ADG1221/ADG1222/ADG1223 NOTES (c)2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06574-0-3/09(A) Rev. A | Page 16 of 16