2nd-Order
DS Modulator
CHA+
AVDD
CHA-
Output
Interface
Circuit
RC
Oscillator
20MHz
Out EN
Clock
Select
Divider
REFINA
Reference
Voltage
2.5V
REFOUT
OUTA
OUTB
CLKIN
AGND BGND
BVDD
CLKOUT
CLKSEL
2nd-Order
DS Modulator
CHB+
CHB-
REFINB
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
Two 1-Bit, 10MHz, 2nd-Order
Delta-Sigma Modulators
Check for Samples: ADS1209
1FEATURES DESCRIPTION
2• 16-Bit Resolution The ADS1209 is a two-channel, high-performance,
delta-sigma (ΔΣ) modulator with an 86dB dynamic
• 13-Bit Linearity range, operating from a single +5V supply. The
• ±2.3V Specified Input Voltage Range differential inputs are ideal for direct connection to
• Internal Reference Voltage: 2% signal sources in an industrial environment. With the
• Gain Error: 0.5% appropriate digital filter and modulator rate, the
device can be used to achieve 16-bit analog-to-digital
• Two Independent Delta-Sigma Modulators (A/D) conversion with no missing codes. Effective
• Two Input Reference Buffers accuracy of 14 bits can be obtained with a digital filter
• On-Chip Oscillator bandwidth of 20kHz at a modulator rate of 10MHz.
The ADS1209 is designed for use in high-resolution
• Selectable Internal or External Clock measurement applications including current
• Specified Temperature Range: measurements, industrial process control, and
–40°C to +105°C resolvers. It is available in a TSSOP-24 package and
• TSSOP-24 Package is specified for operation over the ambient
temperature range of –40°C to +105°C.
APPLICATIONS
• Motor Control
• Current Measurement
• Resolver
• Industrial Process Control
• Instrumentation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE TEMPERATURE TRANSPORT MEDIA,
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE ORDERING NUMBER QUANTITY
ADS1209SPW Tube, 60
ADS1209 TSSOP-24 PW –40°C to +105°C ADS1209SPWR Tape and Reel, 2000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating ambient temperature range, unless otherwise noted. ADS1209 UNIT
Supply voltage, AVDD to AGND –0.3 to 6 V
Supply voltage, BVDD to BGND –0.3 to 6 V
Analog input voltage AGND – 0.3 to AVDD + 0.3 V
Reference input voltage AGND – 0.3 to AVDD + 0.3 V
Digital input voltage BGND – 0.3 to BVDD + 0.3 V
Ground voltage difference, AGND to BGND ±0.3 V
Input current to any pin except supply ±10 mA
Operating virtual junction temperature range, TJ–40 to +150 °C
Operating ambient temperature range, TOA –40 to +125 °C
Human body model (HBM) JEDEC standard 22, test method A114-C.01 +2000 V
ESD ratings,
all pins Charged device model (CDM) JEDEC standard 22, test method C101 +500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
TA≤+25°C DERATING FACTOR TA= +70°C TA= +85°C TA= +105°C
PACKAGE POWER RATING ABOVE TA= +25°C(1) POWER RATING POWER RATING POWER RATING
TSSOP-24 1420mW 11.3mW/°C 909mW 738mW 511mW
(1) This is the inverse of the traditional junction-to-ambient thermal resistance (RqJA). Thermal resistances are not production tested and are
for informational purposes only.
THERMAL CHARACTERISTICS: TSSOP-24
Over the operating ambient temperature range of –40°C to +105°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RqJA Junction-to-air thermal resistance High-K thermal resistance(1) 88 °C/W
RqJC Junction-to-case thermal resistance 26 °C/W
PDDevice power dissipation CLKSEL = 0, 5V supply 100 mW
(1) Modeled in accordance with the High-K thermal definitions of EIA/JESD51-3.
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ADS1209
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SBAS491 –FEBRUARY 2010
RECOMMENDED OPERATING CONDITIONS
PARAMETER MIN NOM MAX UNIT
Supply voltage, AVDD to AGND 4.5 5 5.5 V
Low-voltage levels 2.7 3.0 3.6 V
Supply voltage, BVDD to BGND 5V logic levels 4.5 5 5.5 V
Reference input voltage, VREF 0.5 2.5 2.6 V
Operating common-mode signal 0 AVDD V
–0.92 × +0.92 ×
Analog inputs +IN – (–IN) V
VREF VREF
External clock(1) 16 20 24 MHz
Operating ambient temperature range, TOA –40 +125 °C
Specified ambient temperature range, TA–40 +105 °C
(1) With reduced accuracy, clock can go from 1MHz up to 33MHz; see Typical Characteristic curves.
ELECTRICAL CHARACTERISTICS
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
RESOLUTION 16 Bits
DC ACCURACY
VIN = ±2.3VPP –8 ±3.8 +8 LSB
INL Integral linearity error(2) VIN = ±2.0VPP –4 ±1.8 +4 LSB
Integral linearity match 1 4 LSB
DNL Differential nonlinearity –1 +1 LSB
VOS Input offset error –3 ±1.5 +3 mV
Input offset error match 0.2 2 mV
TCVOS Input offset error thermal drift –8 1 +8 mV/°C
GERR Gain error Referenced to VREFIN –0.5 ±0.02 +0.5 % FSR
Gain error match 0.1 0.5 % FSR
TCGERR Gain error thermal drift ±1.3 ppm/°C
PSRR Power-supply rejection ratio 4.5V < AVDD < 5.5V 82 dB
ANALOG INPUTS
Full-scale differential input voltage
FSR (CHx+) – (CHx–); CHx– = 2.5V –VREFIN +VREFIN V
range
Specified differential input voltage –0.92 × +0.92 ×
(CHx+) – (CHx–); CHx– = 2.5V V
range VREF VREF
Absolute operating input voltage 0 AVDD V
range
CIInput capacitance CHx to AGND 3 pF
IIL Input leakage current Clock turned off –1 1 µA
RID Differential input resistance 100 kΩ
CID Differential input capacitance 2.5 pF
At dc 108 dB
CMRR Common-mode rejection ratio VIN = ±1.25VPP at 40kHz 117 dB
BW Bandwidth Full-scale sine wave, –3dB 50 MHz
(1) All typical values are at TA= +25°C.
(2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range, expressed either
as the number of LSBs or as a percent of specified input range (4.6V).
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SAMPLING DYNAMICS
CLKSEL = 1, –40°C ≤TA≤+85°C 8 10 12 MHz
fCLK Internal clock frequency CLKSEL = 1, 7.8 10 12 MHz
–40°C ≤TA≤+105°C
fCLKIN External clock frequency CLKSEL = 0 1 20 24 MHz
AC ACCURACY
THD Total harmonic distortion VIN = ±2.3VPP at 5kHz –85 –80 dB
SFDR Spurious-free dynamic range VIN = ±2.3VPP at 5kHz 82 86 dB
VIN = ±2.3VPP at 5kHz 86 90 dB
SNR Signal-to-noise ratio VIN = ±2.0VPP at 5kHz 85 89 dB
SINAD Signal-to-noise + distortion VIN = ±2.3VPP at 5kHz 80 84 dB
Channel-to-channel isolation VIN = ±2.3VPP at 5kHz 100 dB
REFERENCE VOLTAGE OUTPUT
VREFOUT Reference output voltage 2.450 2.5 2.550 V
TCVREFOUT Reference output voltage drift ±20 ppm/°C
f = 0.1Hz to 10Hz, CL= 10mF 10 mVRMS
Output voltage noise f = 10Hz to 10kHz, CL= 10mF 12 mVRMS
IREFOUT Output current 10 mA
IREFSC Short-circuit current 0.5 mA
Turn-on settling time To accuracy level of 0.1%, no load 100 ms
REFERENCE VOLTAGE INPUT
VREFIN Input voltage 0.5 2.5 2.6 V
RREFIN Input resistance 100 MΩ
CREFIN Input capacitance 5 pF
IREFIN Input current 1 mA
DIGITAL INPUTS
Logic family CMOS with Schmitt Trigger
VIH High-level input voltage 0.7 × BVDD BVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × BVDD V
IIN Input current VIN = BVDD or BGND ±50 nA
CIInput capacitance 5 pF
DIGITAL OUTPUTS
Logic family CMOS
VOH High-level output voltage BVDD = 4.5V, IOH = –100mA 4.44 V
VOL Low-level output voltage BVDD = 4.5V, IOL = +100mA 0.5 V
COOutput capacitance 5 pF
CLLoad capacitance 30 pF
Data format Bit stream
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Product Folder Link(s): ADS1209
R
650W
ON C
1pF
(SAMPLE)
BVDD
DIN
BGND
AVDD
AIN
AGND
DiodeTurn-OnVoltage:0.35V
EquivalentDigitalInputCircuit
EquivalentAnalogInputCircuit
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– =
2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3filter with OSR = 256, unless otherwise noted.
ADS1209
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
DIGITAL INPUTS
Logic family LVCMOS
VIH High-level input voltage BVDD = 3.6V 2 BVDD + 0.3 V
VIL Low-level input voltage BVDD = 2.7V –0.3 0.8 V
IIN Input current VIN = BVDD or BGND ±50 nA
CIInput capacitance 5 pF
DIGITAL OUTPUTS
Logic family LVCMOS
VOH High-level output voltage BVDD = 2.7V, IOH = –100mA BVDD – 0.2 V
VOL Low-level output voltage BVDD = 2.7V, IOL = +100mA 0.2 V
COOutput capacitance 5 pF
CLLoad capacitance 30 pF
Data format Bit stream
POWER SUPPLY
AVDD Analog supply voltage 4.5 5.0 5.5 V
Low-voltage levels 2.7 3.0 3.6 V
BVDD Buffer I/O supply voltage 5V logic levels 4.5 5.0 5.5 V
CLKSEL = 1 12.2 17 mA
AIDD Analog operating supply current CLKSEL = 0 11.8 16 mA
BVDD = 3V, CLKOUT = 10MHz 0.9 2 mA
BIDD Buffer I/O operating supply current BVDD = 5V, CLKOUT = 10MHz 1.3 3 mA
CLKSEL = 1, 5V supply 67.5 100.0 mW
PDPower dissipation CLKSEL = 0, 5V supply 65.5 95 mW
BLANKSPACE
EQUIVALENT INPUT CIRCUITS
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS1209
AVDD
AGND
REFINA
NC
CHA+
CHA-
CHB-
CHB+
NC
REFINB
AGND
AVDD
AVDD
REFOUT
AGND
OUTA
OUTB
CLKOUT
BGND
BVDD
CLKIN
CLKSEL
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
ADS1209
14
13
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
PIN CONFIGURATION
PW PACKAGE
TSSOP-24
(TOP VIEW)
PIN DESCRIPTIONS
PIN
NAME NO. I/O(1) DESCRIPTION
AVDD 1 P Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AGND 2 P Analog ground. Connect to analog ground plane.
REFINA 3 AI Reference voltage input for channel A
NC 4 NC This pin is not internally connected
CHA+ 5 AI Fully differential noninverting analog input channel A
CHA– 6 AI Fully differential inverting analog input channel A
CHB– 7 AI Fully differential inverting analog input channel B
CHB+ 8 AI Fully differential noninverting analog input channel B
NC 9 NC This pin is not internally connected
REFINB 10 AI Reference voltage input for channel B
AGND 11 P Analog ground. Connect to analog ground plane.
AVDD 12 P Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AVDD 13 P Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AGND 14 P Analog ground. Connect to analog ground plane.
Clock select input. When this pin is low, an external clock source at CLKIN is used. When high, the
CLKSEL 15 DI internal RC oscillator is used as clock source.
CLKIN 16 DI External clock input. Must be tied to BVDD or BGND, if not used.
BVDD 17 P I/O buffer power supply, nominal: 3V. Decouple to BGND with a 0.1µF ceramic capacitor
BGND 18 P I/O buffer ground. Connect to digital ground plane
CLKOUT 19 DO Bit stream clock output
OUTB 20 DO Bit stream data output of channel B modulator
OUTA 21 DO Bit stream data output of channel A modulator
AGND 22 P Analog ground. Connect to analog ground plane.
REFOUT 23 AO Internal reference voltage output, nominal: 2.5V. Decouple to AGND with a 0.1µF ceramic capacitor.
AVDD 24 P Analog power supply, nominal: 5V. Decouple to AGND with a 0.1µF ceramic capacitor.
(1) AI = analog input; AO = analog output; DI = digital input; DO = digital output; P = power supply; NC = not connected.
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CLKIN
OUTx
CLKOUT
t2
t1
t3
tD3 tH1
tD1 t4tD2
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION
Figure 1. ADS1209 Timing Diagram
TIMING CHARACTERISTICS(1)
Over the recommended operating ambient temperature range of –40°C to +105°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted. PARAMETER TEST CONDITIONS MIN MAX UNIT
t1CLKIN period CLKSEL = 0 41.6 1000 ns
t2CLKIN high time CLKSEL = 0 10 t1– 10 ns
CLKSEL = 0 2 × t1ns
t3CLKOUT period CLKSEL = 1 83 125 ns
t4CLKOUT high time (t3/2) – 5 (t3/2) + 5 ns
tD1 CLKIN rising edge to CLKOUT falling edge delay CLKSEL = 0 10 ns
tD2 CLKIN rising edge to CLKOUT rising edge delay CLKSEL = 0 10 ns
CLKSEL = 0 t2+ 7 ns
tD3 CLKOUT rising edge to new data valid delay CLKSEL = 1 (t3/4) + 8 ns
CLKSEL = 0 t2– 3 ns
tH1 Data valid hold time referred to rising CLKOUT edge CLKSEL = 1 (t3/4) – 8 ns
(1) All input signals are specified with tR= tF= 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
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8
6
4
2
0
2
4
6
8
-
-
-
-
INL(LSB)
-2.0-2.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
DifferentialInputVoltage(V)
- °40 C
+25°C
+85°C
+105°C
4
3
2
1
0
1
2
3
4
-
-
-
-
INLMatch(LSB)
-2.0-2.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5
DifferentialInputVoltage(V)
- °40 C
+25°C
+85°C
+105°C
8
6
4
2
0
2
4
6
8
-
-
-
-
INL(LSB)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-
-
-
-
-
-
OffsetError(mV)
4.64.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-
-
-
-
-
-
OffsetErrorandMatch(mV)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
OffsetMatch
Offset
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
GainErrorandMatch(%FSR)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
GainMatch
Gain
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3filter, with OSR = 256, unless otherwise noted.
INTEGRAL NONLINEARITY INTEGRAL NONLINEARITY MATCH
vs INPUT SIGNAL VOLTAGE vs INPUT SIGNAL
Figure 2. Figure 3.
INTEGRAL NONLINEARITY OFFSET ERROR
vs TEMPERATURE vs ANALOG SUPPLY VOLTAGE
Figure 4. Figure 5.
OFFSET ERROR AND MATCH GAIN ERROR AND MATCH
vs TEMPERATURE vs TEMPERATURE
Figure 6. Figure 7.
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100
90
80
70
60
PSRR(dB)
100 10k
f (Hz)
RIPPLE
1k
130
120
110
100
90
CMRR(dB)
100 1M
f (Hz)
IN
1k 10k 100k
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
f (MHz)
CLK
4.64.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD(V)
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
f (MHz)
CLK
-40 125
Temperature( )°C
-25 110958065503520
-10 5
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
TYPICAL CHARACTERISTICS (continued)
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3filter, with OSR = 256, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO COMMON-MODE REJECTION RATIO
vs RIPPLE FREQUENCY vs INPUT SIGNAL FREQUENCY
Figure 8. Figure 9.
INTERNAL CLOCK FREQUENCY INTERNAL CLOCK FREQUENCY
ANALOG SUPPLY VOLTAGE vs TEMPERATURE
Figure 10. Figure 11.
TOTAL HARMONIC DISTORTION AND SPURIOUS-FREE TOTAL HARMONIC DISTORTION AND SPURIOUS-FREE
DYNAMIC RANGE vs INPUT FREQUENCY DYNAMIC RANGE vs TEMPERATURE
Figure 12. Figure 13.
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96
94
92
90
88
86
84
82
80
SNRandSINAD(dB)
100 10k
f (Hz)
IN
1k
SNR
SINAD
96
94
92
90
88
86
84
82
80
SNRandSINAD(dB)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
SNR
SINAD
0
20
40
60
80
100
120
140
-
-
-
-
-
-
-
Frequency(kHz)
0 20
Magnitude(dB)
2 4 6 8 10 12 14 16 18
0
20
40
60
80
100
120
140
-
-
-
-
-
-
-
Frequency(kHz)
0 20
Magnitude(dB)
2 4 6 8 10 12 14 16 18
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
VREFOUT(V)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
18
16
14
12
10
8
6
4
2
0
IDD(mA)
-40 125
Temperature( )°C
-25 110958065503520
-10 5
IBVDD
IAVDD,InternalCLK
IAVDD,ExternalCLK
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and
16-bit Sinc3filter, with OSR = 256, unless otherwise noted.
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE +
DISTORTION vs INPUT FREQUENCY DISTORTION vs TEMPERATURE
Figure 14. Figure 15.
FREQUENCY SPECTRUM FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 4.6VPP) (4096 Point FFT, fIN = 5kHz, 4.6VPP)
Figure 16. Figure 17.
INTERNAL REFERENCE VOLTAGE SUPPLY CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 18. Figure 19.
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27W
5kW
5kW2kW
2kW
+5V
0.1nF
+3V
+3V
0.1 Fm
0.1 Fm
0.1 Fm
±5V
OPA2350
0.1 Fm
27W
5kW
5kW2kW
2kW
+5V
0.1nF
±5V
OPA2350
0.1 Fm
2nd-Order
DS Modulator
FPGA
or
ASIC
CHA+
AVDD
CHA-Output
Interface
Circuit
RC
Oscillator
20MHz
Out EN
Clock
Select
Divider
REFINA
Reference
Voltage
2.5V
REFOUT
OUTA
OUTB
CLKIN
AGNDAGNDAGNDAGND
BVDD
CLKOUT
BVDD
BGND
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
CLKSEL
AVDD
AVDD
AVDD
AVDD
2nd-Order
DS Modulator
CHB+
CHB-
REFINB
+5V
OPA336
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
GENERAL DESCRIPTION
The ADS1209 is a two-channel, second-order, CMOS An application-specific integrated circuit (ASIC) or
device with two delta-sigma (ΔΣ) modulators, field-programmable gate array (FPGA) can be used
designed for medium- to high-resolution A/D signal to implement the digital filter. Alternatively, TI's
conversions from dc to 40kHz (filter response –3dB) if AMC1210 offers four programmable digital filters that
an oversampling ratio (OSR) of 64 is chosen. The can be used. Figure 20 and Figure 21 show typical
output of the converter (OUTx) provides a stream of application circuits with the ADS1209 connected to an
digital ones and zeros. The time average of this serial FPGA or ASIC.
output is proportional to the analog input voltage. The overall performance (that is, speed and
The modulator shifts the quantization noise to high accuracy) depends on the selection of an appropriate
frequencies. A low-pass digital filter should be used OSR and filter type. A higher OSR produces greater
at the output of the ΔΣ modulator. The filter serves output accuracy while operating at a lower data rate.
two functions. First, it filters out high-frequency noise. Alternatively, a lower OSR produces lower output
Second, the filter converts the 1-bit data stream at a accuracy, but operates at a higher data rate. This
high sampling rate into a higher-bit data word at a system allows flexibility with the digital filter design
lower rate (decimation). and is capable of A/D conversion results that have a
dynamic range exceeding 86dB with an OSR = 256.
Figure 20. Single-Ended Connection Diagram for the ADS1209 ΔΣ Modulator
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): ADS1209
+3V
+3V
0.1 Fm
0.1 Fm
0.1 Fm
2nd-Order
DS Modulator
FPGA
or
ASIC
CH A+
AVDD
CHA-Output
Interface
Circuit
RC
Oscillator
20MHz
Out EN
Clock
Select
Divider
REFIN A
Reference
Voltage
2.5V
REFOUT
OUTA
OUT B
CLKIN
AGNDAGNDAGNDAGND
BVDD
CLKOUT
BVDD
BGND
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
CLKSEL
AVDD
AVDD
AVDD
AVDD
2nd-Order
DS Modulator
CHB+
CHB-
REFINB
27W
R1
R2
+5V
0.1nF
IN+
IN-
OPA4354
27W
R1
R2
+5V
OPA4354
27W
R1
R2
+5V
0.1nF
IN+
IN-
OPA4354
27W
R1
R2
+5V
OPA4354
+5V
OPA336
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
Figure 21. Differential Connection Diagram for the ADS1209 ΔΣ Modulator
12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1209
Z =
IN
100kW
f /10MHz
MOD
650W
650W
SwitchingFrequency=CLK
High
Impedance
>1GW
1.2pF
VCM
AIN+
1.2pF
0.4pF
0.4pF
AIN-
High
Impedance
>1GW
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
THEORY OF OPERATION The input impedance of the analog input depends on
the modulator clock frequency (fMOD). Figure 22
The differential analog input of the ADS1209 is shows the basic input structure of one channel of the
implemented with a switched-capacitor circuit. This ADS1209. The relationship between the input
circuit implements a second-order modulator stage, impedance of the ADS1209 and the modulator clock
which digitizes the analog input signal into a 1-bit frequency is:
output stream. The clock source can be internal as
well as external. Every analog input signal is
continuously sampled by the modulator and (1)
compared to a reference voltage that is applied to the The input impedance becomes a consideration in
REFINx pin. A digital stream that represents the designs where the source impedance of the input
analog input voltage over time appears at the output signal is high. This high impedance may cause
of the corresponding converter. degradation in gain, linearity, and THD. The
importance of this effect depends on the desired
ANALOG INPUT STAGE system performance. There are two restrictions on
the analog input signals, CHx+ and CHx–. If the input
Analog Input voltage exceeds the range (AGND – 0.3V) to (AVDD
The topology of the analog inputs of ADS1209 is + 0.3V), the input current must be limited to 10mA
based on fully differential switched-capacitor because the input protection diodes on the front end
architecture. This input stage provides the of the converter begin to turn on. In addition, the
mechanism to achieve low system noise, high linearity and noise performance of the device meet
common-mode rejection, and excellent power-supply the stored specifications only when the differential
rejection. analog voltage resides within ±2.3V (with VREFIN as a
midpoint); however, the FSR input voltage is ±2.5V.
BLANKSPACE
Figure 22. Input Impedance of the ADS1209
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS1209
VREF
X4
X6
Integrator2
Comparator
fCLK
DATA
DAC
X3
X2
X(t)
fS
Integrator1
ModulatorOutput
AnalogInput
+FS(AnalogInput)
-FS(AnalogInput)
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
Modulator comparator switches from low to high, or vice versa,
depending on its original state. When the output
The ADS1209 can be operated in two modes. When value of the comparator switches direction, the 1-bit
CKLSEL = 1, the two modulators operate using the DAC responds on the next clock pulse by changing
internal clock, which is fixed at 20MHz. When its analog output voltage at X6, causing the
CKLSEL = 0, the modulators operate using an integrators to progress in the opposite direction. The
external clock. In both modes, the clock is internally feedback of the modulator to the front end of the
divided by two and functions as the modulator clock. integrators forces the value of the integrator output to
The frequency of the external clock can vary from track the average of the input.
1MHz to 24MHz to adjust for the clock requirements
of the application. DIGITAL OUTPUT
The modulator topology is a second-order, A differential input signal of 0V ideally produces a
switched-capacitor, ΔΣ modulator, such as the one stream of ones and zeros that are high 50% of the
conceptualized in Figure 23. The analog input voltage time and low 50% of the time. A differential input of
and the output of the 1-bit digital-to-analog converter +2.3V produces a stream of ones and zeros that are
(DAC) are differentiated, providing analog voltages at high 92% of the time. A differential input of –2.3V
X2and X3. The voltages at X2and X3are presented produces a stream of ones and zeros that are high
to the respective individual integrators. The output of 8% of the time. The input voltage versus the output
these integrators progresses in a negative or positive modulator signal is shown in Figure 24.
direction. When the value of the signal at X4equals
the comparator reference voltage, the output of the
Figure 23. Block Diagram of the Second-Order Modulator
Figure 24. Analog Input vs Modulator Output of the ADS1209
14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1209
0
-10
-20
-30
-40
-50
-60
-70
-80
Gain(dB)
Frequency(kHz)
0 200 400 600 800 1000 1200 1400 1600
OSR=32
f =10MHz/32=312.5kHz
3dB:81.9kHz
DATA
-
H(z)= 1 z-
-OSR
1 z-
-1
3
0
10
20
30
40
50
60
-
-
-
-
-
-
Gain(dB)
100 100k
Frequency(Hz)
10k1k
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
DIGITAL INTERFACE
This behavior can be adjusted by a cascaded filter
INTRODUCTION structure. For example, the first decimation stage can
be a Sinc3filter with a low OSR, and the second
The analog signal connected to the input of the ΔΣ stage a high-order filter.
modulator is converted using the clock signal applied
to the modulator. The result of the conversion (or For more information, see application note SBAA094,
modulation) is available on one of the OUTx pins, Combining the ADS1202 with an FPGA Digital Filter
depending on the modulator. In addition, a common for Current Measurement in Motor Control
clock output signal (CLKOUT) for both Applications, available for download at www.ti.com.
simultaneously-sampling modulators is provided. If
CLKSEL = 1, CLKIN must not be left floating, but
should tied to BVDD or BGND.
MODES OF OPERATION
The device clock of the ADS1209 is 20MHz by
default. The device clock can either be generated by
the internal 20MHz RC oscillator or can be provided
by an external clock source. For this purpose, the
CLKIN pin is provided; it is controlled by the mode
setting, CLKSEL.
The device clock is divided by two before being used
as the modulator clock. Therefore, the default clock
frequency of the modulator is 10MHz. With a possible
external clock range of 1MHz to 24MHz, the
modulator operates between 500kHz and 12MHz. Figure 25. Frequency Response of Sinc3Filter
(OSR = 32)
FILTER USAGE
The modulator generates a bitstream. In order to
output a digital word equivalent to the analog input
voltage, the bitstream must be processed by a digital
filter.
A simple filter, built with minimal effort and hardware,
is the Sinc3filter shown in Equation 2:
(2)
This filter provides the best output performance with a
relatively low number of gates required for
implementation. For oversampling ratios in the range
of 16 to 256, this filter architecture represents a good
choice. All the characterizations in this data sheet are
done using a Sinc3filter with an oversampling ratio of Figure 26. Frequency Response of Sinc3Filter
OSR = 256 and an output word width of 16 bits. (OSR = 256)
In a Sinc3filter response (shown in Figure 25 and
Figure 26), the location of the first notch occurs at the
frequency of output data rate fDATA = fMOD/OSR. The
–3dB point is located at half the Nyquist frequency or
fDATA/4.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS1209
SNR=1.76dB+6.02dB ENOB´
H(z)= 1 z-
-OSR
1 z-
-1(1+z )
- ´2OSR
2
16
14
12
10
8
6
4
2
0
ENOB(Bits)
10 1000
OSR
100
Sinc2
Sinc3
0 2 6 84 10
Settling Time(ms)
ENOB(Bits)
10
9
8
7
6
5
4
3
2
1
0
Sincfast
Sinc3
Sinc
Sinc2
ADS1209
SBAS491 –FEBRUARY 2010
www.ti.com
The effective number of bits (ENOB) can be used to the modulator clock divided by the OSR. For
compare the performance of A/D converters and ΔΣ overcurrent protection, filter types other than Sinc3
modulators. Figure 27 shows the ENOB of the may be a better choice. A simple example is a Sinc2
ADS1209 with different filter types. In this data sheet, filter. The Sincfast is a modified Sinc2filter as
the ENOB is calculated from the SNR as shown in Equation 4 shows:
Equation 3:(3)
(4)
Figure 28 compares the settling time of different filter
types operating with a 10MHz modulator clock.
Figure 27. Measured ENOB vs OSR
In motor-control applications, a very fast response
time is required for overcurrent detection. There is a Figure 28. Measured ENOB vs Settling Time
constraint between 1ms and 5ms with 3 bits to 7 bits
of resolution. The time for full settling depends on the
filter order. Therefore, the full settling of the Sinc3For more information, see application note SBAA094,
filter requires three data clocks and the Sinc2filter Combining the ADS1202 with an FPGA Digital Filter
requires two data clocks. The data clock is equal to for Current Measurement in Motor Control
Applications, available for download at www.ti.com.
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1209
ADS1209
www.ti.com
SBAS491 –FEBRUARY 2010
LAYOUT CONSIDERATIONS
POWER SUPPLIES DECOUPLING
An applied external digital filter rejects high-frequency Good decoupling practices must be used for the
noise. PSRR and CMRR improve at higher ADS1209 and for all components in the design. All
frequencies because the digital filter suppresses decoupling capacitors, specifically the 0.1mF ceramic
high-frequency noise. However, the suppression of capacitors, must be placed as close as possible to
the filter is not infinite while high-frequency noise the pin being decoupled. A 1mF and 10mF capacitor,
continues to influence the conversion result. in parallel with the 0.1mF ceramic capacitor, can be
used to decouple AVDD to AGND as well as BVDD
Inputs to the ADS1209, such as CHx+, CHx–, and to BGND. At least one 0.1mF ceramic capacitor must
CLKIN, should not be present before the power be used to decouple every AVDD to AGND and
supply is on. Violating this condition could cause BVDD to BGND, as well as for the digital supply on
latch-up. If these signals are present before the each digital component.
supply is on, series resistors should be used to limit
the input current to a maximum of 10mA. The digital supply sets the I/O voltage for the
interface and can be set within a range of 2.7V to
5.5V.
GROUNDING In cases where both the analog and digital I/O
Analog and digital sections of the design must be supplies share the same supply source, an RC filter
carefully and cleanly partitioned. Each section should of 10Ωand 0.1mF can be used to help reduce the
have its own ground plane with a connection between noise in the analog supply.
them underneath the converter.
For multiple converters, connect the two ground
planes as close as possible to each of the converters.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS1209
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS1209SPW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1209SPWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1209SPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1209SPWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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