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December 1997
ACTS138MS
Radiation Hardened
TTL Input, 3-to-8 Line Decoder/Demultiplexer
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . .3 x 105RAD(Si)
- SEU Immunity. . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . .>100MeV/(mg/cm2)
• Input Logic Levels . . . . . . . . . . VIL = 0.8V, VIH = (Vcc/2)
• Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA
• Quiescent Supply Current. . . . . . . . . . . . . . . . . . . .20µA
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . .20ns
Applications
• Memory Decoding
• Data Routing
• Code Conversion
Description
The Radiation Hardened ACTS138MS is an Inver ting 3-to-8
Line Decoder/Demultiplexer with three TTL level binary
select inputs (A0, A1 and A2). If the device is enabled, these
inputs determine which one of the eight normally high out-
puts will go low.
Two activ e low and one activ e high enab le inputs (E1, E2 and
E3) are provided to make cascaded decoder designs easier
to implement.
The ACTS138MS is fabricated on a CMOS Silicon on Sap-
phire (SOS) process, which provides an immunity to Single
Event Latch-up and the capability of highly reliable perfor-
mance in any radiation environment. These devices offer
significant power reduction and faster performance when
compared to ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed belo w m ust be used when or dering.
Detailed Electrical Specifications for the ACTS138 are
contained in SMD 5962-98535. A “hot-link” is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Ordering Information
Pinouts ACTS138 (SBDIP)
TOP VIEW ACTS138 (FLATPACK)
TOP VIEW
SMD PART NUMBER INTERSIL PART NUMBER TEMP. RANGE (oC) PACKAGE CASE OUTLINE
5962F9853501VEC ACTS138DMSR-02 -55 to 125 16 Ld SBDIP CDIP2-T16
N/A ACTS138D/Sample-02 25 16 Ld SBDIP CDIP2-T16
5962F9853501VXC ACTS138KMSR-02 -55 to 125 16 Ld Flatpack CDFP4-F16
N/A ACTS138K/Sample-02 25 16 Ld Flatpack CDFP4-F16
N/A ACTS138HMSR-02 25 Die N/A
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
Y7
VCC
Y1
Y2
Y3
Y4
Y5
Y6
Y0
A0
A1
A2
E1
E2
E3
Y7
GND
2
3
4
5
6
7
8
116
15
14
13
12
11
10
9
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
File Number 4460
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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Die Characteristics
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
METALLIZATION: Al
Metal 1 Thickness: 0.7µm±0.1µm
Metal 2 Thickness: 1.0µm±0.1µm
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm±0.15µm
SPECIAL INSTRUCTIONS:
Bond VCC First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 105 A/cm2
Transistor Count: 256
Metallization Mask Layout
ACTS138MS
A1A0VCC Y0
A2
E1
E2
E3
Y1
Y2
Y3
Y4
Y7GND Y6Y5
ACTS138MS
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information fur nished by Intersil is believed to be accurate
and reliable . However, no responsibility is assumed by Intersil or its subsidiaries f or its use; nor for any infringements of patents or other rights of third parties which
may result from its use . No license is g r anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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