Supertex inc.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5623
Block Diagram
32-Channel Serial To Parallel Converter
With Open Drain Outputs
General Description
The HV5623 is a low-voltage serial to high-voltage parallel converter
with open drain outputs. This device has been designed for use as
a driver for AC-electroluminescent displays. It can also be used in
any application requiring multiple output high voltage current sinking
capabilities, such as driving inkjet and electrostatic print heads,
plasma panels, and vacuum uorescent or large matrix LCD displays.
This device consists of a 32-bit shift register, 32 latches, and control
logic to perform the polarity selection and blanking of the outputs.
Data are shifted through the shift register on the high to low transition
of the clock. The HV5623 shifts in a clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reects the current status of the last
bit of the shift register. Operation of the shift register is not affected by
the LE (latch enable), BL (blanking), or POL (polarity) inputs. Transfer
of data from the shift register to the latch occurs when the LE (latch
enable) input is high. The data in the latch is stored when LE is low.
POL
BL
LE
DATA
INPUT
CLK
DATA
OUTPUT
HVOUT1
(Outputs 3 to 30
not shown)
Latch
Latch
HVOUT2
HVOUT31
HVOUT32
Latch
Latch
32-Bit
Shift
Register
Features
►Processed with HVCMOS® technology
►Sink current minimum 100mA
►Shift register speed 16MHz
►Polarity and blanking inputs
►CMOS compatible inputs
Applications
►Inkjet and Electrostatic Print Heads
►AC-Electroluminescent Displays
►MEMS Applications
2
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5623
Ordering Information
Device
High Voltage
Output
HVOUT
(max V)
44-Lead QFN
7.00x7.00mm body,
0.80mm height (max),
0.50mm pitch
HV5623 220 HV5623K7-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
Supply voltage, VDD
1-0.5V to +7.0V
Output voltage, HVOUT
1-0.5V to +230V
Logic input levels1-0.5V to VDD +0.5V
Ground current21.5A
Continuous total power dissipation33.4W
Operating temperature range -40°C to +85°C
Storage temperature range -65°C to +150°C
Maximum junction temperature +125°C
Thermal resistance (θja)329OC/W
Notes:
1. Voltages are referenced to VSS.
2. Duty cycle is limited by the total power dissipated in the package.
3. 1.0oz 4-layer 3x4” PCB.
Pin Conguration
Operating Supply Voltages and Conditions
Sym Parameter Min Typ Max Units Conditions
VDD Logic supply voltage 4.5 - 5.5 V ---
HVOUT High voltage output -0.3 - +220 V ---
VIH High-level input voltage 0.8VDD - VDD V ---
VIL Low-level input voltage 0 - 0.2VDD V ---
fCLK Clock frequency - - 16 MHz ---
TAOperating free-air temperature -40 - +85 °C ---
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Product Marking
44-Lead QFN (K7)
1
44
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
HV5623K7
LLLLLLLLL
YYWW
AAA CCC
44-Lead QFN (K7)
(top view)
Package may or may not include the following marks: Si or
3
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5623
DC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted)
Sym Parameter Min Typ Max Units Conditions
IDD VDD supply current - - 25 mA fCLK = 16MHz, fDATA = 8.0MHz
IDDQ Quiescent VDD supply current - - 100 µA DIN = 0V, all input logic pins =
0V, all outputs OFF
IO(OFF) OFF state output current - - 10 µA All outputs high,
all switches parallel
IIH High-level logic input current - - 1.0 µA VIH = VDD
IIL Low-level logic input current - - -1.0 µA VIL = 0V
VOH High level output VDD -1.0V - - V IDOUT = -10mA
VOL Low level output HVOUT - - 15 V IHVOUT = +100mA
DATA OUT - - 1.0 V IDOUT = +10mA
VOC HVOUT clamp voltage - - -1.5 V IOL = -100mA
AC Electrical Characteristics (VDD = 5.0V, Tj = 25OC)
Sym Parameter Min Typ Max Units Conditions
fCLK Clock frequency - - 16 MHz ---
tWClock high / low pulse width 31 - - ns ---
tSU Data setup time before clock falls 25 - - ns ---
tHData hold time after clock falls 10 - - ns ---
tON Turn ON time, HVOUT from Enable - - 400 ns RL = 2.0kΩ to VPP max
tDHL Delay time clock to data high to low - - 35 ns CL = 15pF
tDLH Delay time clock to data low to high - - 35 ns CL = 15pF
tDLE Delay time clock to LE low to high 20 - - ns ---
tWLE Width of LE pulse 20 - - ns ---
tSLE LE set-up time before clock falls 20 - - ns ---
CIN Digital logic input capacitance - - 15 pF ---
Input and Output Equivalent Circuits
VDD
DATA
INPUT
HVOUT
Logic Inputs
DATA
OUTPUT
Logic Data Output High Voltage Outputs
VDD
VSS VSS
VSS
4
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5623
Switching Waveforms
LE
HV
OUT
w/ S/R HIGH
Data Valid50%
DATA
INPUT
CLK
DATA
OUTPUT
t
SU
t
H
t
WH
t
WL
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50% 50%
10%
t
ON
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
OH
V
OL
50%
50% 50%50%50%
Function Table
Function
Inputs Outputs
Data CLK LE BL POL Shift Reg
1 2...32
HV Outputs
1 2...32
Data Out
*
All ON X X X L L * *...*ON ON...ON *
All OFF X X X LH* *...*OFF OFF...OFF *
Invert mode X X LHL* *...* * *...**
Load S/R H or L ↓ L H H H or L *...* * *...**
Load latches XH or L ↑ H H * *...* * *...**
XH or L ↑ HL* *...* * *...**
Transparent latch
mode
L ↓ HHHL *...*OFF *...**
H↓H H H H *...*ON *...**
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition
* = dependent on previous stage’s state before the last CLK↓ or last LE high.
5
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5623
Pin # Function Description
1 HVOUT22
High voltage outputs.
2 HVOUT21
3 HVOUT20
4 HVOUT19
5 HVOUT18
6 HVOUT17
7 HVOUT16
8 HVOUT15
9 HVOUT14
10 HVOUT13
11 HVOUT12
12 HVOUT11
13 HVOUT10
14 HVOUT9
15 HVOUT8
16 HVOUT7
17 HVOUT6
18 HVOUT5
19 HVOUT4
20 HVOUT3
21 HVOUT2
22 HVOUT1
23 DATA OUT Data output pin.
24 N/C
No internal connection.25 N/C
26 N/C
27 POL Inverts the polarity of the HVOUT pins
28 CLK Clock pin, shift registers shifts data on falling edge of input clock.
29 VSS Reference voltage, usually ground.
30 VDD Logic supply voltage.
31 LE Latch enable pin, data is shifted from shift register to latches on logic input high.
32 DATA IN Data input pin.
33 BL Blanking pin sets all HVOUT pins ON or OFF depending upon state of polarity. See function table.
34 N/C No internal connection.
35 HVOUT32
High voltage outputs.
36 HVOUT31
37 HVOUT30
38 HVOUT29
39 HVOUT28
40 HVOUT27
41 HVOUT26
42 HVOUT25
43 HVOUT24
44 HVOUT23
Center Tab Connect to VSS
Pin Description
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA
94089
Tel: 408-222-8888
www
.supertex.com
6
HV5623
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV5623
A062111
44-Lead QFN Package Outline (K7)
7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch
Symbol A A1 A3 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.70 0.00
0.20
REF
0.18 6.85* 5.00†6.85* 5.00†
0.50
BSC
0.45†0.00 0O
NOM 0.75 0.02 0.25 7.00 5.15†7.00 5.15†0.55†- -
MAX 0.80 0.05 0.30 7.15* 5.25†7.15* 5.25†0.65†0.15 14O
JEDEC Registration MO-220, Variation WKKD-3, Issue K, June 2006
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44QFNK77X7P050, Version A122309.
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
A3
L
L1
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
1
44
1
44
View B
Note 1
(Index Area
D/2 x E/2)
b
e
E2
D2
θx4
View B