Rev. 0.3 8/09 Copyright © by 2009 Silicon Labo ratories Si5xx5x7-EVB
Si5xx5x7-EVB
EVALUATION BOARD FOR Si53X/55X/59X XOS/VCXOS
Description
This document describes the operation of the Silicon
Laboratories Si5xx5x7-EVB evaluation board to
evaluate both Silicon Laboratories' Si55x and Si595
VCXOs and Si53x and Si590/591 XOs. The Si53x/55x/
59x devices use Silicon Laboratories' advanced
DSPLL® circuitry to provide a low-jitter clock at high
frequencies. The Si55x/Si53x/59x IC-based device is
factory configurable for a wide variety of user
specifications including frequency, supply voltage,
output, and tuning slope. Specific configurations are
factory programmed into the Si55x/Si53x/59x at time of
shipment, thereby eliminating the long lead times
associated with custom oscillators. Si55x/Si53x/59x
samples should be ordered at the same time as the
Si5xx5x7-EVB since the EVB does not come with the
device. This allows end users maximum flexibility.
Silicon Laboratories can solder down samples when
ordering an EVB; please specify when ordering.
Features
Evaluation of Silicon Laboratories' Si55x/53x/59x
family
AC-coupled differential output clocks
Voltage control (VC) input port (for Si55x/595
devices)
Jumper selection for multi-frequency outputs
Jumper selection for output enable
Functional Block Diagram
Si5xx
Device
VC
Input
CLK+
Output
Bias DC
Block
RC F ilter
(no-pop)
Configuration
Jumpers
CLK–
Pow er Input
Si5xx5x7-EVB
2 Rev. 0.3
1. Functional Description
The Si5xx5x7-EVB provides access to all signals for
configuring and operating the device. This board allows
evaluation of the Si55x/59 5 VCXO device either b y it self
(open-loop) or within a prototyp e PLL (closed-loop) . The
performance of the Si53x/590/591 XO device can also
be evaluated on this board (the Vc port is not used for
XO devices).
1.1. Power Supply
The Si55x/Si53x/59x devices support operation from
nominal voltages of 1.8, 2.5, and 3.3 V. Review the
device data sheet and part number for allowed
configurations of output buffer type and device power
supply.
1.2. Voltage Control for VCXOs
The voltage con trol (VC) inp ut of the Si55x/595 device is
conveniently accessible through an SMA jack (J3) but
can also be driven (and observed) through 100 mil-
centered posts (JP4). For prototyping purposes, two
0603 solder pads are located near the device VC input
(R3 and C3). A traditional PLL might use these as a
single-time-constant low-pass filter (RC filter). The EVB
is shipped with a 0 resistor soldered at R3; C3 is left
open. The voltage control input is not used for XO
devices.
1.3. Output Clock
Because the Si55x/Si53x/59x devices can support an
LVPECL buffer type (in addition to LVDS and CMOS),
pulldown resistors (R1 and R2) are available for proper
output biasing. For LVPECL buffers, biasing can be
achieved through a variety of equivalent circuits; the
Si5xx5x7-EVB allows for 130 pulldown resistors. After
the output biasing, the high-speed outputs are dc-
blocked for connection to differently biased inputs, such
as standard test equipment or a phase detector EVB.
Please review “1.4. Preparing the EVB” for non-LVPECL
devices.
1.4. Preparing the EVB
By default, the evaluation board is set up to accept
LVPECL configured devices. This configuration uses
130 pull-down resistors to bias the LVPECL output
stage. If an LVDS, CMOS, or CML based device is to
be installed, the output biasing resistors, R1 and R2,
should be removed.
Table 1. Jumper Control
Part Type JP1 JP2 JP3 JP4
Si530 N/A N/A OE N/A
Si531 N/A N/A N/A OE
Si532 N/A N/A OE Freq Sel
Si533 N/A N/A Freq Sel OE
Si534 Freq Sel1 Freq Sel2 OE N/A
Si550 N/A N/A OE VC
Si552 N/A N/A Freq Sel VC
Si554 Freq Sel1 Freq Sel2 OE VC
Si590 N/A N/A OE N/A
Si591 N/A N/A N/A OE
Si595 N/A N/A OE VC
Notes:
1. With jumper(s) installed, signal(s) are driven low.
2. With jumper(s) not installed, signal(s) are pulled high.
Si5xx5x7-EVB
Rev. 0.3 3
2. Schematics
VDD
VDD
VDD
F1
OE
F2
OE
F2
F1
EVB Power Input
Vc input High-order pole
Alternate Vc input
Place in-line with J3
Main output; route as differential pair
Silicon Labs VCXO
Frequency Select
Output Enable
JP4JP4
J1
SMA
J1
SMA
JP1JP1
C2
0.1uF
C2
0.1uF
C6
DNS
C6
DNS
J2
SMA
J2
SMA
J3
SMA
J3
SMA
C1
0.1uF
C1
0.1uF
C3
DNS
C3
DNS
R1
DNS
R1
DNS
C5
DNS
C5
DNS
JP2JP2
R3
0
R3
0
POS1 1
POS2 2
J4
MKDSN 2,5/3-5,08
J4
MKDSN 2,5/3-5,08
VC
1
OE
2
CLKOUT- 4
CLKOUT+ 5
VDD 6
GND
3
F1
7
F2
8
DNC
9
U1
Si550
U1
Si550
C4
DNS
C4
DNS
R2
DNS
R2
DNS
JP3JP3
Figure 1. Si5xx5x7-EVB Schematic
Si5xx5x7-EVB
4 Rev. 0.3
3. Bill of Materials
Table 2. Si5xx5x7-EVB Bill of Materials
Item Qty Ref Description Mfr # Mfr
1 2 C1,C2 CAP,SM,0.1 µF,
16 V,20%,X7R,0402 C0402X7R160-104KNE Venkel
2 2 C5 CAP,SM,0.1 µF,
16 V,20%,X7R,0603 C0603X7R160-104KNE Venkel
31 C4 CAP,SM,10µF,
10 V,10%,TANTALUM,3216 TA010TCM106KAR Venkel
4 1 C6 CAP,SM,100 pF,
50 V,10%,C0G,0603 C0603C0G500-101KNE Venkel
5 4 JP1,JP2,
JP3,JP4 CONN,HEADER,2X1 TSW-150-07-T-D or
TSW-150-07-T-S Samtec
6 3 J1,J2,J3 CONN,SMA SIDE MOUNT 901-10003 Amphenol
7 1 J4 CONN,POWER,
2 POSITION 1729018 Phoenix Contact
8 1 R3 RES,SM,0 ,0603 CR0603-16W-000T Venkel
9 2 R1,R2 RES,SM,150,1%,0603 CR0603-16W-1500FT Venkel
No Load
11 1 C3 CAP,SM,0.1 µF,
16 V,20%,X7R,0603 C0603X7R160-104KNE Venkel
10 1 U1 Si5xx - Not populated Si5xx Silicon Laboratories
Si5xx5x7-EVB
Rev. 0.3 5
4. Layout
Figure 2. Assembly Drawing
Figure 3. Layer 1 Primary
Figure 4. Layer 2 Secondary
Si5xx5x7-EVB
6 Rev. 0.3
DOCUMENT CHANGE LIST
Revision 0.13 to Revision 0.14
Updated "Bill of Materials‚" on page 4.
Updated Figure 2, “Assembly Drawing,” on page 5.
Revision 0.14 to Revision 0.2
Changed Si5xx-EVB to Si5xx5x7-EVB.
Revision 0.2 to Revision 0.3
Changed instances of Si53x/590/591, Si55x, and
Si53x to Si53x/55x/59x throughout.
Updated Table 1, “Jumpe r Co ntr o l,” on page 2.
Si5xx5x7-EVB
Rev. 0.3 7
NOTES:
Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
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