2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Features DDR2 SDRAM SORDIMM MT18HTS25672RH - 2GB MT18HTS51272RH - 4GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * 200-pin, small-outline registered, dual in-line memory module (SORDIMM) * Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300 * 2GB (256 Meg x 72), 4GB (512 Meg x 72) * Supports ECC error detection and correction * VDD = VDDQ = +1.8V * VDDSPD = +3.0V to +3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * Multiple internal device banks for concurrent operation * Programmable CAS# latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * PLL to reduce system clock line loading * Gold edge contacts * Dual rank, using TwinDieTM devices * I2C temperature sensor Table 1: 200-Pin SORDIMM (MO-224) PCB height: 30mm (1.18in) Options Marking 1 * Operating temperature - Commercial (0C TA +70C) - Industrial (-40C TA +85C) * Package - 200-pin DIMM (Pb-free) * Frequency/CAS latency2 - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) - 5.0ns @ CL = 3 (DDR2-400) * PCB height - 30mm (1.18in) None I Y -667 -53E -40E Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 5 CL = 4 -667 -53E -40E PC2-5300 PC2-4200 PC2-3200 667 - - 533 533 - PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 1 tRCD tRP tRC CL = 3 (ns) (ns) (ns) 400 400 400 15 15 15 15 15 15 55 55 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 2GB 4GB 8K 16K (A0-A13) 8 (BA0-BA2) 1KB 2Gb TwinDie (256 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 32K (A0-A14) 8 (BA0-BA2) 1KB 4Gb TwinDie (512 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) Part Numbers and Timing Parameters - 2GB Modules Base device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM Part Number2 MT18HTS25672RH(I)Y-667__ MT18HTS25672RH(I)Y-53E__ MT18HTS25672RH(I)Y-40E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 2GB 2GB 2GB 256 Meg x 72 256 Meg x 72 256 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters - 4GB Modules Base device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Module Density Configuration Part Number2 MT18HTS51272RH(I)Y-667__ MT18HTS51272RH(I)Y-53E__ MT18HTS51272RH(I)Y-40E__ Notes: PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 4GB 4GB 4GB 512 Meg x 72 512 Meg x 72 512 Meg x 72 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18HTS25672PY-667E1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SORDIMM Front 200-Pin SORDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF DQ0 VSS DQ1 DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CKE0 CKE1 EVENT# VDD A12 A9 A7 PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 VDD A5 A3 A2 VDD A10 BA0 RAS# VDD CAS# S1# VDD ODT1 NC DQ32 VSS DQ33 DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 DQ58 VSS DQ59 VDDSPD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 3 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS RESET# DM2 VSS DQ22 DQ23 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VSS DQ28 DQ29 VSS DM3 VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 VSS CB6 CB7 VSS CB2 CB3 VSS BA2 A14 A11 VDD A8 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A6 A4 VDD A1 A0 BA1 VDD WE# S0# ODT0 A13 VDD CK0 CK0# VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 VSS DM5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 DQ62 VSS DQ63 SDA SCL SA1 SA0 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type ODT0, ODT1 Input (SSTL_18) CK0, CK0# CKE0, CKE1 S0#, S1# RAS#, CAS#, WE# BA0-BA2 A0-A13 (2GB), A0-A14 (4GB) DM0-DM8 SCL SA0-SA1 RESET# DQ0-DQ63 CB0-CB7 DQS0-DQS8 SDA EVENT# VDD VREF VSS VDDSPD NC Description On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Input Clock: CK and CK# are differential clock inputs. All address and control input signals are (SSTL_18) sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates (SSTL_18) clocking circuitry on the DDR2 SDRAM. Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command (SSTL_18) decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being (SSTL_18) entered. Input Bank address inputs: BA0-BA2 define to which device bank an ACTIVE, READ, WRITE, or (SSTL_18) PRECHARGE command is being applied. BA0-BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. Input Address inputs: Provide the row address for ACTIVE commands, and the column address (SSTL_18) and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA2) or all device banks (A10 HIGH). The address inputs also provide the opcode during a LOAD MODE command. Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM (SSTL_18) is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Input Serial clock: SCL is used to synchronize the presence-detect and temperature sensor data (SSTL_18) transfer to and from the module. Input Serial address inputs: These pins are used to configure the presence-detect and (SSTL_18) temperature sensor devices. Input Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be (LVCMOS) used during power-up to ensure that CKE is LOW and DQs are High-Z. I/O Data input/output: Bidirectional data bus. (SSTL_18) I/O Check bits. (SSTL_18) I/O Data strobe: Output with read data, input with write data for source synchronous (SSTL_18) operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of (SSTL_18) the presence-detect and temperature sensor devices. Output Temperature sensor alarm output. Supply Power supply: +1.8V 0.1V. Supply SSTL_18 reference voltage. Supply Ground. Supply Serial EEPROM and temperature sensor positive power supply: +3.0V to +3.6V. - No connect: These pins should be left unconnected. PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM DQ DQ DQ DQ DQ DQ DQ DQ U1b CS# DM DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U14b CS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U8t DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U14t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U11b CS# DQS DQS# U11t DQS6# DQS6 DM6 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM DQ DQ DQ DQ DQ DQ DQ DQ U2b CS# DM DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2t DQS3# DQS3 DM3 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U9b CS# DQS DQS# U6t DQS7# DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS# U8b DM DQS DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U13b CS# DM DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U13t CS# DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U10b CS# DQS DQS# U10t DQS8# DQS8 DM8 DM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U12b DM DQ DQ DQ DQ DQ DQ DQ DQ CS# U6 DQS DQS# CK0 CK0# PLL U12t RESET# U5 SPD EEPROM WP A0 SCL Rank0 = U1b, U2b, U8b-U14b Rank1 = U1t, U2t, U8t-U14t R E G I S T E R RS0#: Rank0 RS1#: Rank1 RBA0-RBA2: DDR2 SDRAM RA0-RA13/RA14: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: Rank0 RCKE1: Rank1 RODT0: Rank0 RODT1: Rank1 A1 SDA A2 VSS SA0 SA1 VSS U3 Temp Sensor U7 S0# S1# BA0-BA2 A0-A13/A14 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 EVT A0 A1 SDA A2 SA0 SA1 VSS Event# VDDSPD SPD EEPROM, temperature sensor VDD DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM RESET# PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM General Description General Description The MT18HTS25672RH and MT18HTS51272RH DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 2GB and 4GB memory modules organized in a x72 configuration. DDR2 SDRAM modules use internally configured 8-bank (2Gb TwinDie and 4Gb TwinDie) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Register and PLL Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address, command, control, and clock signal loading by isolating DRAM from the system controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Temperature Sensor An on-board temperature sensor provides the ability to monitor the module temperature along with monitoring alarms. Programmable registers can be used to specify temperature events and critical boundaries. An EVENT# pin is used to signal when different conditions occur based on how the registers are defined. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (1:0), which provide four unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VIN, VOUT II VDD supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE# S#, test = 0V) CKE, ODT, BA CK0, CK0# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial -0.5 -0.5 -5 +2.3 +2.3 +5 V V A -250 -10 -10 +250 +10 +10 A -36 0 -40 0 -40 +36 +70 +85 +85 +95 A C C C C IOZ IVREF TA TC1 1. Refresh rate is required to double when 85C < TC 95C. 2. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron's Web site. Notes: Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -667 -53E -40E -3 -37E -5E PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Electrical Specifications IDD Specifications Table 9: DDR2 IDD Specifications and Conditions - 2GB Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 8 Symbol -667 -53E -40E Units IDD0 873 738 738 mA IDD1 1,008 963 918 mA IDD2P 126 126 126 mA IDD2Q 603 612 621 mA IDD2N 468 468 423 mA IDD3P 270 270 270 mA 90 90 90 mA IDD3N 603 513 468 mA IDD4W 1,278 1,188 1,008 mA IDD4R 1,323 1,233 1,053 mA IDD5 2,043 1,998 1,953 mA IDD6 126 126 126 mA IDD7 2,628 2,538 2,448 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Electrical Specifications Table 10: DDR2 IDD Specifications and Conditions - 4GB Values shown for MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (512 Meg x 8) component data sheet Parameter/Condition tCK tCK Operating one bank active-precharge current: = (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -667 -53E -40E Units IDD0 1,017 927 927 mA IDD1 1,422 1,062 1,062 mA IDD2P 144 144 144 mA IDD2Q 567 576 585 mA IDD2N 657 567 522 mA IDD3P 360 315 270 mA 90 90 90 mA IDD3N 612 522 477 mA IDD4W 1,422 1,242 1,197 mA IDD4R 1,647 1,656 1,665 mA IDD5 2,637 2,457 2,367 mA IDD6 144 144 144 mA IDD7 3,177 2,772 2,772 mA t PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Register and PLL Specifications Register and PLL Specifications Table 11: Register Specifications SSTU32872 devices or equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) SSTL_18 VREF(DC) + 125 - mV DC low-level input voltage VIL(DC) SSTL_18 - VREF(DC) - 125 mV AC high-level input voltage VIH(AC) SSTL_18 VREF(DC) + 250 - mV AC low-level input voltage VIL(AC) Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins All pins SSTL_18 - VREF(DC) - 250 mV 1.2 - -5 - - - 0.5 5 200 80 V V A A mA - Varies by manufacturer A - Varies by manufacturer A 2.5 3.5 pF - Varies by manufacturer pF Output high voltage Output low voltage Input current Static standby Static operating VOH VOL II IDD IDD Dynamic operating (clock tree) IDDD Dynamic operating (per each input) IDDD Input capacitance (per device, per pin) Input capacitance (per device, per pin) CI Notes: PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN CI LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle All inputs VI = VREF 350mV; except RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Register and PLL Specifications Table 12: PLL Specifications CUA845 device or JESD82-21 equivalent Parameter DC high-level input voltage DC low-level input voltage Input voltage (limits) Input differential-pair cross voltage Input differential voltage Input differential voltage Input current Output disabled current Static supply current Dynamic supply Pins Condition Min Max Units VIH VIL VIN VIX OE, OS, CK, CK# OE, OS, CK, CK# LVCMOS LVCMOS 0.65 x VDD - -0.3 (VDD/2) 0.15 0.3 0.6 -10 -250 100 - - - 0.35 x VDD VDD + 0.3 (VDD/2) + 0.15 VDD + 0.4 VDD + 0.4 10 250 - 500 300 V V V V V V A A A A mA 2 3 pF VID(DC) VID(AC) II IODL IDDLD IDD CIN Input capacitance Table 13: Symbol Differential input Differential input Differential input OE, OS, FBIN, FBIN# VI = VDD or VSS CK, CK# VI = VDD or VSS OE = L, VODL = 100mV CL = 0pf n/a CK and CK# = 410 MHZ all output are open (not connected to a PCB) Each input VI = VDD or VSS PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN Symbol Min Max Units tL - 1.0 30 0.0 2.0 15 4 33 -0.50 - s V/ns kHz % MHz slr(i) 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Temperature Sensor The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD. This sensor complies with the JEDEC standard JC-42.4. Table 14: Temperature Sensor Specifications All voltages referenced to VSS Parameter/Condition Supply voltage Average operating supply current Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Logic input current Symbol Min Max Units VDD +3.0 - +2.1 - - -5 -5 -40 +3.6 +500 - +0.8 +0.4 +5 +5 +125 V A V V V A A C Symbol Min Max Units tBUF 4.7 - 300 4.0 4 4.7 - - 250 4.7 4 10 - 300 - - 50 - 1 400 - - - 100 s ns ns s s s s kHz ns s s kHz VIH VIL VOL IIH IIL Temperature sensing range Table 15: Temperature Sensor AC Timing Parameter/Condition Time the bus must be free before a new transition can start SDA and SCL fall time Data hold time Start condition hold time Clock HIGH period Clock LOW period SDA and SCL rise time SCL clock frequency Data setup time Start condition setup time Stop condition setup time Clock frequency tF tHD:DAT tHD:STA tHIGH tLOW tR fSCL tSU:DAT tSU:STA tSU:STO f CK EVENT# Pin The temperature sensor also adds the EVENT# pin. Not used by the SPD, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor's configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. The open-drain output of EVENT# under the three separate operating modes is illustrated in Figure 3 on page 13. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor The interrupt mode allows software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and only returns to the logic HIGH state when the temperature falls outside the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode and the critical EVENT# cannot be cleared through software. SM Bus Slave Subaddress Decoding The temperature sensor's physical address differs from current SPD device physical addresses: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three slave subaddress pins and RW# bit is the READ/WRITE flag. If the slave base address is fixed for the SPD and temperature sensor, then the pins set the subaddress bits of the slave address, allowing the devices to be located anywhere within the eight slave address locations. For example, they could be set from 30h to 3Eh. Figure 3: EVENT# Pin Functionality Temperature Critical Hysteresis affects these trip points Alarm window (MAX) Alarm window (MIN) Clears event Time EVENT# interrupt mode EVENT# comparator mode EVENT# critical temperature only mode PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Table 16: Temperature Sensor Registers Name Pointer register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Address Power-On Default Not applicable 0x00 0x01 0x02 0x03 0x04 0x05 Undefined 0x0001 0x0000 0x0000 0x0000 0x0000 Undefined Pointer Register The pointer register selects which of the 16-bit registers is being accessed in subsequent READ and WRITE operations. This register is a write-only register. Table 17: Pointer Register Bits 0-7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 Register select Register select Register select Register select Table 18: Pointer Register Bits 0-2 Descriptions Bit2 Bit1 Bit0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Register Capability register Configuration register Alarm temperature upper boundary register Alarm temperature lower boundary register Critical temperature register Temperature register Capability Register The capability register indicates the features and functionality supported by the temperature sensor. This register is a read-only register. Table 19: Bit15 Capability Register Bits Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 RFU RFU RFU RFU RFU RFU RFU RFU Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and critical temperature PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Table 20: Bit Capability Register Bit Descriptions Description 0 1 2 4:3 15:5 Basic capability 1: Has alarm and critical trip point capabilities Accuracy 0: 2C over the active range and 3C over the monitor range 1: 1C over the active range and 2C over the monitor range Wider range 0: Temperatures lower than 0C are clamped to a binary value of 0 1: Temperatures below 0C can be read Temperature resolution 00: 0.5C LSB 01: 0.25C LSB 10: 0.125C LSB 11: 0.0625C LSB 0: Must be set to zero Configuration Register Table 21: Configuration Register Bits 0-15 Bit15 Bit14 Bit13 Bit12 Bit11 RFU RFU RFU RFU RFU Bit7 Bit6 Bit5 Bit4 Bit3 Critical lock bit Alarm lock bit Clear event Event output status Event output control Table 22: Bit 0 1 2 3 4 5 Bit10 Bit9 Hysteresis Bit2 Bit8 Shutdown mode Bit1 Critical event Event polarity only Bit0 Event mode Configuration Register Bit Descriptions Description Notes Event mode 0: Comparator mode 1: Interrupt mode EVENT# polarity 0: Active LOW 1: Active HIGH Critical event only 0: EVENT# trips on alarm or critical temperature event 1: EVENT# trips only if critical temperature is reached Event output control 0: Event output disabled 1: Event output enabled Event status 0: EVENT# has not been asserted by this device 1: EVENT# is being asserted due to an alarm window or critical temperature condition Clear event 0: No effect 1: Clears the event when the temperature sensor is in the interrupt mode Cannot be changed if either of the lock bits is set. PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 15 Cannot be changed if either of the lock bits is set. This is a read-only field in the register; the event causing the event can be determined from the read temperature register. This is a write-only field in the register and is self clearing. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Table 22: Bit 6 7 8 10:9 Configuration Register Bit Descriptions (continued) Description Notes Alarm window lock bit 0: Alarm trips are not locked and can be changed 1: Alarm trips are locked and cannot be changed Critical trip lock bit 0: Critical trip is not locked and can be changed 1: Critical trip is locked and cannot be changed Shutdown mode 0: Enabled 1: Shutdown Hysteresis enable 00: Disable 01: Enable at 1.5C 10: Enable at 3C 11: Enable at 6C The shutdown mode is a power saving mode that disables the temperature sensor. When enabled, a hysteresis is applied to temperature movement around the trip points. As an example, if the hysteresis register is enabled to a delta of 6C, the preset trip points will toggle when the temperature reaches the programmed value. These values will reset when the temperature drops below the trip points minus the set hysteresis level. In this case, this would be critical temperature minus 6C. The hysteresis is applied to both the above alarm window and the below alarm window bits found in the read-only temperature register. EVENT# is also affected by this register. Figure 4: Hysteresis TH1 1 3 TH - Hyst TL 2 3 2 TL - Hyst Below window bit Above window bit Notes: Table 23: 1. TH is the value set in the alarm temperature upper boundary trip register. 2. TL is the value set in the alarm temperature lower boundary trip register. 3. Hyst is the value set in the hysteresis bits of the configuration register. Hysteresis Condition Sets Clears Below Alarm Window Bit Temperature gradient Falling Rising PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN Above Alarm Window Bit Critical temperature TL - Hyst TL 16 Temperature gradient Rising Falling Critical temperature TH TH - Hyst Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Temperature Format The temperature trip point registers and temperature readout register use a "2's complement" format to enable negative numbers. The least significant bit (LSB) is equal to 0.0625C or 0.25C depending on which register is referenced. As an example, assuming an LSB of 0.0625C: * A value of 0x018C would equal 24.75C * A value of 0x06C0 would equal 108C * A value of 0x1E74 would equal -24.75C Upper Temperature Boundary Register The upper temperature boundary register is used to set the maximum value of the alarm window. The least significant bit (LSB) for this register is 0.25C. All RFU bits in the register will always report zero. Table 24: Upper Temperature Boundary Register Bits 15 14 13 12 11 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window upper boundary temperature Lower Temperature Boundary Register The lower temperature boundary register is used to set the minimum value of the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 25: Lower Temperature Boundary Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Alarm window lower boundary temperature Critical Temperature Register The critical temperature register is used to set the maximum temperature above the alarm window. The LSB for this register is 0.25C. All RFU bits in the register will always report zero. Table 26: Critical Temperature Register Bits 15 14 13 12 0 0 0 MSB 11 10 9 8 7 6 5 4 3 2 1 0 LSB RFU RFU Critical temperature trip point PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Temperature Sensor Temperature Register The temperature register is a read-only register that provides the current temperature detected by the temperature sensor. The LSB for this register is 0.0625C with a resolution of 0.0625C. The most significant bit (MSB) is 128C in the readout section of this register. The upper three bits of the register are used to monitor the trip points that are set in the previous three registers. Table 27: Temperature Register Bits 15 14 13 12 Above critical trip Above alarm window Below alarm window MSB Table 28: 11 10 9 8 5 4 3 2 1 0 LSB Temperature Register Bit Descriptions Description 13 Below alarm window 0: Temperature is equal to or above the lower boundary 1: Temperature is below alarm window Above alarm window 0: Temperature is equal to or below the upper boundary 1: Temperature is above alarm window Above critical trip point 0: Temperature is below critical trip point 1: Temperature is above critical trip point 15 6 Temperature BIT 14 7 PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Serial Presence-Detect Serial Presence-Detect Table 29: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA SPD input leakage current: VIN = GND to VDD SPD output leakage current: VOUT = GND to VDD SPD standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Average temperature sensor current Table 30: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 3.0 2.1 -0.6 - 0.10 0.05 1.6 0.4 2 - 3.6 VDDSPD + 0.5 0.8 0.4 3 3 4 1 3 500 V V V V A A A mA mA A Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s kHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT t SU:STA tSU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Serial Presence-Detect Table 31: Serial Presence-Detect Matrix Byte Description 0 1 2 3 4 5 6 7 8 9 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 SDRAM access from clock, tAC (CL = MAX value, see byte 18) 11 12 13 14 15 16 17 18 Module configuration type Refresh rate/type SDRAM device width (primary SDRAM) Error-checking SDRAM data width Reserved Burst lengths supported Number of banks on SDRAM device CAS latencies supported 19 20 21 22 Module thickness DDR2 DIMM type SDRAM module attributes SDRAM device attributes: weak driver (01) or 50 ODT (03) SDRAM cycle time, tCK, MAX CL - 1 23 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 27 28 29 30 SDRAM access from CK, tAC, MAX CL - 2 MIN row precharge time, tRP MIN row active to row active, tRRD MIN RAS#-to-CAS# delay, tRCD MIN active-to-precharge time, tRAS 31 32 Module rank density Address and command setup time, tISb PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN Entry (Version) 2GB 4GB 128 256 DDR2 SDRAM 14 or 15 10 30mm, dual rank 72 0 SSTL 1.8V -667 -53E -40E -667 -53E -40E ECC 7.81s/SELF 8 8 0 4, 8 8 -667 (5, 4, 3) -53E/-40E (4, 3) 80 08 08 0E 0A 71 48 00 05 30 3D 50 45 50 60 02 82 08 08 00 0C 08 38 18 01 04 04 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 01 20 25 35 80 08 08 0F 0A 71 48 00 05 30 3D 50 45 50 60 02 82 08 08 00 0C 08 38 18 01 04 04 03 01 3D 50 45 50 60 50 00 45 00 3C 1E 3C 2D 28 02 20 25 35 SODIMM 1 PLL, 1 Reg -667 -53E/-40E -667 -53E/-40E -667 -53E -40E -667 -53E/-40E -667 -53E/-40E -667/-53E -40E 2GB, 4GB -667 -53E -40E 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Serial Presence-Detect Table 31: Serial Presence-Detect Matrix (continued) Byte Description 33 Address and command hold time, 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 39 40 41 READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 MIN active-to-active/refresh time, tRC1 42 MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period, tRFC SDRAM device MAX cycle time, tCK (MAX) SDRAM device MAX DQS-DQ skew time, tDQSQ 43 44 45 Entry (Version) 2GB 4GB -667 -53E -40E -667/-53E -40E -667 -53E -40E 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 06 3C 37 7F 27 37 47 10 15 17 22 27 3C 1E 28 1E 00 06 3C 37 C5 80 18 1E 23 22 28 2D 0F 00 12 24 CF 36 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 80 18 1E 23 22 28 2D 0F 00 12 C6 17 CE 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF tIH b -667/-53E -40E -667/-53E -40E -667 -53E -40E -667 -53E -40E SDRAM device MAX read data hold skew factor, tQHS 46 47-61 62 63 64 65-71 72 73-90 91 92 93 94 95-98 99-127 128-255 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0-62 Release 1.2 -667 -53E -40E MICRON (continued) 1-12 - 1-9 0 - - - Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data Reserved for customer-specific data Notes: PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM Module Dimensions Module Dimensions Figure 5: 200-Pin DDR2 SORDIMM 3.80 (0.150) MAX Front view 67.75 (2.667) 67.45 (2.656) U3 2.0 (0.079) R (2X) U7 U5 1.0 (0.039) R (2X) 1.80 (0.071) (2X) U1 U2 U8 30.15 (1.187) 29.85 (1.175) U9 20.0 (0.787) TYP U6 6.0 (0.236) TYP 0.50 (0.0197) R 2.00 (0.079) TYP 1.10 (0.043) 0.90 (0.035) 0.60 (0.024) TYP 0.45 (0.018) TYP PIN 199 PIN 1 63.60 (2.504) TYP Back view U10 U11 U12 U13 U14 10.00 (0.394) TYP 3.50 (0.138) TYP 4.2 (0.165) TYP PIN 200 1.0 (0.039) TYP PIN 2 47.4 (1.87) TYP 11.4 (0.45) TYP 16.26 (0.64) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and TwinDie are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef828665bd/Source: 09005aef828665a3 HTS18C_256_512x72RH.fm - Rev. B 5/08 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved.