MT18HTS25672PY-667E1 - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

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DDR2 SDRAM SORDIMM

MT18HTS25672RH – 2GB

MT18HTS51272RH – 4GB

For component data sheets, refer to Micron’s Web site: www.micron.com

Features

• 200-pin, small-outline registered, dual in-line

memory module (SORDIMM)

• Fast data transfer rates: PC2-3200, PC2-4200,

or PC2-5300

• 2GB (256 Meg x 72), 4GB (512 Meg x 72)

• S upports ECC error detection and correction

•V

DD = VDDQ = +1.8V

•V

DDSPD = +3.0V to +3.6V

• JEDEC-standar d 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

• Multipl e internal device banks for concurrent

operation

• Programmable CAS# latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Pro grammable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• PLL to reduce system clock line loading

• Gold edge contacts

• Dual rank, using TwinDie™ devices

•I

2C temperature sensor

Figure 1: 200-Pin SORDIMM (MO-224)

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

Options Marking

• Operating temperature1

–Commercial (0°C ≤ TA ≤ +70°C) None

–Industrial (–40°C ≤ TA ≤ +85°C) I

•Package

–200-pin DIMM (Pb-free) Y

• Frequency/CAS latency2

–3.0ns @ CL = 5 (DDR2-667) -667

–3.75ns @ CL = 4 (DDR2-533) -53E

–5.0ns @ CL = 3 (DDR2-400) -40E

•PCB height

– 30mm (1.18in)

PCB height: 30mm (1.18in)

Table 1: Key Timing Parameters

Speed

Grade Industry Nomenclature

Data Rate (MT/s) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 5 CL = 4 CL = 3

-667 PC2-5300 667 533 400 15 15 55

-53E PC2-4200 – 533 400 15 15 55

-40E PC2-3200 – – 400 15 15 55

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Features

Notes: 1. Data sheets for the base devices can be found on Micron ’s Web si te.

2. All part numbers end with a two-place code (not shown), designating component and PCB

revisions. Consult factory for current revision codes. Example: MT18HTS25672PY-667E1.

Ta ble 2: Addressing

Parameter 2GB 4GB

Refresh count 8K 8K

Row address 16K (A0–A13) 32K (A0–A14)

Device bank address 8 (BA0–BA2) 8 (BA0–BA2)

Device page size per bank 1KB 1KB

Device configuration 2Gb TwinDie (256 Meg x 8) 4Gb TwinDie (512 Meg x 8)

Column address 1K (A0–A9) 1K (A0–A9)

Module rank address 2 (S0#, S1#) 2 (S0#, S1#)

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H256 M8THN,1 2Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Latency

(CL-tRCD-tRP)

MT18HTS25672RH(I)Y-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT18HTS25672RH(I)Y-53E__ 2GB 256 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT18HTS25672RH(I)Y-40E__ 2GB 256 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Table 4: Part Numbers and Timing Parameters – 4GB Modules

Base device: MT47H512 M8THM,1 4Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Latency

(CL-tRCD-tRP)

MT18HTS51272RH(I)Y-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT18HTS51272RH(I)Y-53E__ 4GB 512 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT18HTS51272RH(I)Y-40E__ 4GB 512 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Assignments and Descriptions

Ta ble 5: Pin Assignments

200-Pin SORDIMM Front 200-Pin SORDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REF 51 DQ18 101 VDD 151 VSS 2VSS 52 VSS 102 A6 152 VSS

3 DQ0 53 DQ19 103 A5 153 DQS5# 4 DQ4 54 DQ28 104 A4 154 DM5

SS 55 VSS 105 A3 155 DQS5 6 DQ5 56 DQ29 106 VDD 156 VSS

7 DQ1 57 DQ24 107 A2 157 VSS 8VSS 58 VSS 108 A1 158 DQ46

9 DQS0# 59 DQ25 109 VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47

11 DQS0 61 VSS 111 A10 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS

13 VSS 63 DQS3# 113 BA0 163 VSS 14 DQ6 64 DQ30 114 VDD 164 DQ52

15 DQ2 65 DQS3 115 RAS# 165 DQ48 16 DQ7 66 DQ31 116 WE# 166 DQ53

17 DQ3 67 VSS 117 VDD 167 DQ49 18 VSS 68 VSS 118 S0# 168 VSS

19 VSS 69 DQ26 119 CAS# 169 VSS 20 DQ12 70 CB4 120 ODT0 170 DM6

21 DQ8 71 DQ27 121 S1# 171 DQS6# 22 DQ13 72 CB5 122 A13 172 VSS

23 DQ9 73 VSS 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD 174 DQ54

25 VSS 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK0 176 DQ55

27 DQS1# 77 CB1 127 NC 177 DQ50 28 VSS 78 VSS 128 CK0# 178 VSS

29 DQS1 79 VSS 129 DQ32 179 DQ51 30 DQ14 80 CB6 130 VSS 180 DQ60

31 VSS 81 DQS8# 131 VSS 181 VSS 32 DQ15 82 CB7 132 DQ36 182 DQ61

33 DQ10 83 DQS8 133 DQ33 183 DQ56 34 VSS 84 VSS 134 DQ37 184 VSS

35 DQ11 85 VSS 135 DQS4# 185 DQ57 36 DQ20 86 CB2 136 VSS 186 DM7

37 VSS 87 CKE0 137 DQS4 187 VSS 38 DQ21 88 CB3 138 DM4 188 DQ62

39 DQ16 89 CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS

41 DQ17 91 EVENT# 141 DQ34 191 DQS7 42 RESET# 92 BA2 142 DQ38 192 DQ63

43 VSS 93 VDD 143 DQ35 193 DQ58 44 DM2 94 A14 144 DQ39 194 SDA

45 DQS2# 95 A12 145 VSS 195 VSS 46 VSS 96 A11 146 VSS 196 SCL

47 DQS2 97 A9 147 DQ40 197 DQ59 48 DQ22 98 VDD 148 DQ44 198 SA1

49 VSS 99 A7 149 DQ41 199 VDDSPD 50 DQ23 100 A8 150 DQ45 200 SA0

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Pin Assignments and Descriptions

Table 6: Pin Descriptions

Symbol Type Description

ODT0, ODT1 Input

(SSTL_18) On-die termination: ODT (registered HIGH) enables termination resistance internal to the

DDR2 SDRAM. When enabled, ODT is only applied to each of the fo llowing pins: DQ, DQS,

DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command.

CK0, CK0# Input

(SSTL_18) Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and ne gative edge of CK#. Outp ut data

(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE0,

CKE1 Input

(SSTL_18) Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates

clocking circuitry on the DDR2 SDRAM.

S0#,

S1# Input

(SSTL_18) Chip select: S# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when S# is registered HIGH. S# provides for external rank

selection on systems with multiple ranks. S# is considered part of the command code.

RAS#, CAS#,

WE# Input

(SSTL_18) Command inputs: RAS#, CAS#, and WE# (along with S#) define the command bein g

entered.

BA0–BA2 Input

(SSTL_18) Bank address inputs: BA0–BA2 define to which device bank an ACTIVE, READ, WRI TE, or

PRECHARGE command is being applied. BA0–BA2 define which mode register, including MR,

EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

A0–A13 (2GB),

A0–A14 (4GB) Input

(SSTL_18) Address inputs: Provide the row address for ACTIVE commands, and the column address

and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 sampled during a PRE CHARGE command

determines whether the PRECHARGE applies to one devi ce bank (A10 LOW, device bank

selected by BA0–BA2) or all device banks (A10 HIGH). The address inputs also provide the op-

code during a LOAD MODE command.

DM0–DM8 Input

(SSTL_18) Input data mask: DM is an input mask signal for write data. Input data is masked when DM

is sampled HIGH along with that input data during a WRITE access. DM is sampled on both

edges of DQS. Although DM pins are input-only, the DM loading is designed to match that

of DQ and DQS pins.

SCL Input

(SSTL_18) Serial clock: SCL is used to synchronize the presence-detect and temperature sensor data

transfer to and from the module.

SA0–SA1 Input

(SSTL_18) Serial address inputs: These pins are used to configure the presence-detect and

temperature sensor devices.

RESET# Input

(LVCMOS) Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be

used during power-up to ensure that CKE is LOW and DQs are High-Z.

DQ0–DQ63 I/O

(SSTL_18) Data input/output: Bidirectional data bus.

CB0–CB7 I/O

(SSTL_18) Check bits.

DQS0–DQS8 I/O

(SSTL_18) Data strobe: Output with read data, input with write data for source synchronous

operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used

when differential data strobe mode is enabled via th e LOA D MOD E com m a nd .

SDA I/O

(SSTL_18) Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of

the presence-detect and temperature sensor device s.

EVENT# Output Temperature sensor alarm output.

VDD Supply Power supply: +1.8V ±0.1V.

VREF Supply SSTL_18 reference voltage.

VSS Supply Ground.

VDDSPD Supply Serial EEPROM and temperature sensor positive power supply: +3.0V to +3.6V.

NC – No connect: These pins should be left unconnected.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1b

DM CS# DQS DQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U8b

U8t

DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U14b

DM CS# DQS DQS#

U14t

DM CS# DQS DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U2b

DM CS# DQS DQS#

U2t

DM CS# DQS DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U13b

DM CS# DQS DQS#

U13t

DM CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U11b

U11t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U9b

U6t

DM CS# DQS DQS# DM CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U10b

U10t

DM CS# DQS DQS# DM CS# DQS DQS#

DQS0#

DQS0

DM0

RS0#

RS1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

U12b

DM CS# DQS DQS#

U12t

DM CS# DQS DQS#

DQS8#

DQS8

DM8

VREF

VSS

DDR2 SDRAM

VDD

VDDSPD SPD EEPROM, temperature sensor

DDR2 SDRAM

PLL

CK0

CK0#

U6 DDR2 SDRAM x 2

DDR2 SDRAM x 2

Rank0 = U1b, U2b, U8b–U14b

Rank1 = U1t, U2t, U8t–U14t

SPD EEPROM

A1 A2

SA0

Event#

SA1

SDA

SCL

Temp Sensor

A1 A2

SA0 SA1

EVT

S0#

S1#

BA0–BA2

A0–A13/A14

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

RS0#: Rank0

RS1#: Rank1

RBA0–RBA2: DDR2 SDRAM

RA0–RA13/RA14: DDR2 SDRAM

RRAS#: DDR2 SDRAM

RCAS#: DDR2 SDRAM

RWE#: DDR2 SDRAM

RCKE0: Rank0

RCKE1: Rank1

RODT0: Rank0

RODT1: Rank1

VSS VSS

VSS

RESET#

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

General Description

The MT18HTS25672RH and MT18HTS51272RH DDR2 SDRAM modules are high-speed,

CMOS, dynamic random-access 2GB and 4GB memory modules organized in a x72

configuration. DDR2 SDRAM modules use internally configured 8-bank

(2Gb TwinDie and 4Gb TwinDie) DDR2 SDRAM devices.

DDR2 SDRAM modules use double data ra te architecture to achieve high-speed opera-

tion. The double data rate archi t ecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consis ts of a single

4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-

sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) i s transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands are registered at every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of DQS, as well as to both

edges of CK.

DDR2 SDRAM modules operate in registered mode, wher e the command/add ress input

signals ar e latched in the regi sters on the risi ng clock ed ge and sent to the DDR2 SDRAM

devices on the following rising clock edge (data access is delayed by one clock cycle). A

phase-lock lo op (PLL) on the module receives and redrives the diffe rential clock sign al s

(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,

command, control, and clock signal loadin g by isolating DRA M from the sys te m

controller. PLL clock timing is defined b y JEDEC specifications and ensur ed b y use of the

JEDEC clock reference board. Registered mode will add one clock cycle to CL.

Temperature Sensor

An on-board temperature sensor provides the ability to monitor the module tempera-

ture along with monitoring alarms. Programmable registers can be used to specify

temperature events and cr itical boundaries. An EVENT# pin is used to signal when

different conditions occur based on how the registers are defined.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate seri al presence-d etect (SPD). The SPD functio n is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains

256 bytes . The first 128 b ytes ar e pr ogrammed b y Micron to identify the module type and

various SDRAM organizat ions and timing parameters. The remain ing 128 bytes of

storage are available for use by the customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM device occur via a standar d I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (1:0), which

provide four unique DIMM/EEPROM addresses. Wr ite protect (WP) is tied to VSS on the

module, permanently disabling hardware write protect.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

S tresses greater than those listed in Table 7 may cause permane nt damage to the devi ce.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

Notes: 1. Refresh rate is required to double when 85°C < TC ≤ 95°C.

2. For fur th e r informatio n, r ef er to technical note TN-00-08: Thermal Applications, available

on Micron’s Web site.

Input Capacitance

Micron encourages designers to simulate the performance of the module to achieve

optimum values. Simulations are significantly more accurate and realistic than a gross

estimation of module capacitance when inductance and delay parameters associated

with trace lengths are used in simulations. JEDEC modules are currently designed using

simulations to cl ose timing budget s.

Component AC Timing and Operating Conditions

Re commended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades, as shown in Table 8.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.5 +2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 +2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under

test = 0V)

Address inputs

RAS#, CAS#, WE# S#,

CKE, ODT, BA

–5 +5 µA

CK0, CK0# –250 +250

DM –10 +10

IOZ Output leakage current; 0V ≤ V OUT ≤ VDDQ; DQs and

ODT are disabled DQ, DQS, DQS# –10 +10 µA

IVREF VREF leakage current; VREF = Valid VREF level –36 +36 µA

TAModule ambient operating temperature Commercial 0+70°C

Industrial –40 +85 °C

TC1DDR2 SDRAM component case operating

temperature2Commercial 0+85°C

Industrial –40 +95 °C

Table 8: Module and Component Speed Grades

Module Speed Grade Component Speed Grade

-667 -3

-53E -37E

-40E -5E

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

IDD Specifications

Table 9: DDR2 IDD Specifications and Conditions – 2GB

Values shown for MT 47H256M8THN DDR2 SDRAM only and are computed from values specified in the

2Gb TwinDie (256 Meg x 8) component data sheet

Parameter/Condition Symbol -667 -53E -40E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

IDD0 873 738 738 mA

Operating one bank active-read-pr echarge current: IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Ad dress

bus inputs are switching; Data pattern is same as IDD4W

IDD1 1,008 963 918 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD);

CKE is LOW ; Other control and address bus inputs are stable; Data bus inputs

are floating

IDD2P 126 126 126 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;

Data bus inputs are floating

IDD2Q 603 612 621 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and ad dress bus inputs are switching; Data

bus inputs are switching

IDD2N 468 468 423 mA

Active power-down current: All device banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address bus

inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0 IDD3P 270 270 270 mA

Slow PDN exit

MR[12] = 1 90 90 90 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Other control and address bus inputs are switching; Data bus

inputs are switching

IDD3N 603 513 468 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data bus inputs are switching

IDD4W 1,278 1,188 1,008 mA

Operating burst read current: All device banks open; Continuous burst

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

IDD4R 1,323 1,233 1,053 mA

Burst refresh current: tCK = tCK (IDD); REFRESH command at every

tRFC (IDD) interval; CKE i s HIGH, S# is HIGH between valid commands; Other

control and address bus inputs are switching; Data bus inputs are switching

IDD5 2,043 1,998 1,953 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Data bus inputs are floating IDD6 126 126 126 mA

Operating bank interleave read current: All device banks interleaving

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are stable

during deselects; Data bus inputs are switching

IDD7 2,628 2,538 2,448 mA

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Electrical Specifications

Table 10: DDR2 IDD Specifications and Conditions – 4GB

Values shown for MT 47H512M8THM DDR2 SDRAM only and are computed from values specified in the

4Gb TwinDie (512 Meg x 8) component data sheet

Parameter/Condition Symbol -667 -53E -40E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN (I DD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

IDD0 1,017 927 927 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data pattern is same as IDD4W

IDD1 1,422 1,062 1,062 mA

Precha rge power-down curre nt: All device banks idle; tCK = tCK (IDD); CKE

is LOW; Other control and address bus inputs are stable; Data bus inputs are

floating

IDD2P 144 144 144 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;

Data bus inputs are floating

IDD2Q 567 576 585 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and ad dress bus inputs are switching; Data

bus inputs are switching

IDD2N 657 567 522 mA

Active power-down current: All device banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address bus

inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0 IDD3P 360 315 270 mA

Slow PDN exit

MR[12] = 1 90 90 90 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Other control and address bus inputs are switching; Data bus

inputs are switching

IDD3N 612 522 477 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD4W 1,422 1,242 1,197 mA

Operating burst read current: All device banks open; Continuous burst

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

IDD4R 1,647 1,656 1,665 mA

Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC

(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other

control and address bus inputs are switching; Data bus inputs are switching

IDD5 2,637 2,457 2,367 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Data bus inputs are floating IDD6 144 144 144 mA

Operating bank interleave read current: All device banks interleaving

reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are stable

during deselects; Data bus inputs are switching

IDD7 3,177 2,772 2,772 mA

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Notes: 1. Timing and switching specifications for the register listed above are critical for proper oper-

ation of the DDR2 SDRAM registered DIMMs . These are meant to be a subset of the param-

eters for the specific device used on the module. Detailed information for this register is

available in JEDEC standard JESD82.

Table 11: Register Specifications

SSTU32872 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage VIH(DC) Address,

control,

command

SSTL_18 VREF(DC) + 125 – mV

DC low-level

input voltage VIL(DC) Address,

control,

command

SSTL_18 – VREF(DC) - 125 mV

AC high-level

input voltage VIH(AC) Address,

control,

command

SSTL_18 VREF(DC) + 250 – mV

AC low-level

input voltage VIL(AC) Address,

control,

command

SSTL_18 – VREF(DC) - 250 mV

Output high voltage VOH Parity ou tput LVCMOS 1.2 – V

Output low voltage VOL Parity output LVCMOS – 0.5 V

Input current IIAll pins VI = VDDQ or VSSQ–5 5µA

Static standby IDD All pins RESET# = VSSQ (IO = 0) – 200 µA

Static operating IDD All pins RESET# = VSSQ;

VI = VIH(AC) or VIL(DC)

IO = 0

–80mA

Dynamic operating

(clock tree) IDDD n/a RESET# = VDD, VI = V IH(AC) or

VIL(AC), IO = 0; CK and CK#

switching 50% duty cycle

–Varies by

manufacturer µA

Dynamic operating

(per each input) IDDD n/a RESET# = VDD, VI = V IH(AC) or

VIL(AC), IO = 0; CK and CK#

switching 50% duty cycle;

One data input sw itching at

tCK/2, 50% duty cycle

–Varies by

manufacturer µA

Input capacitance

(per device, per pin) CIAll inputs

except RESET# VI = VREF ±350mV;

VDDQ = 1.8V 2.5 3.5 pF

Input capacitance

(per device, per pin) CIRESET# VI = VDDQ or VSSQ–Varies by

manufacturer pF

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.

This is a subset of parameters for the specific PLL used.

Table 12: PLL Specifications

CUA845 device or JESD82-21 equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level input voltage VIH OE, OS, CK, CK# LVCMOS 0.65 × VDD –V

DC low-level input voltage VIL OE, OS, CK, CK# LVCMOS – 0.35 × VDD V

Input voltage (limits) VIN –0.3 VDD + 0.3 V

Input differential-pair cross

voltage VIX Differential input (VDD/2) -

0.15 (VDD/2) +

0.15 V

Input differential voltage VID(DC) Differential inp ut 0.3 VDD + 0.4 V

Input differential voltage VID(AC) Differential inp ut 0.6 VDD + 0.4 V

Input current IIOE, OS, FBIN, FBIN# VI = VDD or VSS –10 10 µA

CK, CK# VI = VDD or VSS –250 250 µA

Output disabled current IODL OE = L, VODL = 100mV 100 – µA

Static supply current IDDLD C

L = 0pf – 500 µA

Dynamic supply IDD n/a CK and CK# = 410 MHZ

all output are open

(not connected to a PCB )

– 300 mA

Input capacitance CIN Each input VI = VDD or VSS 23pF

Table 13: PLL Clock Driver Timing Requirements and Switching Characteristics

Parameter Symbol Min Max Units

Stabilization time tL–15µs

Input clock slew rate slr(i) 1.0 4 V/ns

SSC modulation frequency 30 33 kHz

SSC clock input frequ ency deviation 0.0 –0.50 %

PLL loop bandwi dth (–3dB from unity gain) 2.0 – MHz

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

The temperature sensor continuousl y monitors the modul e’s temperature and can be

read back at any time over the I2C bus shared with the SPD. This sensor complies with

the JEDEC standard JC-42.4.

EVENT# Pin

The temperature sensor also adds the EVENT# pin. Not used by the SPD, EVENT# is a

temperature sensor output used to flag critical events that can be set up in the sensor’s

configuration register.

EVENT# has thre e defined modes of operati o n: interrupt mode, compare mode , and

critical temperature mode. The open-drain output of EVENT# under the three separate

operating modes is illustrated in Figure 3 on page13. Event thresholds are programmed

in the 0x01 register using a hysteresis. The alarm window provides a comparison

window, with upper and lower limits set in the alarm upper boundary register and the

alarm lower boundary register, respectively. When the alarm window is enabled,

EVENT# will trigger whenever the temperature is outside the MIN or MAX va lues set by

the user.

Table 14: Temperature Sensor Specifications

All voltages referen ce d to VSS

Parameter/Condition Symbol Min Max Units

Supply voltage VDD +3.0 +3.6 V

Average operating supply current – +500 µA

Input high voltage: Logic 1; All inputs VIH +2.1 – V

Input low voltage: Logic 0; All inputs VIL –+0.8V

Output low voltage: IOUT = 3mA VOL –+0.4V

Logic input current IIH –5 +5 µA

IIL –5 +5 µA

Temperature sensing range –40 +125 °C

Table 15: Temperature Sensor AC Timing

Parameter/Condition Symbol Min Max Units

Time the bus must be free before a new transition can start tBUF 4.7 – µs

SDA and SCL fall time tF – 300 ns

Data hold time tHD:DAT 300 – ns

Start condition hold time tHD:STA 4.0 – µs

Clock HIGH period tHIGH 4 50 µs

Clock LOW period tLOW 4.7 – µs

SDA and SCL rise time tR–1µs

SCL clock frequency fSCL – 400 kHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4 – µs

Clock frequenc y fCK 10 100 kHz

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

The interrupt mode allows software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points ar e set in the configuration r egister b y the

user. This mode triggers the critical temper ature limit and both the MIN and MAX of the

temperature window.

The compar e mode is similar to the interrupt mode, except EVENT # cannot be reset by

the user and only returns to the logic HIGH state when the temperature falls outside the

programmed thresholds.

Critical te m perature mode tr iggers EVENT# only when the te mperature has exceeded

the programmed critical trip point. When the critical trip point has bee n reached, the

temperature sensor goes into comparator mode and the critical EVENT# cannot be

cleare d th rou gh software.

SM Bus Slave Subaddress Decoding

The temperature sensor’s physical address differs from current SPD device physical

addresses: 0011 for A0, A1, A2, and RW# in binary where A2, A1, and A0 are the three

slave subaddress pins and RW# bit is the READ/WRITE flag.

If the slave base address is fixed for the SPD and temperature sensor, then the pins set

the subaddress bits of the slave address, allowing the devices to be located anywhere

within the eight slave address locations. For example, they could be set from 30h to 3Eh.

Figure 3: EVENT# Pin Functionality

Time

Critical

Alarm window (MAX)

Alarm window (MIN)

EVENT#

interrupt mode

EVENT#

comparator mode

EVENT#

critical temperature only mode

Clears event

Hysteresis affects

these trip points

Temperature

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Pointer Register

The pointer r eg ister selec ts which of the 16-bit registers is being accessed in subsequent

READ and WRITE operations. This register is a write-only register.

Capability Register

The capability register indicates the features and functionality supported b y the temper-

ature sensor. This register is a read-only register.

Table 16: Temperature Sensor Registers

Name Address Power-On Default

Pointer register Not applicable Undefined

Capability register 0x00 0x0001

Configuration register 0x01 0x0000

Alarm temperature upper boundary register 0x02 0x0000

Alarm temperature lower boundary register 0x03 0x0000

Critical temperature register 0x04 0x0000

Temperature register 0x05 Undefined

Table 17: Pointer Register Bits 0–7

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

0000Register

select Register

select

Table 18: Pointer Register Bits 0–2 Descriptions

Bit2 Bit1 Bit0 Register

000

Capability register

001

Configuration register

010

Alarm temperature upper boundary register

011

Alarm temperat ure lower boundary register

100

Critical temperature register

101

Temperature re g i s ter

Table 19: Capability Register Bits

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

RFU RFU RFU RFU RFU RFU RFU RFU

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RFU RFU RFU TRES1 TRES0 Wider range Precision Has alarm and

critical

temperature

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Configuration Register

Table 20: Capability Register Bit Descriptions

Bit Description

0Basic capability

1: Has alarm and critical trip point capabilities

1Accuracy

0: ±2°C over the active range and ±3°C over the monitor range

1: ±1°C over the active range and ±2°C over the monitor range

2Wider range

0: Temperatures lower than 0°C are clamped to a binary value of 0

1: Temperatures below 0°C can be read

4:3 Temperature resolution

00: 0.5°C LSB

01: 0.25°C LSB

10: 0.125°C LSB

11: 0.0625°C LSB

15:5 0: Must be set to zero

Table 21: Configuration Register Bits 0–15

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

RFU RFU RFU RFU RFU Hysteresis Shutdown

mode

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Critical lock

bit Alarm lock bit Clear event Event o utput

status Event output

control Critical event

only Event polarity Event mode

Table 22: Configuration Register Bit Descriptions

Bit Description Notes

0Event mode

0: Comparator mode

1: Interrupt mode

Cannot be changed if either of the lock bits is set.

1EVENT# polarity

0: Active LOW

1: Active HIGH

Cannot be changed if either of the lock bits is set.

2Critical event only

0: EVENT# trips on alarm or critical temperature event

1: EVENT# trips only if critical temperature is re ached

3Event output control

0: Event output disabled

1: Event output enabled

4Event status

0: EVENT# has not been asserted by this device

1: EVENT# is being asserted due to an alarm window or

critical temperature cond ition

This is a read-only field in the register; the event

causing the event can be determined from the read

temperature register.

5Clear event

0: No effect

1: Clears the event when the temperature sensor is in the

interrupt mode

This is a write-only field in the register and is self

clearing.

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Figure 4: Hysteresis

Notes: 1. TH is the value set in the alarm temperature upper boundary trip registe r.

2. TL is the value set in the alarm tempera ture lower boundary trip register.

3. Hyst is the value set in the hysteresis bits of th e configuration register.

6Alarm window lock bit

0: Alarm trips are not locked and can be changed

1: Alarm trips are locked and cannot be changed

7Critical trip lock bit

0: Critical trip is not locked and can be changed

1: Critical trip is locked and cannot be changed

8Shutdown mode

0: Enabled

1: Shutdown

The shutdown mode is a power saving mode that

disables the temperature sensor.

10:9 Hysteresi s enable

00: Disable

01: Enable at 1.5°C

10: Enable at 3°C

11: Enable at 6°C

When enabled, a hysteresis is applied to temperature

movement around the trip points. As an example, if

the hysteresis register is enabled to a delta of 6°C, the

preset trip points will toggle when the temperature

reaches the programmed value. These values will

reset when the temperature drops below the trip

points minus the set hysteresis level. In this case, this

would be critical temperature minus 6°C.

The hysteresis is applied to both the above alarm

window and the below alarm window bits found in

the read-only temperature register. EVENT# is also

affected by this register.

Table 23: Hysteresis

Condition Below Alarm Window Bit Above Alarm Window Bit

Temperature gradient Critical temperature Temperature gradient Critical temperature

Sets Falling TL - Hyst Rising TH

Clears Rising TLFalling TH - Hyst

Table 22: Configuration Register Bit Descriptions (continued)

Bit Description Notes

Hyst

Below window bit

Above window bit

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Temperature Format

The temperature trip point registers and temper ature readout register use a

“2’s complement” format to enable negative numbers. The least significant bit (LSB) is

equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example,

assuming an LSB of 0.0625°C:

• A value of 0x018C would equal 24.75°C

• A value of 0x06C0 would equal 108°C

• A value of 0x1E74 would equal –24.75°C

Upper Temperature Boundary Register

The upper temperatur e b oundary register is used to set the maximum val ue of the alarm

window. The least significant bit (LSB) for this register is 0.25°C. All RFU bits in the

Lower Temperature Boundary Register

The lower temperature boundary register is used to set the minimum value of the alarm

window. The LSB for this register is 0.25°C. All RFU bits in the register will always report

zero.

Critical Temperature Register

The critical temperature register is used to set the maximum temperature above the

alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always

report zero.

Table 24: Upper Temperature Boundary Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window upper boundary temperature

Table 25: Lower Temperature Boundary Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Alarm window lower boundary temperature

Table 26: Critical Temperature Register Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000MSB LSB RFU RFU

Critical temperature trip point

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Temperature Sensor

Temperature Register

The temperature r egister is a read -only register that provides the current temperature

detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-

tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this

The upper three bits of the register are used to monitor the trip points that are set in the

previous t hre e re gisters.

Table 27: Temperature Register Bits

15 14 13 12 11 10 9876543210

Above

critical

trip

Above

alarm

window

Below

alarm

window

MSB LSB

Temperature

Table 28: Temp erature Register Bit Descriptions

BIT Description

13 Below alarm window

0: Temperature is equal to or above the lower boundary

1: Temperature is below alarm window

14 Above alarm window

0: Tempera ture is equal to or below the up per boun dary

1: Temperature is above alarm window

15 Above critical trip point

0: Temperature is below critical trip point

1: Tempera ture is above critical trip point

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Serial Presence-Detect

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and

the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition o f a write

sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE

cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-

tance, and the EEPROM does not respond to its slave address.

Table 29: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referen ce d to VSS

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V

Input high voltage: Logic 1; All inputs VIH 2.1 VDDSPD + 0.5 V

Input low voltage: Logic 0; All inputs VIL –0.6 0.8 V

Output low voltage: IOUT = 3mA VOL –0.4V

SPD input leakage current: VIN = GND to VDD ILI 0.10 3 µA

SPD output leakage current: VOUT = GND to VDD ILO 0.05 3 µA

SPD standby current ISB 1.6 4 µA

Power supply current, READ: SCL clock frequency = 100 kHz ICCR0.4 1 mA

Power supply current, WRITE: SCL clock frequency = 10 0 kHz ICCW23mA

Average temperature sensor current –500µA

Table 30: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referen ce d to VSS

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 – µs

Data-out hold time tDH 200 – ns

SDA and SCL fall time tF – 300 ns 2

Data-in hold time tHD:DAT 0 – µs

Start condition hold time tHD:STA 0.6 – µs

Clock HIGH period tHIGH 0.6 – µs

Noise suppression time constant at SCL, SDA inputs tI–50ns

Clock LOW period tLOW 1.3 – µs

SDA and SCL rise time tR–0.3µs2

SCL clock frequency fSCL – 400 kHz

Data-in setup time tSU:DAT 100 – ns

Start condition setup time tSU:STA 0.6 – µs 3

Stop condition setup time tSU:STO 0.6 – µs

WRITE cycle time tWRC – 10 ms 4

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Serial Presence-Detect

Table 31: Serial Presence-Detect Matrix

Byte Description Entry (Version) 2GB 4GB

0Number of SPD bytes used by Micron 128 80 80

1Total number of bytes in SPD device 256 08 08

2Fundamental memory type DDR2 SDRAM 08 08

3Number of row addresses on assembly 14 or 15 0E 0F

4Number of column addresses on assembly 10 0A 0A

5DIMM height and module ranks 30mm, dual rank 71 71

6Module data width 72 48 48

7Reserved 000 00

8Module voltage interface levels SSTL 1.8V 05 05

9SDRAM cycle time, tCK

(CL = MAX value, see byte 18) -667

-53E

-40E

10 SDRAM acce ss fr o m clock, tAC

(CL = MAX value, see byte 18) -667

-53E

-40E

11 Module configuration type ECC 02 02

12 Refresh rate/type 7.81µs/SELF 82 82

13 SDRAM device width (pr imary SDRAM) 808 08

14 Error-checking SDRAM data width 808 08

15 Reserved 000 00

16 Burst lengths supported 4, 8 0C 0C

17 Number of banks on SDRAM device 808 08

18 CAS latencies supported -667 (5, 4, 3)

-53E/-40E (4, 3) 38

18 38

19 Module thickness 01 01

20 DDR2 DIMM type SODIMM 04 04

21 SDRAM module attributes 1 PLL, 1 Reg 04 04

22 SDRAM device attributes: weak driver (01) or

50Ω ODT (03) -667

-53E/-40E 03

01 03

23 SDRAM cycle time, tCK, MAX CL - 1 -667

-53E/-40E 3D

50 3D

24 SDRAM access fr om CK, tAC,

MAX CL - 1 -667

-53E

-40E

25 SDRAM cycle time, tCK, MAX CL - 2 -667

-53E/-40E 50

00 50

26 SDRAM access fr om CK, tAC,

MAX CL - 2 -667

-53E/-40E 45

00 45

27 MIN row precharge time, tRP 3C 3C

28 MIN row active to row active, tRRD 1E 1E

29 MIN RAS#-to-CAS# del ay, tRCD 3C 3C

30 MIN active-to-precharge time , tRAS -667/-53E

-40E 2D

28 2D

31 Module rank density 2GB, 4GB 01 02

32 Address and command setup time, tISb-667

-53E

-40E

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2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Serial Presence-Detect

Notes: 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron

DDR2 device specification is tRC = 55ns for all speed grades.

33 Address and command hold time, tIHb-667

-53E

-40E

34 Data/data mask input setup time, tDSb-667/-53E

-40E 10

15 10

35 Data/data mask input hold time, tDHb-667

-53E

-40E

36 Write recovery time, tWR 3C 3C

37 WRITE-to-READ command delay, tWTR -667/-53E

-40E 1E

28 1E

38 READ-to-PRECHARGE command delay, tRTP 1E 1E

39 Memory analysis probe 00 00

40 Extension for bytes 41 and 42 06 06

41 MIN active-to-active/refresh time, tRC1-667/-53E

-40E 3C

37 3C

42 MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH

command period, tRFC 7F C5

43 SDRAM device MAX cycle time, tCK (MAX) 80 80

44 SDRAM device MAX DQS–DQ skew time, tDQSQ -667

-53E

-40E

45 SDRAM device MAX read data hold skew factor,

tQHS -667

-53E

-40E

46 PLL relock time 0F 0F

47–61 Optional features, not supported 00 00

62 SPD revision Release 1.2 12 12

63 Checksum for bytes 0–62 -667

-53E

-40E

64 Manufactur er’s JEDEC ID code MICRON 2C 2C

65–71 Manufactur er’s JEDEC ID code (continued) FF FF

72 Manufacturing location 1–12 01–0C 01–0C

73–90 Module part number (ASCII) – Variable data Variable data

91 PCB identification code 1–9 01–09 01–09

92 Identification code (continued) 000 00

93 Year of manufacture in BCD – Variable data Variable data

94 Week of manufacture in BCD – Variable data Variable data

95–98 Module serial number – Variable data Variable data

99–127 Reserved for manufa cturer-specific data 00 00

128–255 Reserved for customer-specific data FF FF

Table 31: Serial Presence-Detect Matrix (continued)

Byte Description Entry (Version) 2GB 4GB

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, the Micron logo, and T winDie are trademarks of Micron Technology , Inc. All other trademarks are the property of their

respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production

devices. Although considered final, these specifications are subject to change, as further product development and data charact erization

sometimes occur.

2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM

Module Dimensions

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Module Dimensions

Figure 5: 200-Pin DDR2 SORDIMM

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

3.80 (0.150)

MAX

PIN 1

67.75 (2.667)

67.45 (2.656)

20.0 (0.787)

TYP

1.80 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

PIN 199

PIN 200 PIN 2

Front view

2.00 (0.079)

TYP

6.0 (0.236)

TYP

63.60 (2.504)

TYP

3.50 (0.138) TYP

Back view

1.10 (0.043)

0.90 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

0.50 (0.0197) R

16.26 (0.64)

TYP

U1 U2

U8 U9

U10 U11 U12 U13 U14

1.0 (0.039)

TYP

10.00 (0.394)

TYP

1.0 (0.039) R

(2X)

30.15 (1.187)

29.85 (1.175)