LTC2921/LTC2922 Series
1
29212fa
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
2921/22 TA01
100Ω
10Ω
LTC2921
V
CC
SENSE
100Ω
100Ω
4.7k
49.9k
49.9k
169k
243k
V
OUT
V
FB
V
OUT
V
FB
V
OUT
V
FB
10Ω
10Ω
V1
V2
V3
V4
GATE
PG
GND TIMER
Si1012R
CBRST
5V SUPPLY
3.3V SUPPLY
2.5V SUPPLY
Si2316DS
Si2316DS
Si2316DS
WSL1206
0.05Ω
0.22µF
5V
LOAD
3.3V
LOAD
2.5V
LOAD
RESET
0.47µF
DC/DC
CONVERTER
DC/DC
CONVERTER
DC/DC
CONVERTER
100k
D1
D2
D3
S1
S2
S3
CIRCUIT BREAKER
RESET CONTROL
t
GATE
~ 500ms
t
TIMER
~ 130ms
■
Desktop Computers
■
Plug-In Cards
■
Telecom Infrastructure
■
Supply Sequencing
■
Instruments
■
Tracks Multiple Supplies with MOSFET Switches
■
Monitors 5 Input Voltages Including V
CC
■
Guaranteed Threshold Accuracy: ±1% at 0.5V
■
Automatic Remote Sense Switching
■
Adjustable Supply Ramp Rate
■
Overvoltage Monitor
■
Adjustable Electronic Circuit Breaker
■
Adjustable Power-Good Delay
■
Available for V
CC
Supply Voltages of 5V, 3.3V and 2.5V
■
Available in 16-Pin Narrow SSOP (LTC2921 Series)
and 20-Pin TSSOP (LTC2922 Series)
Power Supply Tracker
with Input Monitors
The LTC
®
2921 and LTC2922 monitor up to five supplies
and force them to track on power-up in multiple supply
systems. Using external N-channel pass transistors, the
supplies can be ramped up at an adjustable rate. Auto-
matic remote sense switching allows the DC/DC convert-
ers to compensate for series voltage drops in the wiring.
An incorrect level on one or more of the supplies triggers
disconnect of all supplies. Tight 1% accuracy and glitch
immunity on the low 0.5V monitoring level ensure no false
error disconnects.
The LTC2921 and LTC2922 each feature an adjustable
electronic circuit breaker to protect the V
CC
supply against
short circuits. Capacitance at the TIMER pin programs the
delays in the monitoring sequence.
The LTC2921 includes three remote sense switches in a
16-pin narrow SSOP package, while the LTC2922 includes
five remote sense switches in a 20-pin TSSOP package.
Both parts are available for V
CC
supply voltages of 5V,
3.3V, and 2.5V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Three-Supply Tracker and Monitor (5V, 3.3V, 2.5V)
Load Voltage Ramp-Up and
Power-Good Activation
2921/22 TA01b
2.5V SUPPLY
2V/DIV
PG
2V/DIV
5V LOAD
3.3V LOAD
2.5V LOAD
5V SUPPLY AT 5V
3.3V SUPPLY AT 3.3V 100ms/DIV
OUTPUTS
2V/DIV
LTC2921/LTC2922 Series
2
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Pin
V
CC
Supply Voltage Typical Operating Range
LTC2921/LTC2922 4.50 5.00 5.50 V
LTC2921-3.3/LTC2922-3.3 2.97 3.30 3.63 V
LTC2921-2.5/LTC2922-2.5 2.37 2.50 2.63 V
I
CC
Supply Current 2mA
V
CC(MON)
Supply Monitor Threshold Voltage LTC2921/LTC2922 ●4.285 4.350 4.415 V
LTC2921-3.3/LTC2922-3.3 ●2.828 2.871 2.914 V
LTC2921-2.5/LTC2922-2.5 ●2.265 2.300 2.335 V
V
CC(OV)
Supply Overvoltage Threshold LTC2921/LTC2922 ●5.82 6.13 6.43 V
LTC2921-3.3/LTC2922-3.3 ●3.84 4.04 4.24 V
LTC2921-2.5/LTC2922-2.5 ●3.08 3.24 3.40 V
V
CC
Supply Voltage......................................–0.3V to 7V
V1, V2, V3, V4 Voltages............................... –0.3V to 7V
SENSE Voltage ............................................–0.3V to 7V
TIMER Voltage............................. –0.3V to (V
CC
+ 0.3V)
Charge Pumped Output Voltages
GATE, PG............................................ –0.3V to 12.2V
Switch Voltages
S0, D0, S4, D4 (LTC2922 Series) ............–0.3V to 7V
S1, D1, S2, D2, S3, D3 ............................–0.3V to 7V
ORDER PART
NUMBER
T
JMAX
= 125°C, θ
JA
= 110°C/W
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Switch Currents (DC, RMS)
S0, D0, S4, D4 (LTC2922 Series) ..................... 30mA
S1, D1, S2, D2, S3, D3 ..................................... 30mA
Operating Ambient Temperature Range
LTC2921C/LTC2922C .............................. 0°C to 70°C
LTC2921I/LTC2922I ............................–40°C to 85°C
Junction Temperature (Note 2).............................125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
LTC2922CF
LTC2922CF-3.3
LTC2922CF-2.5
LTC2922IF
LTC2922IF-3.3
LTC2922IF-2.5
T
JMAX
= 125°C, θ
JA
= 90°C/W
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V1
V2
V3
V4
S3
D3
S2
D2
TIMER
VCC
SENSE
GATE
PG
GND
D1
S1
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
SO
TIMER
V1
V2
V3
V4
S4
D4
S3
D3
D0
V
CC
SENSE
GATE
PG
GND
D1
S1
D2
S2
F PACKAGE
20-LEAD PLASTIC TSSOP
LTC2921CGN
LTC2921CGN-3.3
LTC2921CGN-2.5
LTC2921IGN
LTC2921IGN-3.3
LTC2921IGN-2.5
GN PART MARKING
2921
292133
292125
2921I
921I33
921I25
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V for LTC2921/LTC2922, VCC = 3.3V for
LTC2921-3.3/LTC2922-3.3, and VCC = 2.5V for LTC2921-2.5/LTC2922-2.5, unless otherwise noted.
LTC2921/LTC2922 Series
3
29212fa
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V for LTC2921/LTC2922, VCC = 3.3V for
LTC2921-3.3/LTC2922-3.3, and VCC = 2.5V for LTC2921-2.5/LTC2922-2.5, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows:
LTC2921 Series: T
J
= T
A
+ (P
D
• 110°C/W)
LTC2922 Series: T
J
= T
A
+ (P
D
• 90°C/W)
Note 3: This specification applies to all switches, and is measured with
V
S
< V
D
.
Note 4: The PG pin will rise to approximately the same voltage as the
GATE pin when not pulled up or pulled down by external resistance.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC(UVLO)
Supply Undervoltage Lockout V
CC
Rising ●2.08 2.20 2.30 V
V
CC(UVH)
Supply Undervoltage Hysteresis V
CC
Falling 120 mV
Electronic Circuit Breaker
∆V
SENSE
Circuit Breaker Trip Voltage ∆V
SENSE
= V
CC
- V
SENSE
●45 50 55 mV
I
SENSE
SENSE Pin Input Current 150 500 nA
t
V1(DLY)
Circuit Breaker Trip Delay Time V
CC
- V
SENSE
= 150mV
LTC2921/LTC2922 0.5 1.5 3.0 µs
LTC2921-3.3/LTC2922-3.3 0.5 1.5 3.0 µs
LTC2921-2.5/LTC2922-2.5 0.5 1.5 6.0 µs
t
V1(RST)
Circuit Breaker Reset Pulse Width Guaranteed Not to Reset ●50 µs
Guaranteed to Reset ●150 µs
V
V1(RST)
Circuit Breaker Reset Threshold Voltage ●0.490 0.500 0.510 V
Monitor Inputs
V
MON
V1-V4 Monitor Threshold Voltages 0.495 0.500 0.505 V
●0.492 0.500 0.508 V
V
OV
V1-V4 Overvoltage Thresholds ●0.665 0.700 0.735 V
I
MON
V1-V4 Input Currents ±0.1 µA
TIMER Pin
V
TIMER(TH)
TIMER Ramp Threshold Voltage ●1.15 1.20 1.25 V
I
TIMER(PU)
TIMER Pull-Up Current V
TIMER
= 1V ●–1.3 –2.0 –2.5 µA
I
TIMER(PD)
TIMER Pull-Down Current V
CC
= 2.35V, V
TIMER
= 0.4V 100 µA
V
TIMER(CLR)
TIMER Cleared Threshold Voltage V
TIMER
Falling 150 250 mV
GATE Pin
V
GATE
GATE Drive Output Voltage LTC2921/LTC2922 ●10.0 11.1 12.2 V
LTC2921-3.3/LTC2922-3.3 ●8.4 9.1 9.8 V
LTC2921-2.5/LTC2922-2.5 ●6.1 6.8 7.5 V
I
GATE(PU)
GATE Pull-Up Current V
GATE
= V
CC
●–6.5 –10.0 –12.5 µA
I
GATE(PD)
GATE Pull-Down Current V
CC
= 2.35V, V
GATE
= 2.35V 10 mA
Remote Sense Switches
R
DS(FB)
Feedback Switch Resistances (Note 3) V
D
= V
CC
●210 Ω
PG Pin
I
PG(PU)
PG Pull-Up Current V
PG
= V
CC
●–2.6 –4.0 –5.0 µA
I
PG(PD)
PG Pull-Down Current V
CC
= 2.35V, V
PG
= 2.35V 10 mA
V
PG(OL)
PG Output Low Voltage V
CC
= 2.35V, I
PG
= 5mA ●0.4 V
V
PG
PG Output Voltage (Note 4) LTC2921/LTC2922 ●10.0 11.1 12.2 V
LTC2921-3.3/LTC2922-3.3 ●8.4 9.1 9.8 V
LTC2921-2.5/LTC2922-2.5 ●6.1 6.8 7.5 V
LTC2921/LTC2922 Series
4
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V
CC
(V)
2.0
I
CC
(mA)
3.0 4.0 4.5 6.5
2921/2 G01
2.5 3.5 5.0 5.5 6.0
3.00
2.75
2.50
2.25
2.00
1.75
1.50
TEMPERATURE (°C)
–50
I
CC
(mA)
2.6
2.4
2.2
2.0
1.8 10 50
2921/2 G02 2921/2 G03
–30 –10 30 70 90
BREAKER TRIP (mV)
2921/2 G052921/2 G04
55
50
45
TEMPERATURE (°C)
–50
I
SENSE
(nA)
250
200
150
100
50
0–10 30 50
2921/2 G06
–30 10 70 90
TEMPERATURE (°C)
–50 –10 30 50
–30 10 70 90
MONITOR INPUT THRESHOLD (V)
0.505
0.500
0.495
TEMPERATURE (°C)
–10 30 50
–30 10 70 90
–50
TEMPERATURE (°C)
–10 30 50
–30 10 70 90
–50 2.0 3.0 4.0 4.5 6.52.5 3.5 5.0 5.5 6.0
V
CC
(V)
TIMER TRIP VOLTAGE (V)
2921/2 G07
1.21
1.20
1.19
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
TEMPERATURE (°C)
–50
CURRENT (µA)
70
2921/2 G08
–10 30–30 10 50 90
PULL-DOWN CURRENT (µA)
2921/2 G09
170
165
160
155
150
145
140
LTC2921-2.5
LTC2922-2.5
LTC2921-3.3
LTC2922-3.3
LTC2921
LTC2922
LTC2921-2.5
LTC2922-2.5
LTC2921-3.3
LTC2922-3.3
LTC2921
LTC2922
PG SIGNAL ASSERTED PG SIGNAL ASSERTED
MONITOR INPUT OVERDRIVE (mV)
0
MONITOR TRIP DELAY (µs)
100
80
60
40
20
040 80 100
20 60 120 140
LTC2921-2.5
LTC2922-2.5
LTC2921/LTC2922
LTC2921-3.3/LTC2922-3.3
V
SENSE
= V
CC
V
TIMER
= 1V V
TIMER
= 0.4V
Supply Current vs Supply Voltage Supply Current vs Temperature
Monitor Trip Delay vs
Monitor Input Overdrive
Monitor Input Threshold vs
Temperature Circuit Breaker Trip Voltage vs
Temperature
SENSE Input Current
vs Temperature
TIMER Trip Voltage
vs Temperature TIMER Pull-Up Current
vs Temperature
TIMER Pull-Down Current
vs Supply Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Specifications are at TA = 25°C unless otherwise noted.
LTC2921/LTC2922 Series
5
29212fa
V
CC
(V)
2.0 3.0 4.0 4.5 6.52.5 3.5 5.0 5.5 6.0
GATE VOLTAGE (V)
12
11
10
9
8
7
6
GATE VOLTAGE (V)
12
11
10
9
8
7
6
LTC2921-2.5
LTC2922-2.5
LTC2921-3.3
LTC2922-3.3
V
CC
(V)
2.0 3.0 4.0 4.5 6.52.5 3.5 5.0 5.5 6.0
PG (V)
12
11
10
9
8
7
6
TEMPERATURE (°C)
–50 10 50
2921/2 G112921/2 G10
–30 –10 30 70 90
LOAD CURRENT (µA)
40123 78
2921/2 G12
65910
GATE VOLTAGE (V)
12
10
8
6
4
2
0
CURRENT (µA)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
TEMPERATURE (°C)
–50 10 50
2921/2 G15
–30 –10 30 70 90
TEMPERATURE (°C)
–50 10 50
2921/2 G13
–30 –10 30 70 90
2921/2 G14
CURRENT (µA)
GATE LOAD = 1000pF || 10MΩ
PG LOAD = 2kΩ TO V
CC
V
CC
BYPASS CAP = 1µF
GATE LOAD = 1000pF || 10MΩ
PG LOAD = 2kΩ TO V
CC
V
CC
BYPASS CAP = 1µF
LTC2921
LTC2922
LTC2921-2.5
LTC2922-2.5
LTC2921-3.3
LTC2922-3.3
LTC2921
LTC2922
LTC2921-2.5
LTC2922-2.5
LTC2921-2.5
LTC2922-2.5
LTC2921-3.3
LTC2922-3.3
LTC2921-3.3
LTC2922-3.3
LTC2921
LTC2922
LTC2921
LTC2922
11.5
11.0
10.5
10.0
9.5
9.0
8.5
V
GATE
= V
CC
V
PG
= V
CC
GATE LOAD = 1000pF || 10MΩ
PG LOAD = 2kΩ TO V
CC
V
CC
BYPASS CAP = 1µF
GATE LOAD = 1000pF || 10MΩ
PG LOAD = 1000pF || 10MΩ
V
CC
BYPASS CAP = 1µF
Gate Voltage vs Supply Voltage Gate Voltage vs Temperature Gate Voltage vs Load Current
GATE Pull-Up Current
vs Temperature
PG Pull-Up Current vs
Temperature
PG Voltage vs Supply Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Specifications are at TA = 25°C unless otherwise noted.
LTC2921/LTC2922 Series
6
29212fa
S0, D0 (Pins 1, 20 [LTC2922]): Remote Switch 0. These
pins are the terminals of an internal N-channel FET switch
that is enabled after the GATE pin is fully ramped up. This
switch can be used to connect a remote sense line to
compensate for IR drop across the external FETs. The gate
of the internal switch ramps up at a nominal rate of 8V/ms.
The pins are interchangeable, either switch pin can be tied
to the load side. Tie both pins to ground if unused.
S4, D4 (Pins 7, 8 [LTC2922]): Remote Sense Switch 4. Tie
to GND if unused.
S3, D3 (Pins 5, 6/Pins 9, 10): Remote Sense Switch 3. Tie
to GND if unused.
S2, D2 (Pins 7, 8/Pins 11, 12): Remote Sense Switch 2.
Tie to GND if unused.
S1, D1 (Pins 9, 10/Pins 13, 14): Remote Sense Switch 1.
Tie to GND if unused.
TIMER (Pin 16/Pin 2): Timing Delay Input. Connect a
capacitor between this pin and ground to set a 600ms/µF
delay at two points in the monitoring sequence. This sets
the delay after all monitors are good, before the start of
GATE ramping, and the delay after the remote sense
switches are on, before PG is activated. TIMER must fall
below 150mV before a timing delay can start. The TIMER
pin is pulled to ground at other points in the sequence.
V1-V4 (Pins 1-4/Pins 3-6): Supply Monitor Inputs. All four
inputs must lie above the monitor threshold level (0.5V)
and below the monitor overvoltage level (0.7V) for a turn-
on sequence to commence or continue. When any monitor
input falls outside those levels, the GATE and PG pins are
pulled low, disconnecting all the loads. Glitch filtering on
the 0.5V monitor threshold prevents low-energy voltage
spikes from affecting the comparators’ results. V1 also
serves as an active-low reset pin for the circuit breaker. Tie
unused monitor inputs to used monitor inputs.
GND (Pin 11/Pin 15): Circuit Ground.
PG (Pin 12/Pin 16): Power Good Output. A 4µA current
source from the internal charge pump rail (V
PUMP
) pulls
PG up after the turn-on sequence is complete. The output
is pulled to ground before turn-on is complete, when any
monitor is out of compliance, when the circuit breaker
trips, and when V
CC
is undervoltage. An external resistor
can be added to pull up to a lower voltage and to improve
pull up speed. This pin can also be configured as a gate
drive for external N-channel FETs in sequencing applica-
tions. In applications not requiring the PG output, leave the
pin unconnected.
GATE (Pin 13/Pin 17): Gate Drive for External N-Channel
FETs. A 10µA current source from the internal charge
pump rail (V
PUMP
) ramps the gates of the external N-
channel MOSFETs forcing all supplies to track on. The
resistor and capacitor network from this pin to ground
sets the supplies’ ramp rate and enhances control loop
stability.
SENSE (Pin 14/Pin 18): Circuit Breaker Sense Input. An
external resistor between V
CC
and SENSE sets the elec-
tronic circuit breaker trip current. The breaker trips when
the voltage across the resistor exceeds 50mV for 1µs. To
disable the circuit breaker tie SENSE to V
CC
. To reset the
circuit breaker after the current falls below the trip point,
pull the V1 pin below 0.5V for >150µs or go into
undervoltage lockout for >10µs.
V
CC
(Pin 15/Pin 19): Supply Voltage. The voltage at V
CC
is
monitored through an internal resistive divider in a man-
ner similar to the V1-V4 inputs. An undervoltage lockout
circuit disables the part until the voltage at V
CC
is greater
than 2.2V. The V
CC
pin must be connected to the highest
supply voltage. Bypass the V
CC
pin to ground with a 10µF
capacitor.
UU
U
PI FU CTIO S
(LTC2921/LTC2922 or [LTC2922 Only])
LTC2921/LTC2922 Series
7
29212fa
Figure 1. LTC2921 and LTC2922 Functional Diagram
2921/22 F01
+
–
+
+
+
+
+
+
+
+
+
+
–
–
–
–
–
–
–
–
–
–
LATCH
V
OVERVOLTAGE
MONITOR
OVERVOLTAGE
MONITOR
OVERVOLTAGE
MONITOR
OVERVOLTAGE
MONITOR
OVERVOLTAGE
MONITOR
CONTROL
LOGIC
+
+
+
V
PUMP
V
PUMP
V
PUMP
GATE
ON
TIMER
DONE
PULSE
TIMER
DONE
CIRCUIT
BREAKER
RESET PULSE
TIMER ENABLE
TIMER
ENABLE
GATE
ENABLE
REMOTE
SENSE
SWITCH
ENABLE
P
G
ENABLE
4µA
2µA
10µA
V
CC
V
CC
PG
GATE
TIMER
+–
50mV
0.5V
0.7V
SENSE
V
CC
V1
V2
V3
V4
(LTC2922 ONLY)
D4
S4
(LTC2922 ONLY)
D3D2D1
(LTC2922 ONLY)
D0
S0
(LTC2922 ONLY) S1 S2 S3
1.2V
OVERCURRENT
UNDERVOLTAGE
+
SWITCHES ON
V
SWON
V
SWON
V
SWON
REMOTE
SENSE
SWITCH
GATE
REFERENCE
GENERATOR
AND
CHARGE
PUMP
+
–
V
PUMP
≈ 11.1V
AT V
CC
=5V
1.2V
0.7V
0.5V
GND
APPROXIMATELY 1V
FUNCTIONAL DIAGRA
UU
W
LTC2921/LTC2922 Series
8
29212fa
General Operation
The LTC2921 and LTC2922 track multiple supplies, moni-
tor multiple inputs, and provide integrated switches for
remote sensing. Once all input voltages lie between moni-
toring and overvoltage threshold levels, in-line FETs are
turned on to simultaneously ramp power to the loads. The
automatic remote sense switches are then activated, and
the power good signal is asserted. After initial power-on
the LTC2921 and LTC2922 continue monitoring the in-
puts. Several types of events will trigger interruption, any
of which will disconnect all supplies, deactivate the power
good signal, and open the remote sense switches.
Monitoring Sequence
A normal power-on sequence comprises the following
steps:
Step 0) Wait for V
CC
to exceed the undervoltage lockout
threshold. Continue checking V
CC
.
Step 1) Confirm that the circuit breaker has not tripped and
wait for all monitored supplies, including V
CC
, to be
between their programmed monitor and overvoltage
thresholds. Continue checking these conditions.
Step 2) Check that the TIMER pin voltage starts below
150mV. Create a delay by ramping up the TIMER pin until
it trips an internal comparator.
Step 3) Ramp the GATE pin to turn on the external
N-channel FETs, simultaneously ramping the supplies into
their loads. Await confirmation of full GATE enhancement,
i.e., GATE voltage within ~1V of V
PUMP
. Continue checking
this condition.
Step 4) Activate the remote sense switches. Await confir-
mation of full Feedback Switch Gate enhancement.
Step 5) Wait again for another TIMER cycle delay.
Step 6) Release the pull-down on the PG output. Continue
checking V
CC
, the circuit breaker, the input voltages, and
the GATE voltage.
Interrupting Events
Three events can interrupt the sequence and trigger imme-
diate disconnect of all supplies, pull-down of the PG
signal, and deactivation of the remote sense switches. The
three interrupting events are a lockout, a fault, and an
error.
A lockout occurs when V
CC
falls below the undervoltage
threshold (including hysteresis). Escape from lockout
requires sufficient V
CC
voltage. Leaving lockout, the se-
quence begins at Step 1. A lockout condition supersedes
faults and errors.
A fault occurs when the circuit breaker trips. Escape from
a fault requires pulsing the V1 pin below the reset thresh-
old of 0.5V(nom) for more than 150µs after the current
falls below the trip point. When V1 returns high, the
sequence begins from Step 1. An undervoltage lockout of
>10µs also clears the circuit breaker fault latch. A fault
condition supersedes errors.
An error occurs when one or more of the monitor inputs
(V1-V4 pins) or V
CC
falls below its monitor threshold, or
rises above its overvoltage threshold. A loss of voltage on
the GATE pin, once it has fully ramped up, also causes an
error. An error sends the sequence to Step 1.
Feedback Switches for Remote Sensing
The integrated N-channel switches of the LTC2921/
LTC2922 automatically compensate for the voltage drops
caused by the R
DS(ON)
of the external load-control MOS-
FET switches. This is accomplished by modifying the
normal feedback path of each power supply that is con-
trolled by the LTC2921/LTC2922. When the load-control
switches are off, the remote sense switches are also off,
and the power supply uses its normal feedback path to
sense its output voltage. After the load-control switches
are turned on, the remote sense switches are turned on to
create dominating feedback paths. The feedback loops
include the load-control switches, thus compensating for
their voltage drops.
In order to eliminate glitching on the output of the power
supply, the remote sense switches are turned on at a
controlled rate of about 8V/ms. The gates of these inte-
grated N-channel devices are pulled up above V
CC
to
V
PUMP
so as to provide a low-resistance path for a wide
range of voltages.
OPERATIO
U
LTC2921/LTC2922 Series
9
29212fa
Electronic Circuit Breaker
Placing a resistor between the V
CC
and SENSE pins allows
the part to detect shorts and excessive currents on the V
CC
supply. The electronic circuit breaker trips when the
voltage across the resistor is >50mV for more than 1µs. A
trip causes a fault condition which interrupts the monitor
OPERATIO
U
sequence, and which requires reset of the circuit breaker
latch (see Interrupting Events section). Breaker reset is
achieved by pulling V1 below the reset threshold for
>150µs after the current falls below the trip point, or by
returning from undervoltage lockout on V
CC
.
The timing of a typical start-up sequence for the LTC2921/
LTC2922 is shown in Figure 2. V
CC
exceeds the undervoltage
lockout level at time 0. All monitor inputs settle between
the 0.5V monitor threshold and the 0.7V overvoltage
threshold by time 1, then a TIMER cycle starts. The TIMER
pin reaches 1.2V at time 2, and GATE ramping begins.
When the GATE ramp completes at time 3, the automatic
remote sense switches close. Another TIMER delay
begins at time 4 and finishes at time 5, at which time PG
is activated.
The timing of a monitor failure and subsequent regular
turn-on is shown in Figure 3. Prior to time 1, a successful
turn-on sequence had completed. At time 1, monitor V2
falls below the 0.5V reference, triggering an error. The
GATE pin, PG pin, and the remote sense switches fall at
rates determined by the pull-down currents and loading
conditions of each (times 2, 3, 4). At time 5, monitor V2
recovers, and a normal turn-on sequence begins.
TI I G DIAGRA S
WUW
V
CC
SENSE
V1
V2
V3
V4
TIMER
GATE
PG
012 345
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
V
CC
V
CC
V
CC
-50mV
1.2V 1.2V
UNDERVOLTAGE
LOCKOUT LEVEL
REMOTE
SENSE
SWITCH
GATE
V
CC
SENSE
V1
V2
V3
V4
TIMER
GATE
PG
1234 5
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
V
CC
V
CC
V
CC
-50mV
1.2V
1.2V
UNDERVOLTAGE
LOCKOUT LEVEL
REMOTE
SENSE
SWITCH
GATE
Figure 2. Typical Start-Up Sequence Figure 3. Monitor Failure and Start-Up Sequence Timing
LTC2921/LTC2922 Series
10
29212fa
The timing of a circuit breaker trip and reset, and a
subsequent regular turn-on are shown in Figure 4. Prior to
time 1, a successful turn-on sequence had completed. At
time 1, excessive current pulls SENSE more than 50mV
below V
CC
. The GATE pin, PG pin, and the remote sense
switches fall at rates determined by the pull-down currents
and loading conditions of each (times 2, 3, 4). Note that the
excessive current condition ceases at time 4. A circuit
breaker reset pulse is initiated at time 5. The latch resets
at time 6 since the V1 pulse is wide enough. A normal turn-
on begins when V1 rises above the monitor threshold
(time 7 onward).
Multiple supply systems have become common to accom-
modate circuits on the same board with different voltage
requirements. Desktop PC motherboards, instrumenta-
tion circuits and plug-in boards of all kinds often require
tracking and control of several supply voltages.
The LTC2921 and LTC2922 ramp and monitor up to five
supply voltages in such systems. External resistive volt-
age dividers independently program four monitor levels,
while an internal divider sets the V
CC
pin supply monitor
level. Time delays in the monitoring sequence are set by an
external capacitor at the TIMER pin.
The GATE pin provides a high side drive voltage appropri-
ate to logic-level and sublogic-level N-channel power
TI I G DIAGRA S
WUW
V1
V2
V3
V4
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
0.7V
0.5V
V
CC
V
CC
V
CC
-50mV
V
CC
V
CC
-50mV
1.2V 1.2V
1234 675
V
CC
SENSE
TIMER
GATE
PG
REMOTE
SENSE
SWITCH
GATE
INTERNAL
CIRCUIT
BREAKER
LATCH
UNDERVOLTAGE
LOCKOUT LEVEL
APPLICATIO S I FOR ATIO
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Figure 4. Circuit Breaker Trip, Reset and Start-Up Sequence Timing
MOSFETs. The external RC network on GATE programs
the supply ramp rate and eliminates possible high fre-
quency oscillations in the power path. Featured in the
LTC2921/LTC2922 series are sub-10Ω internal remote
sense switches to compensate for voltage drops between
the supplies and the loads.
At the end of a successful power-on sequence, the LTC2921/
LTC2922 asserts the PG output. A typical application uses
an external pull-up resistor between PG and the load side
of a supply. In applications where supply power-on se-
quencing is required, the PG pin can function as a second,
separate high side driver.
LTC2921/LTC2922 Series
11
29212fa
APPLICATIO S I FOR ATIO
WUUU
Figure 5. Basic Monitor Connection
Setting the Supply Monitor Levels
The LTC2921 and LTC2922 series both feature low 0.5V
monitoring thresholds with tight 1% accuracy. To set a
supply monitoring level tightly, design a precision ratio
resistive divider to relate the lowest valid supply voltage to
the maximum specified monitor threshold voltage. Use
resistors with 1% tolerance or better to limit the error due
to mismatch. The basic resistive divider connection for
supply monitoring is shown in Figure 5.
2921/22 F05
LTC2922
V1
GND
GATE
V
Q1
Q1
C
GATE
LOAD
I
MON
I
A1
R
B1
R
Y1
R
Z1
R
A1
V
L1
V
V1
V
SRC1
R
G1
10Ω
V
OUT
V
FB
GND
DC/DC
CONVERTER
+–
±0.1µA
First, divide the nominal monitor threshold voltage by an
acceptable bias current (I
A1
), and choose a nearby stan-
dard value for resistor R
A1
(see Equation 1).
Next, calculate the bounds on the value of R
B1
that
guarantee that the divided minimum supply voltage ex-
ceeds the maximum specified monitor threshold voltage,
and that the minimum specified overvoltage threshold
exceeds the divided maximum supply voltage. Use Equa-
tions 2 and 3 to calculate R
B1(MAX)
and R
B1(MIN)
from R
A1
,
the resistor tolerance (RTOL), the supply voltage, the
monitor threshold and overvoltage specifications, and the
monitor pin leakage current specification.
When the integrated remote sensing switch is closed, the
DC/DC converter will compensate for the IR drop from
drain to source of the external N-channel FET (V
Q1(ON)
) by
increasing the supply voltage by the same amount. Calcu-
late with V
Q1(ON)(MAX)
= 0V if the remote sense switch is
not used.
RV
I
AA
11
0 500
=.
(1)
R
RRTOL
RTOL
VV
VAR
B MAX
ASRC MIN
A
1
11
1
1
1
0 505
0 505 0 1
()
()
•–•–.
..•
=
+
+µ
(2)
RR
RTOL
RTOL
VV V
VAR
B MIN A
SRC MAX Q ON MAX
A
11
11
1
1
1
0 665
0 665 0 1
()
() ()()
•–•
–.
.–.•
=+
+µ
(3)
Choose a standard resistor value for R
B1
that satisfies the
inequality of Equation 4.
R
B1(MIN)
≤ R
B1
≤ R
B1(MAX)
(4)
When several standard values meet the requirement,
choose the value closest to R
B1(MAX)
to set the tightest
monitor threshold. This also allows more headroom for
larger V
Q1(ON)(MAX)
. Alternatively, choose the standard
value closest to R
B1(MIN)
to set the tightest overvoltage
threshold.
All four monitor input voltages must be between the
monitor threshold and the overvoltage threshold for the
turn-on sequence to begin. Connect unneeded monitor
input pins to any of the utilized monitor input pins.
Selecting the External N-Channel MOSFETs
The GATE pin drives the gate of external N-channel
MOSFETs above V
CC
to connect the supplies to the loads.
The GATE drive voltage provided by the LTC2921/LTC2922
series is best suited to logic-level and sublogic-level
power MOSFETs. To achieve the lowest switch resistance,
the V
CC
pin must be connected to the highest supply
voltage.
Consider the application requirements for current, turnoff
speed, on-resistance, gate-source voltage specification,
etc. Refer to the Electrical Specifications and Typical
Performance Curves to determine the GATE voltages for
given V
CC
voltages over the required range of conditions.
Calculate the minimum gate drive voltage for each moni-
tored supply for use in selecting the FETs. Check the
maximum GATE voltage against the FETs’ gate-source
LTC2921/LTC2922 Series
12
29212fa
voltage specifications. On-resistance is a critical param-
eter when choosing power MOSFETs. The integrated
remote sense switches compensate for IR drops, but
minimizing V
Q(MAX)
leaves more margin for designing the
resistive voltage divider for the monitors.
Setting the GATE Ramp Rate
Application of power to the loads is controlled by setting
the voltage ramping rate with an external capacitor on the
GATE pin. During Step 3 of the monitoring sequence, a
10µA pull-up ramps the GATE pin capacitance up to
V
PUMP
, the internal charge pump voltage. Use Equation 5
to calculate the nominal GATE pin capacitance necessary
to achieve a given ramp rate, ∆V/∆t:
CA
Vt
GATE
=µ
∆∆
10
/
(5)
Alternatively, to calculate the GATE capacitor to achieve a
desired nominal ramp time, use Equation 6. The GATE
drive voltage (V
GATE
) varies with V
CC
voltage. Consult the
Electrical Characteristics table and Typical Performance
curves to choose an appropriate value to insert for V
GATE
.
CAt
V
GATE RAMP
GATE
=µ10 •
(6)
When the GATE pin drives several FETs in parallel, the load
voltages ramp together at the same rate until the lowest
supply reaches its full value. The other supplies continue
to track until the next lowest supply reaches its full value,
and so on.
The GATE pin must not be forced above the level it reaches
when fully ramped. An internal clamp limits the GATE
voltage to ≤12.2V relative to ground.
Damp possible ramp-on oscillations by including a 10Ω
resistor in series with each external N-channel gate, and as
necessary, a 0.1µF capacitor on each external N-channel
drain, as shown in Figure 6.
Setting the Sequence Delay Timer
The turn-on sequence includes two programmable delays
set by the capacitance on the TIMER pin. More precisely,
a single delay value is used at two points in the sequence.
APPLICATIO S I FOR ATIO
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In both cases, the delay provides a measure of confidence
that conditions are stable enough for the sequence to
advance.
The first TIMER delay begins once all monitor voltages
comply with their thresholds, the electronic circuit breaker
has not tripped, and V
CC
is not undervoltage. The TIMER
pin sources 2µA into an external capacitor, which ramps
its voltage. A comparator trips when the TIMER pin voltage
reaches the internal 1.2V reference, then the GATE ramp
begins, and TIMER is pulled to ground. The second TIMER
delay begins after the gate of the remote sense switches is
fully ramped up. After the TIMER ramp completes, the PG
pin is activated. An internal circuit pulls-down the TIMER
pin with >100µA of current at all times, except during the
ramping periods, and when V
CC
is undervoltage.
Calculate the nominal value for the timing capacitor by
inserting the desired delay into Equation 7:
CA
Vt
TIMER DLY
=µ2
12.•
(7)
For delay times below 60µs, be sure to limit stray capaci-
tances on the TIMER pin by using good PCB design
practices. To program essentially no delay (<1µs), float
the TIMER pin.
Internal circuitry guarantees that the TIMER pin is pulled
below 150mV (typical) before a delay cycle can begin.
LTC2922
GND
GATE
R
G2
10Ω
R
G1
10Ω
R
G0
10Ω
Q2
Q1
Q0
C
GATE
C
D2
0.1µF
(OPT)
C
D1
0.1µF
(OPT)
C
D0
0.1µF
(OPT)
V
SRC2
V
SRC1
V
SRC0
2921/22 F06
V
L2
V
L1
V
L0
Figure 6. Ramping and Damping Components on GATE Pin
LTC2921/LTC2922 Series
13
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Electronic Circuit Breaker
The LTC2921/LTC2922’s electronic circuit breaker pro-
tects against excessive current on V
CC
. The circuit breaker
trips when the SENSE pin falls more than 50mV below the
V
CC
pin for more than 1µs. When the breaker trips, the
remote sense switches are opened and the PG and GATE
pins are pulled to ground, disconnecting the supplies. An
internal latch guarantees that the monitoring sequence
cannot start until the breaker is reset. To reset the circuit
breaker, cycle the V1 input below 0.5V(nom) for more than
150µs. V
CC
falling below the undervoltage threshold also
resets the breaker. After reset, the sequence returns to
Step 1, awaiting valid monitor levels.
Figure 7 shows an equivalent schematic for the electronic
circuit breaker function. Using Equation 8, set the circuit
breaker by selecting R
SENSE
to drop less than the mini-
mum ∆V
SENSE
at the desired trip current:
RV
I
SENSE SENSE MIN
LO TRIP
≤∆
()
()
(8)
After selecting a resistor, use Equations 9a and 9b to
calculate the actual minimum and maximum trip current
threshold limits:
IV
R
TRIP MIN SENSE MIN
SENSE MAX
() ()
()
=∆
(9a)
IV
R
TRIP MAX SENSE MAX
SENSE MIN
() ()
()
=∆
(9b)
Be mindful of thermal effects and power ratings when
choosing a resistor. Place R
SENSE
as close as possible to
the LTC2921/LTC2922 pins to reduce noise pickup, and
use Kelvin sensing to ensure accurate measurement of the
voltage drop. In applications not requiring the current
sensing circuit breaker, tie the SENSE pin to the V
CC
pin.
Configuring the PG Pin Output
The LTC2921 and LTC2922 each include a power good
indicator, the PG pin. During the turn-on sequence, and
upon detection of errors, a strong FET pulls PG to ground
with >10mA of current. When all supplies have satisfied
their monitor and overvoltage thresholds, the circuit breaker
has not tripped, the GATE pin has reached its peak, and the
remote sense switches have turned on, a 4µA current
source from V
PUMP
pulls up PG.
Configure PG as a logic signal by adding an external pull-
up resistor to a voltage source. For example, create a
negative-logic system reset signal by adding an external
pull-up resistor to the load side of a supply voltage, as in
Figure 8. Calculate the minimum pull-up resistor value that
meets the output low voltage specification for V
PG(OL)
:
RVV
mA
PG MIN LO MAX
() ()
.
=−04
5
(10)
Do not pull PG above the GATE pin’s fully ramped voltage.
An internal clamp limits the PG voltage to ≤12.2V relative
to ground. In applications that do not require the PG
output, leave the pin unconnected.
The PG output can also be used as the gate drive for
external N-channel MOSFETs, as in Figure 9. The delay
between the GATE ramp and the PG activation makes a
supply sequencer, useful when two supplies (or two
groups of supplies) need to be ramped one after another.
Choose the FETs and design the ramp rate in the same way
as for the GATE pin. Refer to Equations 5 and 6, substitut-
ing 4µA for 10µA, to choose capacitor C
PG
.
Integrated Switches for Remote Sensing
A significant feature of the LTC2921/LTC2922 series
is a set of remote sense switches that allow for
compensation of voltage drops in the load path. Switch
activation occurs in the turn-on sequence after the GATE
Figure 7. Circuit Breaker Functional Schematic
GATE
ENABLE
CONTROL
LOGIC
V
PUMP
V
PUMP
V
PUMP
SWITCH
ENABLE
PG
ENABLE
4µA
4µA
PG
GATE
REMOTE
SENSE
SWITCH
GATE
LATCH
V
PULSE
WIDTH
MEAS.
+
+
–
50mV
V
CC
SENSE
R
SENSE
OVERCURRENT
COMPARATOR
V1
V
LO
I
LO
V
SRC0
GND
C
GATE
R
G0
10Ω
2921/22 F07
Q0
LOAD
LTC2922
LTC2921/LTC2922 Series
14
29212fa
APPLICATIO S I FOR ATIO
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pin has fully ramped up. The switches are N-channel
MOSFETs whose gates are ramped from ground to V
PUMP
at a nominal rate of 8V/ms. The PG pin is activated upon
completion of the TIMER delay cycle that follows GATE
ramp-up and remote sense switch activation. When con-
ditions indicate a supply disconnect, the switches shut off
in less than 10µs.
Figure 10 shows an example of how to connect a switch to
remote sense the load voltage. Although only one remote
sense switch is referred to in this section, the calculations
and comments apply to all.
Before the activation of Q1 and the internal switch, resistor
R
X1
provides a direct path between the DC/DC converter’s
output voltage and its feedback network (R
Y1
and R
Z1
).
Once Q1 activates, the supply energizes the load. When
the internal switch turns on, it provides a remote sense
path between the load voltage and the converter’s feed-
back network.
To choose a value for resistor R
X1
, consider the remote
sense switch connection equivalent network in Figure 11.
Resistor R
Q1(ON)
represents the on-resistance of Q1, and
resistor R
FB1(ON)
represents the on-resistance of the inter-
nal switch.
To allow the load voltage to dominate the feedback to the
converter when the internal switch is closed, make R
X1
>>
R
FB1(ON)
. To set the converter feedback ratio accurately
with R
Y1
and R
Z1
, make both R
X1
and R
FB1(ON)
much less
than (R
Y1
+ R
Z1
). To ensure that most of the load current
flows through the external N-channel FET, choose (R
X1
+
R
FB1(ON)
) >> R
Q1(ON)
. Summarized, these requirements
amount to:
R
Q1(ON)
, R
FB(ON)
<< R
X1
<< (R
Y1
+ R
Z1
) (11)
Approach the selection of R
X1
in the following way: design
the DC/DC converter feedback based on the resistive
divider formed by R
Y1
and R
Z1
with V
S1
at the desired
supply voltage value. When the resistor values satisfy
Equation 11, Equations 12 through 15 are valid.
PG
ENABLE
4µA
PG
VCC SENSE
RSENSE
GATE
VL0
VSRC0
GND
CGATE
RG0
10Ω
RPG
2921/22 F08
Q0
LTC2922
µC
RESET
VPUMP
PG
ENABLE
4µA
PG
V
CC
SENSE
R
SENSE
GATE
V
L0
V
L5
V
SRC0
V
SRC5
GND
C
GATE
C
PG
R
G0
10Ω
R
G5
10Ω
2921/22 F09
Q0
Q5
LTC2922
V
PUMP
2921/22 F10
R
X1
R
Y1
R
Z1
V
SRC1
V
OUT
V
FB
GND
DC/DC
CONVERTER
LTC2922
V1
GND
GATE
Q1
C
GATE
LOAD
R
B1
R
G1
10Ω
R
A1
V
L1
S1 D1
V
S1
2921/22 F11
LTC2922
S1 D1 LOAD
I
DS1
I
Q1
R
X1
R
FB1(ON)
R
Q1(ON)
R
Y1
R
Z1
V
SRC1
V
L1
V
S1
I
L1
V
OUT
V
FB
GND
DC/DC
CONVERTER
Figure 9. PG Pin as Sequenced N-Channel Gate Driver
Figure 8. PG Pin as Logic Output
Figure 10. Automatic Remote Sense Switching Connection
Figure 11. Remote Sense Switch Connection Equivalent Network
LTC2921/LTC2922 Series
15
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APPLICATIO S I FOR ATIO
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Before Q1 closes to connect the load, the actual supply
voltage relative to V
S1
is given by Equation 12.
∆= = ++
VVVV R
RRR
SRC SRC S S X
XYZ
1111 1
111
–•
(12)
After both Q1 and the internal remote sense switch have
closed, the load voltage relative to V
S1
is given by Equation
13.
∆= =
VVV IR R
R
LLS LQON FB ON
X
111 11 1
1
––• •
() ()
(13)
A small part of the load current will flow through the
remote sense switch. Use Equation 14 to calculate the
current, and do not exceed the switch current Absolute
Maximum Rating when choosing the value of R
X1
.
II
R
R
DS L QON
X
11 1
1
=
•()
(14)
In addition, once the remote sensing is active, the supply
voltage V
SRC1
will rise by approximately the drop across
the external FET. The effect on the monitor resistive divider
design has already been accounted for in the previous
section, Setting the Supply Monitor Levels.
VVIR R
R
VV
SRC S L Q ON FB ON
X
SQON
1111 1
1
11
1=+
≈+
••–
() ()
()
(15)
The terminals of each switch are interchangeable; choose
the connections to optimize the board layout. Ground all
unused switch pins.
Design Example
Consider the design of a three-supply monitoring system,
as shown in Figure 12, with specifications as listed in
Table␣ 1.
Table 1. Design Example Electrical Specifications
Supply Specifications
5V ± 7.5% V
SRC0(MAX)
= 5.375V I
L0
= 0.8A (max)
V
SRC0(MIN)
= 4.625V
3.3V ± 7.5% V
SRC1(MAX)
= 3.5475V I
L1
= 1.6A (max)
V
SRC1(MIN)
= 3.0525V
2.5V ± 7.5% V
SRC2(MAX)
= 2.6875V I
L2
= 0.4A (max)
V
SRC2(MIN)
= 2.3125V
External N-channel FET Drain-Source Voltage Specification
5V Supply V
Q0(ON)(MAX)
< 250mV
3.3V Supply V
Q1(ON)(MAX)
< 250mV
2.5V Supply V
Q2(ON)(MAX)
< 150mV
Timing Specification
TIMER Delay t
DLY
= 150ms (nom)
GATE Ramp Time t
RAMP
= 500ms (nom)
Bias Current Specification
Monitor Resistive I
A1
= 10µA (nom)
Divider Current I
A2
= 10µA (nom)
Other Requirements
• Remote Sense all 3 Load Voltages
• Tight Monitoring Levels
• Use Circuit Breaker Function
• DC/DC Converter Feedback Resistive Divider >100kΩ
The LTC2921 suits this application because the largest
supply in the system is 5V, and only three remote sense
switches are required.
Start with the design of the resistive dividers that set the
monitor levels. As the largest supply voltage, the 5V
supply must be connected to the V
CC
pin; an internal
resistive divider sets that monitor level. Consult the
Electrical Characteristics table to confirm that V
SRC0(MIN)
>V
CC(MON)(MAX)
and V
SRC0(MAX)
<V
CC(OV)(MIN)
.
The bias current in the lower resistor for the 3.3V supply’s
dividers yields a standard 1% value of R
A1
= 49.9k:
RV
Akk
A1 0 500
10 50 49 9=µ=≈
..
LTC2921/LTC2922 Series
16
29212fa
APPLICATIO S I FOR ATIO
WUUU
Selecting R
B1
= 243k satisfies the range restrictions be-
low:
Rk
VV
VAk k
Rk
VVV
V
B MAX
B MIN
1
1
49 9 1001
1001
3 0525 0 505
0 505 0 1 49 9 244 3
49 9 1001
1001
3 5475 0 250 0 665
0 665 0 1
()
()
.•–.
.•
.–.
..•. .
.• .
–. •
..–.
.–.
=+
+µ
=
=+
+µµ
=
Ak k
•. .
49 9 241 6
Similar calculations for the 2.5V supply yield suitable
standard 1% values of R
A2
= 49.9k and R
B2
= 169k.
RV
Akk
Rk
VV
VAk k
Rk
V
A
B MAX
B MIN
2
2
2
0 500
10 50 49 9
49 9 1001
1001
2 3125 0 505
0 505 0 1 49 9 173 3
49 9 1001
1001
2 6875
=µ=≈
=+
+µ
=
=+
..
.•–.
.•
.–.
..•. .
.• .
–. •
.
()
()
++ µ
=
0 150 0 665
0 665 0 1 49 9 167 6
.–.
.–.•. .
VV
VAk k
Tie the unused V3 and V4 monitor pins to V2 for proper
operation.
2921/22 F12
RX0
100ΩRG0
10Ω
LTC2921
VCC SENSE
RX1
100Ω
RX2
100Ω
R2
4.7k
RA2
49.9k
1%
RA1
49.9k
1%
RB2
169k
1%
RB1
243k
1%
VOUT
VFB
VOUT
VFB
VOUT
VFB
RG1
10Ω
RG2
10Ω
V1
V2
V3
V4
S1
S2
S3
GATE
PG
D1
D2
D3
GND TIMER
QRST
Si1012R
CBRST
5V = 7.5%
3.3V = 7.5%
2.5V = 7.5%
Q0
Si2316DS
Q1
Si2316DS
Q2
Si2316DS
RSENSE
WSL1206
0.05Ω, 1%
CTIMER
0.22µF
10V
5V
LOAD
0.8A MAX
3.3V
LOAD
1.6A MAX
2.5V
LOAD
0.4A MAX
RESET
CGATE
0.47µF
25V
CD0
0.1µF
25V
CD1
0.1µF
25V
CD2
0.1µF
25V
CBYP
10µF
25V
DC/DC
CONVERTER
DC/DC
CONVERTER
DC/DC
CONVERTER
R1
100k
CIRCUIT BREAKER
RESET CONTROL
15 14
13
12
10
8
6
1611
1
2
3
4
9
7
5
Figure 12. Design Example of a Three-Supply Tracker and Monitor (5V, 3.3V, 2.5V)
LTC2921/LTC2922 Series
17
29212fa
APPLICATIO S I FOR ATIO
WUUU
Next, consider the supply ramping N-channel MOSFETs
Q0, Q1 and Q2. Transistor Q0 will have >4.5V of gate-
source voltage, even at maximum supply voltage (5.375V)
and minimum GATE pin voltage (10V). Considering the
voltages, temperatures, and currents involved, the maxi-
mum on-resistance (R
Q(ON)(MAX)
) of the Vishay Siliconix
Si2316DS is about 150mΩ. Switches Q1 and Q2 will see
even higher gate-source voltages, implying even smaller
R
Q(ON)(MAX)
values. Table 2 summarizes the calculated
V
Q(ON)(MAX)
voltages. Include the additional 50mV drop
across R
SENSE
when budgeting for the V
CC
supply path.
Table 2. External MOSFET Drain-Source Voltage Drops
Supply External R
Q(ON)
I
L
V
Q(ON)
Voltage MOSFET Max Max Max
120mV
5V Q0 ~150mΩ0.8A (+50mV = 170mV)
3.3V Q1 <150mΩ1.6A <240mV
2.5V Q2 <150mΩ0.4A <60mV
The ±20V absolute maximum gate-source voltage rating
of the Si2316DS easily accommodates this design.
Next, calculate the necessary capacitance on the GATE pin
to realize the desired ramp rate. Use the nominal value of
V
GATE
from the Electrical Specification, and choose a
standard value.
CAms
VFF
GATE
=µ=µ≈µ
10 500
10 8 0 463 0 47
•
...
Include drain bypass capacitors of 0.1µF and series gate
resistors of 10Ω on each external power FET to damp turn-
on oscillations.
Find the capacitance at the TIMER pin required to set the
delays in the power-on sequence:
CA
Vms F F
TIMER
=µ=µ≈µ
2
12 150 0 25 0 22
.•..
The application requires the use of the circuit breaker
function on the V
CC
supply. First, find the upper limit on the
sense resistor value:
RmV
Am
SENSE ≤= Ω
45
08 53 25
..
Select a precision power sense resistor, such as the
Vishay Dale WSL1206 series. They can be specified to 1%,
and exhibit <1% variation over the LTC2921/LTC2922
operating range; choose R
SENSE
= 50mΩ. Including toler-
ances, the circuit breaker trip current threshold variation
will be:
ImV
mA
ImV
mA
TRIP MIN
TRIP MAX
()
()
.
.
=Ω=
=Ω=
45
51 088
55
49 112
The PG pin is configured as a 2.5V negative-logic reset
signal for the microcontroller. The minimum pull-up resis-
tance for proper operation is:
RVV
mA
PG MIN()
.–.
=≈Ω
2 6875 0 4
5460
Figure 13 shows R
PG
= 4.7k. The value is somewhat
arbitrarily chosen, but it does limit the pull-down current
to <500µA. Trade off lower pull-down currents against
faster pull-up edge rates in other applications.
Recall that proper operation of the remote load sensing
function requires:
R
Q(ON)
, R
FB(ON)
<< R
X
<< (R
Y
+R
Z
)
In this example, the operating conditions and the Si2316DS
give R
Q(ON)(MAX)
= 150mΩ, the Electrical Characteristics
table guarantees R
FB(ON)
< 10Ω, and the example design
specification requires that (R
Y
+ R
Z
) <100k. Selecting R
X0
= R
X1
= R
X2
= 100Ω satisfies the inequality.
Before the loads are connected to the supplies, the voltage
error due to the R
X
resistors will be <0.1% for all three
supplies:
∆= Ω
==VV k
Vof V
SRC SRC SRC SRC
•.%
100
100 1000 01
After the remote sense switches close, the load voltage
errors due to R
X
at maximum loads will be:
LTC2921/LTC2922 Series
18
29212fa
APPLICATIO S I FOR ATIO
WUUU
∆= Ω Ω
Ω
=
=
∆= Ω Ω
Ω
=
=
∆= Ω Ω
Ω
=
=
VAm mV
of V
VAm mV
of V
VAm mV
of
L
L
L
0
1
2
0 8 150 10
100 12
024 5
1 6 150 10
100 24
073 33
0 4 150 10
100 6
024 2
–. • • –
–. %
–. • • –
–. % .
–. • • –
–. % .55V
Confirm that the currents through the remote sense
switches are less than the Absolute Maximum Ratings:
The pull-down transistor Q5 on the V1 pin is a circuit
breaker reset mechanism. Choose the transistor to pull
down V
V1
below the reset threshold under worst-case
conditions, and choose a gate-grounding resistor based
on speed and current considerations. The Vishay Siliconix
Si1012R and a 100k resistor proved sufficient for this
design. Finally, bypass the V
CC
pin with a 10µF capacitor.
TYPICAL APPLICATIO S
U
Five-Supply Tracker and Monitor (3.3V, 2.5V, 1.8V, 1.5V, 1.2V)
2921/22 TA02
R
G2
10Ω
LTC2922-3.3
V
CC
SENSE
R2
4.7k
R
A4
49.9k
1%
R
A3
49.9k
1%
R
B4
60.4k
1%
R
B3
86.6k
1%
V
OUT
V
FB
V
OUT
V
FB
V
OUT
V
FB
R
G3
10Ω
R
G4
10Ω
V1
V2
V3
V4
S0
S1
S2
S3
S4
GATE
PG
D0
D1
D2
D3
D4
GND TIMER
QRST
Si1012R
CBRST
1.8V ± 5%
1.5V ± 5%
1.2V ± 5%
Q2
Si2316DS
Q3
Si2316DS
Q4
Si2316DS
R
SENSE
WSL1206
0.05Ω, 1%
C
TIMER
0.22µF
10V
1.8V
LOAD
1.6A MAX
1.5V
LOAD
1.4A MAX
1.2V
LOAD
1.2A MAX
RESET
C
GATE
0.47µF
25V
C
D2
0.1µF
25V
C
D3
0.1µF
25V
C
D4
0.1µF
25V
C
BYP
10µF
25V
DC/DC
CONVERTER
DC/DC
CONVERTER
DC/DC
CONVERTER
V
OUT
V
FB
V
OUT
V
FB
R
G0
10Ω
R
G1
10Ω
3.3V± 10%
2.5V ± 5%
Q0
Si2316DS
Q1
Si2316DS
3.3V
LOAD
0.8A MAX
2.5V
LOAD
2.3A MAX
C
D0
0.1µF
25V
C
D1
0.1µF
25V
DC/DC
CONVERTER
DC/DC
CONVERTER
R
A2
49.9k
1%
R
B2
113k
1%
R
A1
49.9k
1%
R
B1
178k
1%
R
X0
100Ω
R
X1
100Ω
R
X2
100Ω
R
X3
100Ω
R
X4
100Ω
R1
100k
19 18
17
16
20
14
12
10
8
215
7
9
11
1
6
5
4
3
13
CIRCUIT BREAKER
RESET CONTROL
PG PIN AS RESET
WITH PULL-UP
TO 2.5V
IA
mmA
IA
mmA
IA
mmA
DS
DS
DS
1
2
3
08 150
100 12
16 150
100 24
04 150
100 06
=Ω
Ω
=
=Ω
Ω
=
=Ω
Ω
=
.• .
.• .
.• .
LTC2921/LTC2922 Series
19
29212fa
F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
PACKAGE DESCRIPTIO
U
F20 TSSOP 0502
0.09 – 0.20
(.0036 – .0079)
0° – 8°
0.45 – 0.75
(.018 – .030)
4.30 – 4.50**
(.169 – .177)
6.40
BSC
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
20 19 18 17 16 15
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
2
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05 0.65 TYP
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
GN16 (SSOP) 0502
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 TYP.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2921/LTC2922 Series
20
29212fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPO RATION 2003
LT/TP 0404 1K REV A • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIO
U
PART NUMBER DESCRIPTION COMMENTS
LTC2900 Programmable Quad Supply Monitor Adjustable RESET Timer, 10-Lead MSOP Package
LTC2901 Programmable Quad Supply Monitor with Watchdog Adjustable RESET Timer and Watchdog Timer,
Individual Comparator Outputs
LTC2902 Programmable Quad Supply Monitor Adjustable RESET Timer, Selectable Tolerance,
RESET Disable for Margining.
LTC4211 Hot Swap Controller with Multifunction Current Control Operates from 2.5V to 16.5V, 10-Lead MSOP Package
LTC4230 Triple Hot Swap Controller with Multifunction Current Control Operates from 1.7V to 16.5V, Supply Tracking
Early-Late Supply Sequencer with Early Supplies LED Indicator
2921/22 TA03
RG2
10Ω
LTC2922
VCC SENSE
RA4
49.9k
1%
RA3
49.9k
1%
RB4
162k
1%
RB3
232k
1%
VOUT
VFB
VOUT
VFB
VOUT
VFB
RG3
10Ω
RG4
10Ω
V1
V2
V3
V4
S0
S1
S2
S3
S4
GATE
PG
D0
D1
D2
D3
D4
GND TIMER
QRST
Si1012R
CBRST
1.8V ± 5%
3.3V ± 10%
2.5V ± 10%
Q2
Si2316DS
Q3
Si2316DS
Q4
Si2316DS
RSENSE
WSL1206
0.05Ω, 1%
CTIMER
0.22µF
10V
1.8V
EARLY
1.5A MAX
3.3V
LATE
2.5V
LATE
CGATE
0.47µF
25V
CD2
0.1µF
25V
CD3
0.1µF
25V
CD4
0.1µF
25V
CBYP
10µF
25V
DC/DC
CONVERTER
DC/DC
CONVERTER
DC/DC
CONVERTER
VOUT
VFB
VOUT
VFB
RG0
10Ω
RG1
10Ω
5V ± 10%
2.5V ± 5%
Q0
Si2316DS
Q1
Si2316DS
5V
EARLY
0.8A MAX
2.5V
EARLY
1.5A MAX
CD0
0.1µF
25V
CD1
0.1µF
25V
DC/DC
CONVERTER
DC/DC
CONVERTER
RA2
49.9k
1%
RB2
113k
1%
RA1
49.9k
1%
RB1
169k
1%
RX0
100Ω
RX1
100Ω
RX2
100Ω
R1
100k
CPG
0.22µF
25V
19 18
17
16
20
14
12
10
8
215
7
9
11
1
6
5
4
3
13
CIRCUIT BREAKER
RESET CONTROL
PG PIN AS
SEQUENCED
GATE DRIVER
EARLY
VOLTAGES
ON
R6
330Ω
tGATE ~ 500ms
tPG ~ 600ms