IDT5V9950PFG - Integrated Device Technology

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

sOE

1Q0

Skew

Select 1Q1

1F1:0

2Q0

Skew

Select 2Q1

2F1:0

REF PLL

3Q0

Skew

Select 3Q1

3F1:0

4Q0

4Q1

Skew

Select

4F1:0

PE TEST

MARCH 2001

2001 Integrated Device Technology, Inc. DSC-5870/-c

IDT5V9950

ADVANCED

INFORMATION

INDUSTRIAL TEMPERATURE RANGE

3.3V PROGRAMMABLE

SKEW PLL CLOCK DRIVER

TURBOCLOCK™ II JR.

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended

for high performance computing and data-communications applications. A

key feature of the programmable skew is the ability of outputs to lead or lag

the REF input signal. The IDT5V9950 has eight programmable skew

outputs in four banks of 2. Skew is controlled by 3-level input signals that

may be hard-wired to appropriate HIGH-MID-LOW levels.

When the sOE pin is held low, all the outputs are synchronously enabled.

However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are

synchronously disabled.

Furthermore, when PE is held high, all the outputs are synchronized with

the positive edge of the REF clock input. When PE is held low, all the outputs

are synchronized with the negative edge of REF. The IDT5V9950 has

LVTTL outputs with 12mA balanced drive outputs.

FEATURES:

• REF is 5V tolerant

• 4 pairs of programmable skew outputs

• Low skew: 185ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

• Synchronous output enable

• Input frequency: 6MHz to 200MHz

• Output frequency: 6MHz to 200MHz

• 2x, 4x, 1/2, and 1/4 outputs

• 3-level inputs for skew and PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <100ps cycle-to-cycle

• Available in 32-pin TQFP Package

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

PIN CONFIGURATION

TQFP

TOP VIEW

30 29 28 27 26 25

11 12 13 14 15 16

REF

GND

TEST

DDQ

GND

3F1

4F0

4F1

4Q1

4Q0

GND

VDDQ

18 GND

sOE

1F1

1F0

1Q0

1Q1

VDDQ

17 GND

PR32

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Rating Max. Unit

DDQ

DD Supply Voltage to Ground –0.5 to +4.6 V

VIDC Input Voltage –0.5 to VDD+0.5 V

REF Input Voltage –0.5 to +5.5 V

Maximum Power TA = 85°C 0.7 W

Dissipation TA = 55°C 1.1 W

TSTG Storage Temperature Range –65 to +150 °C

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

CAPACITANCE

(TA = 25° C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance 5 7 pF

NOTE:

1. Capacit anc e appl i es to all inputs except TEST, FS, and nF[1: 0] .

PIN DESCRIPTION

Pin Name Type Description

REF IN Reference Clock Input

FB IN Feedback Input

TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control

Summary Table) remain in effect. Set LOW for normal operation.

sOE (1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1

may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act

as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down).

PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the

reference clock (has internal pull-up).

nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions

FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)

nQ[1:0] OUT Four banks of two outputs with programmable skew

VDDQ PWR Power supply for output buffers

VDD PWR Power supply for phase locked loop and other internal circuitry

GND PWR Ground

NOTE:

1. When TEST = M ID and sOE = HIGH, PLL remains active with nF[1:0] = LL func tioning as an output di sable control f or i ndi vidual output banks. Skew

selections remain in ef f ect unless nF[1:0] = LL.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate

requirements for special timing relationships between clocked compo-

nents. Skew is selectable as a multiple of a time unit (tU) which ranges

from 625ps to 1.3ns (see Programmable Skew Range and Resolution

Table). There are nine skew configurations available for each output

pair. These configurations are chosen by the nF1:0 control pins. In order

to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)

are used, they are intended for but not restricted to hard-wiring. Undriven

3-level inputs default to the MID level. Where programmable skew is

not a requirement, the control pins can be left open for the zero skew

default setting. The Control Summary Table shows how to select specific

skew taps by using the nF1:0 control pins.

PROGRAMMABLE SKEW

EXTERNAL FEEDBACK

By providing external feedback, the IDT5V9950 gives users flexibility

with regard to skew adjustment. The FB signal is compared with the

input REF signal at the phase detector in order to drive the VCO. Phase

differences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

FS = LOW FS = MID FS = HIGH Comments

Timing Unit Calculation (tU) 1/(32 x FNOM) 1/(16 x FNOM)1/(8 x F

NOM)

VCO Frequency Range (FNOM) (1,2) 24 to 50MHz 48 to 100MHz 96 to 200 MHz

Skew Adjustment Range (3)

Max Adjustment: ±7.8125ns ±7.8125ns ±7.8125ns ns

±67.5º ±135º ±270º Phase Degrees

±18.75% ±37.5% ±75% % of Cycle Time

Example 1, FNOM = 25MHz tu = 1.25ns — —

Example 2, FNOM = 37.5MHz tu = 0.833ns — —

Example 3, FNOM = 50MHz tu = 0.625ns tu = 1.25ns —

Example 4, FNOM = 75MHz — tu = 0.833ns —

Example 5, FNOM = 100MHz — tu = 0.625ns tu = 1.25ns

Example 6, FNOM = 150MHz — — tu = 0.833ns

Example 7, FNOM = 200MHz — — tu = 0.625ns

NOTES:

1. The device may be operated outsi de recommended frequency ranges without damage, but functional operat i on i s not guaranteed.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always

appears at 1Q1:0, 2Q1:0, and the higher out puts when they are operated in t heir undiv ided m odes. The frequenc y appearing at the RE F and FB input s

will be the same as VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO

frequency when the part is configured for frequency m ul tiplicati on by using a divided out put as the FB input .

3. Skew adj ustment range assumes that a z ero skew output is used for f eedback. I f a skewed Q output is used for feedback, then adjustm ent range wil l

be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is

programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest

FNOM value.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4)

LL (1) –4tUDivide by 2 Divide by 2

LM –3tU–6tU–6tU

LH –2tU–4tU–4tU

ML –1tU–2tU–2tU

MM Zero Skew Zero Skew Zero Skew

MH 1tU2tU2tU

HL 2tU4tU4tU

HM 3tU6tU6tU

HH 4tUDivide by 4 Inverted (2)

NOTES:

1. LL disables outputs if TE S T = M ID and sOE = HIGH.

2. When pair #4 is s et to HH (inverted), sOE disabl es pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.

RECOMMENDED OPERATING RANGE

Symbol Description Min. Typ. Max. Unit

VDD/VDDQ Power Supply Voltage 3 3.3 3.6 V

TAAmbient Operating Temperature -40 — +85 °C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Conditions Min. Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V

VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 0.8 V

VIHH Input HIGH Voltage (1) 3-Level Inputs Only VDD−0.6 — V

VIMM Input MID Voltage (1) 3-Level Inputs Only VDD/2−0.3 VDD/2+0.3 V

VILL Input LOW Voltage (1) 3-Level Inputs Only — 0.6 V

IIN Input Leakage Current

(REF, FB Inputs Only) VIN = VDD or GND

VDD = Max. −5+5µA

IN = VDD HIGH Level — +200

I33-Level Input DC Current VIN = VDD/2 MID Level −50 +50 µA

(TEST, FS, nF[1:0]) VIN = GND LOW Level −200 —

IPU Input Pull-Up Current (PE) VDD = Max., VIN = GND −100 — µA

IPD Input Pull-Down Current (sOE)V

DD = Max., VIN = VDD — +100 µA

VOH Output HIGH Voltage VDDQ = Min., IOH = −12mA 2.4 — V

VOL Output LOW Voltage VDDQ = Min., IOL = 12mA — 0.4 V

NOTE:

1. These inputs are normally wired t o VDD, GND, or unconnect ed. Internal terminat ion resistors bi as unconnected inputs to VDD/2. If these inputs are

switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are

achieved.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Typ. (2) Max. Unit

IDDQ Quiescent Power Supply Current VDD = Max., TEST = MID, REF = LOW,

PE = LOW, sOE = LOW

All outputs unloaded

20 30 mA

∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 3V 1 30 µA

FS = L 190 290

IDDD Dynamic Power Supply Current per Output FS = M 150 230 µA/MHz

FS = H 130 200

FS = L , FVCO = 50MHz, CL = 0pF 56 —

ITOT Total Power Supply Current FS = M , FVCO = 100MHz, CL = 0pF 80 — m A

FS = H, FVCO = 200MHz, CL = 0pF 125 —

NOTES:

1. Measurements are for divide-by-1 out puts and DS[1:0] = MM.

2. For nominal voltage and temperature.

INPUT TIMING REQUIREMENTS

Symbol Description (1) Min. Max. Unit

tR, tFMaximum input rise and fall times, 0.8V to 2V — 10 ns/V

tPWC Input clock pulse, HIGH or LOW 2 — ns

DHInput duty cycle 10 90 %

FS = LOW 6 50

FREF Reference clock input frequency FS = MID 12 100 MHz

FS = HIGH 24 200

NOTE:

1. Where pulse wi dt h i mplied by DH is less than tPWC limit, tPWC limit applies.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Min. Typ. Max. Unit

FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table

tRPWH REF Pulse Width HIGH (10) 2——ns

RPWL REF Pulse Width LOW (10) 2——ns

Programmable Skew Time Unit See Control Summary Table

tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1) (1,2) — 50 185 ps

tSKEW0 Zero Output Skew (All Outputs) (3) — 0.1 0.25 ns

tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) (4) — 0.1 0.25 ns

tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) (4) —0.20.5ns

SKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) (4) — 0.15 0.5 ns

tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) (1) —0.30.9ns

DEV Device-to-Device Skew (1,5) — — 0.75 ns

t(φ)REF Input to FB Static Phase Offset (7) −0.25 0 0.25 ns

tODCV Output Duty Cycle Variation from 50% −101ns

PWH Output HIGH Time Deviation from 50% (8) ——1.5ns

PWL Output LOW Time Deviation from 50% (9) ——2ns

ORISE Output Rise Time 0.15 0.7 1.5 ns

tOFALL Output Fall Time 0.15 0.7 1.5 ns

tLOCK PLL Lock Time (6) ——0.5ms

CCJH Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = H) — — 100

tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = M) — — 150 ps

tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak)

(divide by 1 output frequency, FS = L) — — 200

NOTES:

1. S kew is the t im e between the earl ies t and t he lates t out put t ransit ion am ong all out puts for whic h the sam e tU del ay has been s elected when al l are

loaded with t he s pecified load.

2. tSKEWPR i s the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are select ed for 0tU.

3. tSK(0) is the s kew between outputs when they are selected for 0tU.

4. There are 3 classes of outputs: Nominal (multiple of tU delay ), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx onl y

in Divide-by-2 or Divide-by-4 mode). Test condit i on: nF0:1 = MM is set on unused output s .

5. tDEV is the output-to-output skew between any t wo devices operati ng under t he same conditions (VDDQ, VDD, ambient temperature, air f l ow, etc.)

6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal

operating lim i ts. This param et er i s measured from t he appl i cation of a new si gnal or f requency at REF or FB until tPD is within specified limits.

7. tφ is m easured with REF input ri se and fall tim es (from 0.8V t o 2V ) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.

8. Measured at 2V .

9. Measured at 0.8V.

10. Ref er to Input Timing Requi rem ent s table for more det ai l .

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

AC TEST LOADS AND WAVEFORMS

2.0V

tPWL

tPWH

tORISE tOFALL

0.8V

≤1ns ≤1ns

2.0V

0.8V

3.0V

VTH = 1.5V

150Ω

VDDQ

Output

150Ω20pF

VTH = 1.5V

LVTTL INPUT TEST WAVEFORM

LVTTL OUTPUT WAVEFORM

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

REF

OTHER Q

INVERTED Q

REF D IVIDED BY 2

REF D IVIDED BY 4

tREF

tSKEW2

tSKEW 3, 4

tSKEW 1 , 3, 4 tSKEW 2, 4

tSKEW 3, 4

tSKEW2

tSKEWPR

tSKEW 0, 1

tCCJH,M,L

tODCV tODCV

tRPWH

tRPWL

tSKEWPR

tSKEW 0, 1

t(φ)

AC TIMING DIAGRAM

NOTES:

PE: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs

change on the negati ve edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 s i gnal s align.

Skew: The time bet ween the earliest and t he latest out put transit ion among all outputs for which the s ame tU delay has been s elected when all are

loaded with 20pF and t erm i nat ed wi th 75Ω to VDDQ/2.

tSKEWPR: The skew bet ween a pai r of outputs (xQ0 and xQ1) when al l ei ght outputs are sel ected for 0tU.

tSKEW0: The skew bet ween out puts when they are s el ec ted for 0tU.

tDEV: The output-to-output skew between any two devices operating under the same conditions (V DDQ, VDD, ambient temperature, air flow, etc.)

tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included i n t SKEW2 and tSKEW4 specifications.

tPWH is measured at 2V.

tPWL is m easured at 0.8V.

tORISE and tOFALL are measured between 0. 8V and 2V.

tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal

operating lim i ts. This param et er i s measured from t he appl i cation of a new si gnal or f requency at REF or FB until tPD is within specified limits.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

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Santa Clara, CA 95054 fax: 408-492-8674

www.idt.com*

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The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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ORDERING INFORMATION

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Package

Device Type

5V9950 3.3V Program m able S kew P LL C lock

D riv e r Tu rb o Clo c k II Jr.

Thin Qu ad Flat Pack (PR 32)