8-Output Very Low-Power PCIe Gen1-4 Clock Generator with Zo = 100ohms 9FGV0841 DATASHEET Description Features The 9FGV0841 is a member of IDT's SOC-friendly 1.8V very low-power PCIe clock family. It has integrated output terminations providing Zo = 100 for direction connection to 100 transmission lines. The device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off, and 2 selectable SMBus addresses. * Direct connection to 100 transmission lines; saves 32 * * Typical Applications * * PCIe Gen1-4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points * Output Features * * 8 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with * * Zo = 100 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL) support * * Key Specifications * * * * DIF cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps DIF phase jitter is PCIe Gen1-4 compliant REF phase jitter is < 1.5ps RMS * * * * resistors compared to standard PCIe devices 62mW typical power consumption; reduced thermal concerns Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings OE# pins; support DIF power management LP-HCSL differential clock outputs; reduced power and board space Programmable slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments DIF outputs blocked until PLL is locked; clean system start-up Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI External 25MHz crystal; supports tight ppm with 0 ppm synthesis error Configuration can be accomplished with strapping pins; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Selectable SMBus addresses; multiple devices can easily share an SMBus segment Space saving 6 x 6 mm 48-VFQFPN; minimal board space Block Diagram vOE(7:0)# 8 REF1.8 XIN/CLKIN_25 X2 OSC DIF7 DIF6 DIF5 SS Capable PLL DIF3 vSADR vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 9FGV0841 JANUARY 24, 2018 DIF4 DIF2 CONTROL LOGIC DIF1 DIF0 1 (c)2018 Integrated Device Technology, Inc. 9FGV0841 DATASHEET vOE5# VDD1.8 VDDIO GND DIF6 DIF6# vOE6# DIF7 DIF7# vOE7# VDDIO ^CKPWRGD_PD# Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 vSS_EN_tri GNDXTAL X1_25 X2 VDDXTAL1.8 VDDREF1.8 vSADR/REF1.8 GNDREF GNDDIG SCLK_3.3 SDATA_3.3 VDDDIG1.8 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 9FGV0841 DIF5# DIF5 vOE4# DIF4# DIF4 VDDIO VDDA1.8 GNDA vOE3# DIF3# DIF3 vOE2# DIF2 DIF2# GND VDDIO DIF1# VDD1.8 DIF1 DIF0# vOE1# DIF0 vOE0# VDDIO 13 14 15 16 17 18 19 20 21 22 23 24 6 x 6 mm 48-VFQFPN, 0.4mm pitch vv prefix indicates internal 60kOhm pull-down resistor v prefix indicates internal 120kOhm pull-down resistor ^ prefix indicates internal 120kOhm pull-up resistor SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 1 Address 1101000 1101010 + Read/Write Bit x x Power Management Table SMBus DIFx REF OEx# True O/P Comp. O/P OE bit 0 X X Low Low Hi-Z1 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is Low. CKPWRGD_PD# Power Connections Pin Number VDD 5 6 VDDIO 12 20,38 30 GND 2 8 9 13,21,31,39, 47 Description XTAL OSC REF Power Digital (dirty) Power 22,29,40 DIF outputs 29 PLL Analog 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 2 JANUARY 24, 2018 9FGV0841 DATASHEET Pin Descriptions PIN # PIN NAME 1 vSS_EN_tri 2 3 4 5 6 GNDXTAL X1_25 X2 VDDXTAL1.8 VDDREF1.8 7 vSADR/REF1.8 TYPE LATCHED IN GND IN OUT PWR PWR LATCHED I/O GND GND IN I/O PWR PWR 8 9 10 11 12 13 GNDREF GNDDIG SCLK_3.3 SDATA_3.3 VDDDIG1.8 VDDIO 14 vOE0# IN 15 16 DIF0 DIF0# OUT OUT 17 vOE1# IN 18 19 20 21 22 23 24 DIF1 DIF1# VDD1.8 VDDIO GND DIF2 DIF2# OUT OUT PWR PWR GND OUT OUT 25 vOE2# IN 26 27 DIF3 DIF3# OUT OUT 28 vOE3# IN 29 30 31 32 33 GNDA VDDA1.8 VDDIO DIF4 DIF4# 34 vOE4# IN 35 36 DIF5 DIF5# OUT OUT 37 vOE5# IN 38 39 VDD1.8 VDDIO PWR PWR JANUARY 24, 2018 GND PWR PWR OUT OUT 3 DESCRIPTION Latched select input to select spread spectrum amount at initial power up : 1 = -0.5% spread, M = -0.25%, 0 = Spread Off GND for XTAL Crystal input, Nominally 25.00MHz. Crystal output. Power supply for XTAL, nominal 1.8V VDD for REF output. nominal 1.8V. Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin Ground pin for the REF outputs. Ground pin for digital circuitry Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. 1.8V digital power (dirty power) Power supply for differential outputs Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Power supply, nominal 1.8V Power supply for differential outputs Ground pin. Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Ground pin for the PLL core. 1.8V power for the PLL core. Power supply for differential outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 5. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Power supply, nominal 1.8V Power supply for differential outputs 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET Pin Descriptions (cont.) PIN # PIN NAME 40 GND 41 DIF6 42 DIF6# TYPE GND OUT OUT 43 vOE6# IN 44 45 DIF7 DIF7# OUT OUT 46 vOE7# IN 47 VDDIO PWR 48 ^CKPWRGD_PD# IN DESCRIPTION Ground pin. Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 6. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Differential true clock output Differential Complementary clock output Active low input for enabling DIF pair 7. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs Power supply for differential outputs Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 4 JANUARY 24, 2018 9FGV0841 DATASHEET Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs Zo=100ohm 2pF Rs 2pF Device REF Output Test Load Zo = 50 ohms 33 5pF REF Output Alternate Terminations 3.3V Driving LVDS Cc R7a R7b R8a R8b Rs Zo Cc Rs LVDS Clock input Device Driving LVDS inputs Component R7a, R7b R8a, R8b Cc Vcm JANUARY 24, 2018 Value Receiver has Receiver does not termination have termination Note 10K ohm 140 ohm 5.6K ohm 75 ohm 0.1 uF 0.1 uF 1.2 volts 1.2 volts 5 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9FGV0841. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VDDxx VIN VIHSMB Ts Tj ESD prot Applies to all VDD pins MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model UNITS NOTES MAX 2.5 VDD+0.5V 3.6V 150 125 V V V C C V 2000 1,2 1, 3 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. Electrical Characteristics-Current Consumption TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Operating Supply Current Wake-on-LAN Current (CKPWRGD_PD# = '0' Byte 3, bit 5 = '1') Powerdown Current (CKPWRGD_PD# = '0' Byte 3, bit 5 = '0') 1 2 SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES IDDAOP VDDA, All outputs active @100MHz 6 9 mA IDDOP All VDD, except VDDA and VDDIO, All outputs active @100MHz 12 16 mA IDDIOOP VDDIO, All outputs active @100MHz 28 35 mA IDDAPD VDDA, DIF outputs off, REF output running All VDD, except VDDA and VDDIO, DIF outputs off, REF output running VDDIO, DIF outputs off, REF output running VDDA, all outputs off All VDD, except VDDA and VDDIO, all outputs off VDDIO, all outputs off 0.4 1 mA 2 5.3 8 mA 2 0.04 0.4 0.6 0.0005 0.1 1 1 0.1 mA mA mA mA 2 I DDPD I DDIOPD IDDAPD I DDPD I DDIOPD Guaranteed by design and characterization, not 100% tested in production. This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1) Electrical Characteristics-DIF Output Duty Cycle, Jitter, and Skew Characteristics TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Duty Cycle Skew, Output to Output Jitter, Cycle to cycle tDC tsk3 Measured differentially, PLL Mode Averaging on, VT = 50% 45 50 43 14 55 50 50 tjcyc-cyc UNITS NOTES % ps ps 1,2 1,2 1,2 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 6 JANUARY 24, 2018 9FGV0841 DATASHEET Electrical Characteristics-Input/Supply/Common Parameters-Normal Operating Conditions TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Supply Voltage VDDxx Output Supply Voltage VDDIO Ambient Operating Temperature Input High Voltage Input Mid Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Input Frequency Pin Inductance Capacitance TAMB VIH VIM VIL VIH VIL IIN IINP Fin Lpin CIN COUT Clk Stabilization TSTAB SS Modulation Frequency fMOD OE# Latency tLATOE# Tdrive_PD# tDRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR VILSMB VIHSMB VOLSMB IPULLUP VDDSMB tRSMB t FSMB CONDITIONS Supply voltage for core, analog and single-ended LVCMOS outputs Supply voltage for differential Low Power Outputs MIN TYP MAX 1.7 1.8 1.9 UNITS NOTES V 0.9975 1.05-1.8 1.9 V Commercial range Industrial range Single-ended inputs, except SMBus Single-ended tri-level inputs ('_tri' suffix) Single-ended inputs, except SMBus Single-ended outputs, except SMBus. IOH = -2mA Single-ended outputs, except SMBus. IOL = -2mA Single-ended inputs, VIN = GND, VIN = VDD Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors XTAL, or X1 input 0 -40 0.75 VDD 0.4 VDD -0.3 VDD-0.45 25 25 70 85 VDD + 0.3 0.6 VDD 0.25 VDD Logic Inputs, except DIF_IN Output pin capacitance From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Rise time of single-ended control inputs VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V @ IPULLUP @ VOL 1.5 fMAXSMB -5 0.45 5 C C V V V V V uA -200 200 uA 27 7 5 6 MHz nH pF pF 1 1 1 0.6 1.8 ms 1,2 30 31.6 33 kHz 1 1 3 3 clocks 1,3 20 300 us 1,3 5 5 0.6 3.6 0.4 2 2 1 23 0.5 VDD 25 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 3.6 1000 300 ns ns V V V mA V ns ns Maximum SMBus operating frequency 400 kHz 2.1 4 1.7 4 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 For VDDSMB < 3.3V, VIHSMB >= 0.65xVDDSMB 2 JANUARY 24, 2018 7 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET Electrical Characteristics-DIF Low Power HCSL Outputs TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Slew rate Trf Slew rate matching Trf Voltage High VHIGH CONDITIONS MIN TYP Scope averaging on fast setting Scope averaging on slow setting Slew rate matching, Scope averaging on 1.6 1.3 2.3 1.9 7 3.5 2.9 20 660 784 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs -Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns V/ns % 1,2,3 1,2,3 1,2,4 7 mV -150 -33 150 816 -42 1634 427 12 1150 -300 300 250 550 140 7 mV mV mV mV 7 7 1,2,7 1,5,7 1,6,7 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 2 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute. 7 At default SMBus amplitude settings. Electrical Characteristics-Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions SYMBOL PARAMETER CONDITIONS tjphPCIeG1-CC PCIe Gen 1 PCIe Gen 2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) tjphPCIeG2-CC PCIe Gen 2 High Band Phase Jitter, 1.5MHz < f < Nyquist (50MHz) PLL Mode (PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz) PCIe Gen 3 tjphPCIeG3-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) PCIe Gen 4 tjphPCIeG4-CC (PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) Notes on PCIe Filtered Phase Jitter Table 1 Applies to all differential outputs, guaranteed by design and characterization. 2 Calculated from Intel-supplied Clock Jitter Tool, with spread on and off. 3 Specification UNITS NOTES Limit MIN TYP MAX 21 25 35 86 0.9 0.9 1.1 3 ps (rms) 1, 2 1.5 1.6 1.9 3.1 ps (rms) 1, 2 0.3 0.37 0.44 1 0.3 0.37 0.44 0.5 ps (p-p) 1, 2, 3 ps (rms) ps (rms) 1, 2 1, 2 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 8 JANUARY 24, 2018 9FGV0841 DATASHEET Electrical Characteristics-REF TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 25 MHz output Byte 3 = 1F, 20% to 80% of VDDREF 0.6 Rise/Fall Slew Rate trf1 Byte 3 = 5F, 20% to 80% of VDDREF 0.9 Rise/Fall Slew Rate trf1 Byte 3 = 9F, 20% to 80% of VDDREF 1.1 Rise/Fall Slew Rate trf1 Rise/Fall Slew Rate trf1 Byte 3 = DF, 20% to 80% of VDDREF 1.1 VT = VDD/2 V 45 Duty Cycle dt1X VT = VDD/2 V 0 Duty Cycle Distortion dtcd VT = VDD/2 V Jitter, cycle to cycle tjcyc-cyc Noise floor tjdBc1k 1kHz offset 10kHz offset to Nyquist Noise floor tjdBc10k Jitter, phase tjphREF 12kHz to 5MHz TYP 0 40 1 1.4 1.7 1.8 49.1 2 19.1 -129.8 -143.6 MAX 0.63 1.5 1.6 2.2 2.7 2.9 55 4 250 -105 -115 UNITS ppm ns V/ns V/ns V/ns V/ns % % ps dBc dBc ps (rms) Notes 1,2 2 1 1,3 1 1 1,4 1,5 1,4 1,4 1,4 1,4 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz 3 Default SMBus Value 4 When driven by a crystal. 5 When driven by an external oscillator via the X1 pin, X2 should be floating. 2 Clock Periods-Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC + ppm - ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term Period AbsPer Average Average Average Nominal Min Min Min Max 9.94900 9.99900 10.00000 10.00100 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.05100 ns 1,2 Clock Periods-Differential Outputs with Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 Measurement Window 1us 0.1s 0.1s 0.1s -SSC + ppm - ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term AbsPer Period Average Average Average Min Nominal Min Min Max 9.94906 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.10107 ns 1,2 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz JANUARY 24, 2018 9 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET General SMBus Serial Interface Information How to Write * * * * * * * * * * How to Read Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a stop bit Index Block Write Operation Controller (Host) IDT (Slave/Receiver) T * * * Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Controller (Host) starT bit T Slave Address WR * * * * * * * * * * * IDT (Slave/Receiver) starT bit Slave Address WRite ACK WR WRite ACK Beginning Byte = N Beginning Byte = N ACK ACK Data Byte Count = X ACK RT Beginning Byte N ACK X Byte O O O Repeat starT Slave Address RD ReaD ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit X Byte P O Note: SMBus address is latched on SADR pin. O O O O O Byte N + X - 1 N Not acknowledge P stoP bit 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 10 JANUARY 24, 2018 9FGV0841 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 DIF OE7 Output Enable RW Low/Low Bit 7 DIF OE6 Output Enable RW Low/Low Bit 6 DIF OE5 Output Enable RW Low/Low Bit 5 DIF OE4 Output Enable RW Low/Low Bit 4 DIF OE3 Output Enable RW Low/Low Bit 3 DIF OE2 Output Enable RW Low/Low Bit 2 DIF OE1 Output Enable RW Low/Low Bit 1 DIF OE0 Output Enable RW Low/Low Bit 0 1. A low on these bits will override the OE# pin and force the differential output Low/Low SMBus Table: SS Readback and Control Register Byte 1 Name Control Function SSENRB1 SS Enable Readback Bit1 Bit 7 SSENRB1 SS Enable Readback Bit0 Bit 6 SSEN_SWCNTRL Bit 5 Enable SW control of SS SSENSW1 SS Enable Software Ctl Bit1 Bit 4 SSENSW0 SS Enable Software Ctl Bit0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 Bit 7 SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 Bit 6 SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 Bit 5 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 Bit 4 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 Bit 3 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 Bit 2 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 Bit 1 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 Bit 0 Type 0 1 00' for SS_EN_tri = 0, '01' for SS_EN_tri R = 'M', '11 for SS_EN_tri = '1' R RW Values in B1[7:6] Values in B1[4:3] control SS amount control SS amount. RW 1 RW 1 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS RW RW 00 = 0.6V 10= 0.8V Type RW RW RW RW RW RW RW RW 0 Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register Byte 3 Name Control Function Type RW Bit 7 REF Slew Rate Control RW Bit 6 Bit 5 REF Power Down Function Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REF OE Wake-on-Lan Enable for REF REF Output Enable Reserved Reserved Reserved Reserved 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled 01 = 0.7V 11 = 0.9V Fast Fast Fast Fast Fast Fast Fast Fast 1 Setting Setting Setting Setting Setting Setting Setting Setting 0 1 00 = Slowest 01 = Slow 10 = Fast 11 = Faster REF does not run in REF runs in Power RW Power Down Down RW Low Enabled Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 0 1 0 1 1 1 1 1 Byte 4 is Reserved JANUARY 24, 2018 11 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming Type RW RW RW RW RW 0 1 A rev = 0001 0001 = IDT 0 1 00 = FGx, 01 = DBx ZDB/FOB, 10 = DMx, 11= DBx FOB 001000 binary or 08 hex 0 Default 0 0 0 1 0 0 0 1 Default 0 0 0 0 1 0 0 0 1 Default 0 0 0 0 1 Writing to this register will configure how 0 many bytes will be read back, default is 0 = 8 bytes. 0 Recommended Crystal Characteristics (3225 package) PARAMETER VALUE UNITS NOTES Frequency Resonance Mode Frequency Tolerance @ 25C Frequency Stability, ref @ 25C Over Operating Temperature Range Temperature Range (commercial) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year Notes: 1. FOX 603-25-150. 2. For I-temp, FOX 603-25-261. 25 Fundamental 20 MHz PPM Max 1 1 1 20 PPM Max 1 0~70 -40~85 50 7 8 0.3 5 C C Max pF Max pF Max mW Max PPM Max 1 2 1 1 1 1 1 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 12 JANUARY 24, 2018 9FGV0841 DATASHEET Thermal Characteristics PARAMETER Thermal Resistance SYMBOL CONDITIONS PKG Junction to Case JC Junction to Base Jb Junction to Air, still air JA0 NDG48 Junction to Air, 1 m/s air flow JA1 Junction to Air, 3 m/s air flow JA3 Junction to Air, 5 m/s air flow JA5 TYP. 33 2.1 37 30 27 26 UNITS C/W C/W C/W C/W C/W C/W NOTES 1 1 1 1 1 1 1 ePad soldered to board Marking Diagrams ICS GV0841AIL YYWW COO LOT ICS FGV0841AL YYWW COO LOT Notes: 1. Line 2 is the truncated part number. 2. "L" denotes RoHS compliant package. 3. "I" denotes industrial temperature grade. 4. "YYWW" is the last two digits of the year and week that the part was assembled. 5. "COO" denotes country of origin. 6. "LOT" is the lot number. JANUARY 24, 2018 13 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 9FGV0841 DATASHEET Package Outline Drawings (NDG48P2, 6 x 6 mm 48-VFQFPN) 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 14 JANUARY 24, 2018 9FGV0841 DATASHEET Package Outline Drawings (NDG48P2, 6 x 6 mm 48-VFQFPN), cont. JANUARY 24, 2018 15 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS Ordering Information Part / Order Number 9FGV0841AKLF 9FGV0841AKLFT 9FGV0841AKILF 9FGV0841AKLIFT Shipping Packaging Trays Tape and Reel Trays Tape and Reel Package 48-VFQFPN 48-VFQFPN 48-VFQFPN 48-VFQFPN Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "A" is the device revision designator (will not correlate with the datasheet revision). Revision History Issue Date Description 11/12/2015 1. Updated POD diagram. 10/18/2016 Removed IDT crystal part number. Page # 14 6/26/2017 Updated front page Gendes to reflect the PCIe Gen4 updates. Updated Electrical Characteristics - Filtered Phase Jitter Parameters PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data. 1,7 1/24/2018 1. Corrected Byte 5 bit 4 to be '1' instead of '0'. 12 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved. 9FGV0841 JANUARY 24, 2018 16 (c)2018 Integrated Device Technology, Inc.