DATASHEET
9FGV0841 JANUARY 24, 2018 1 ©2018 Integrated Device Technology, Inc.
8-Output Very Low-Power PCIe Gen1-4 Clock
Generator with Zo = 100ohms 9FGV0841
Description
The 9FGV0841 is a member of IDT's SOC-friendly 1.8V very
low-power PCIe clock family. It has integrated output
terminations providing Zo = 100 for direction connection to
100 transmission lines. The device has 8 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off, and 2 selectable SMBus addresses.
Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•8 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with
Zo = 100
•1 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
support
Key Specifications
•DIF cycle-to-cycle jitter < 50ps
•DIF output-to-output skew < 50ps
•DIF phase jitter is PCIe Gen1–4 compliant
•REF phase jitter is < 1.5ps RMS
Features
•Direct connection to 100Ω transmission lines; saves 32
resistors compared to standard PCIe devices
•62mW typical power consumption; reduced thermal
concerns
•Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
•OE# pins; support DIF power management
•LP-HCSL differential clock outputs; reduced power and
board space
•Programmable slew rate for each output; allows tuning for
various line lengths
•Programmable output amplitude; allows tuning for various
application environments
•DIF outputs blocked until PLL is locked; clean system
start-up
•Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
•External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
•Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
•3.3V tolerant SMBus interface works with legacy controllers
•Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
•Space saving 6 x 6 mm 48-VFQFPN; minimal board space
Block Diagram
XIN/CLKIN_25
X2
CONTROL
LOGIC
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SS Capable PLL
OSC
REF1.8
vOE(7:0)#
SCLK_3.3
vSADR
DIF0
DIF1
DIF2
DIF3
DIF4
DIF5
DIF6
DIF7
8
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 2 JANUARY 24, 2018
9FGV0841 DATASHEET
Pin Configuration
SMBus Address Selection Table
Power Management Table
Power Connections
^CKPWRGD_PD#
VDDIO
vOE7#
DIF7#
DIF7
vOE6#
DIF6#
DIF6
GND
VDDIO
VDD1.8
vOE5#
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1 36 DIF5#
GNDXTAL 2 35 DIF5
X1_25 3 34 vOE4#
X2 4 33 DIF4#
VDDXTAL1.8 5 32 DIF4
VDDREF1.8 6 31 VDDIO
vSADR/REF1.8 7 30 VDDA1.8
GNDREF 8 29 GNDA
GNDDIG 9 28 vOE3#
SCLK_3.3 10 27 DIF3#
SDATA_3.3 11 26 DIF3
VDDDIG1.8 12 25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
VDDIO
vOE0#
DIF0
DIF0#
vOE1#
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
vv
prefix indicates internal 60kOhm pull-down resisto
r
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
6 x 6 mm 48-VFQFPN, 0.4mm pitch
9FGV0841
SADR Address
0 1101000
1 1101010
+ Read/Write Bit
x
x
State of SADR on first application
of CKPWRGD_PD#
OEx # True O/ P Comp. O/ P
0XXLowLow
Hi-Z1
1 1 0 Running Running Running
1 0 1 Low Low Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
REF
CKPWRGD_PD# SMBus
OE bit DIFx
Pin Number
VDD VDDIO GND
5 2 XTAL OSC
68REF Power
12 9 Digital (dirty)
Power
20,38 13,21,31,39,
47 22,29,40 DIF outputs
30 29 PLL Analog
Description
JANUARY 24, 2018 3 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Pin Descriptions
PIN # PIN NAME TYPE DESCRIPTION
1vSS_EN_tri LATCHED
IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
2 GNDXTAL GND GND for XTAL
3 X1_25 IN Crystal input, Nominally 25.00MHz.
4 X2 OUT Crystal output.
5 VDDXTAL1.8 PWR Power supply for XTAL, nominal 1.8V
6 VDDREF1.8 PWR VDD for REF output. nominal 1.8V.
7vSADR/REF1.8 LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
8 GNDREF GND Ground pin for the REF outputs.
9 GNDDIG GND Ground pin for digital circuitry
10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
12 VDDDIG1.8 PWR 1.8V digital power (dirty power)
13 VDDIO PWR Power supply for differential outputs
14 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
15 DIF0 OUT Differential true clock output
16 DIF0# OUT Differential Complementary clock output
17 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 DIF1 OUT Differential true clock output
19 DIF1# OUT Differential Complementary clock output
20 VDD1.8 PWR Power supply, nominal 1.8V
21 VDDIO PWR Power supply for differential outputs
22 GND GND Ground pin.
23 DIF2 OUT Differential true clock output
24 DIF2# OUT Differential Complementary clock output
25 vOE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26 DIF3 OUT Differential true clock output
27 DIF3# OUT Differential Complementary clock output
28 vOE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29 GNDA GND Ground pin for the PLL core.
30 VDDA1.8 PWR 1.8V power for the PLL core.
31 VDDIO PWR Power supply for differential outputs
32 DIF4 OUT Differential true clock output
33 DIF4# OUT Differential Complementary clock output
34 vOE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
35 DIF5 OUT Differential true clock output
36 DIF5# OUT Differential Complementary clock output
37 vOE5# IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
38 VDD1.8 PWR Power supply, nominal 1.8V
39 VDDIO PWR Power supply for differential outputs
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 4 JANUARY 24, 2018
9FGV0841 DATASHEET
Pin Descriptions (cont.)
PIN # PIN NAME TYPE DESCRIPTION
40 GND GND Ground pin.
41 DIF6 OUT Differential true clock output
42 DIF6# OUT Differential Complementary clock output
43 vOE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
44 DIF7 OUT Differential true clock output
45 DIF7# OUT Differential Complementary clock output
46 vOE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
47 VDDIO PWR Power supply for differential outputs
48 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
JANUARY 24, 2018 5 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Test Loads
Alternate Terminations
Rs
Rs
Low-Power HCSL Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohm
Device
REF Output
33
REF Output Test Load
5pF
Zo = 50 ohms
Rs
Device
Rs
Zo
Driving LVDS
Cc
Cc R7a R7b
R8a R8b
3.3V
LVDS Clock
input
Driving LVDS inputs
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1 uF 0.1 uF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 6 JANUARY 24, 2018
9FGV0841 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Current Consumption
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxx Applies to all VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
IDDAOP VDDA, All outputs active @100MHz 6 9 mA
IDDOP
All VDD, except VDDA and VDDIO, All outputs
active @100MHz 12 16 mA
IDDIOOP VDDIO, All outputs active @100MHz 28 35 mA
I
DDAP
D
VDDA, DIF outputs off, REF output running 0.4 1 mA 2
IDDPD
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running 5.3 8 mA 2
I
DDIOPD
VDDIO, DIF outputs off, REF output running 0.04 0.1 mA 2
I
DDAP
D
VDDA, all outputs off 0.4 1 mA
I
DDPD All VDD, except VDDA and VDDIO, all outputs off
0.6 1 mA
IDDIOPD VDDIO, all outputs off 0.0005 0.1 mA
1 Guaranteed by design and characterization, not 100% tested in production.
2
This is the current required to have the REF output runnin
g
in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Operating Supply Current
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 50 55 % 1,2
Skew, Output to Output t
sk3
Averaging on, V
T
= 50% 4350ps1,2
Jitter, Cycle to cycle tjcyc-cyc 14 50 ps 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
JANUARY 24, 2018 7 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxx Supply voltage for core, analog and single-ended
LVCMOS outputs 1.7 1.8 1.9 V
Output Supply Voltage VDDIO Supply voltage for differential Low Power Outputs 0.9975 1.05-1.8 1.9 V
Commercial range 0 25 70 °C
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.5 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
Output High Voltage V
IH
Single-ended outputs, except SMBus. I
OH
= -2mA V
DD
-0.45 V
Output Low Voltage V
IL
Single-ended outputs, except SMBus. I
OL
= -2mA 0.45 V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
Input Frequency F
in
XTAL, or X1 input 23 25 27 MHz
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock 0.6 1.8 ms 1,2
SS Modulation Frequency fMOD
Allowable Frequency
(Triangular Modulation) 30 31.6 33 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 1 3 3 clocks 1,3
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion 20 300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
1.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 400 kHz 1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
Capacitance
3
Time from deassertion until out
p
uts are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.65xVDDSMB
Input Current
Ambient Operating
Temperature TAMB
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 8 JANUARY 24, 2018
9FGV0841 DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on fast settin
g
1.6 2.3 3.5
V/ns
1,2,3
Scope averaging on slow setting 1.3 1.9 2.9 V/ns 1,2,3
Slew rate matchin
g
ΔTrf Slew rate matchin
g
, Scope avera
g
in
g
on 7 20
%
1,2,4
Voltage High VHI GH 660 784 850 7
Voltage Low VLOW -150 -33 150 7
Max Voltage Vmax 816 1150 7
Min Volta
g
e Vmin -300 -42 7
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1634 mV 1,2,7
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 427 550 mV 1,5,7
Crossing Voltage (var) Δ-Vcross Scope averaging off 12 140 mV 1,6,7
2 Measured from differential waveform
7
At default SMBus amplitude settin
g
s.
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
Slew rate Trf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
1Guaranteed by design and characterization, not 100% tested in production.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL PARAMETER CONDITIONS MIN TYP MAX Specification
Limit UNITS NOTES
tjphPCIeG1-CC PCIe Gen 1 21 25 35 86 ps (p-p) 1, 2, 3
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
0.9 0.9 1.1 3 ps
(rms) 1, 2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
1.5 1.6 1.9 3.1 ps
(rms) 1, 2
tjphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 1 ps
(rms) 1, 2
tjphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz) 0.3 0.37 0.44 0.5 ps
(rms) 1, 2
Notes on PCIe Filtered Phase Jitter Table
1
Applies to all differential outputs,
g
uaranteed by desi
g
n and characterization.
Phase Jitter,
PLL Mode
tjphPCIeG2-CC
2
Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
JANUARY 24, 2018 9 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBO
L
CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output 40 ns 2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, 20% to 80% of VDDREF 0.6 1 1.6 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, 20% to 80% of VDDREF 0.9 1.4 2.2 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, 20% to 80% of VDDREF 1.1 1.7 2.7 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, 20% to 80% of VDDREF 1.1 1.8 2.9 V/ns 1
Duty Cycle d
t1X
V
T
= VDD/2 V 45 49.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V 0 2 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 19.1 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -129.8 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -143.6 -115 dBc 1,4
Jitter, phase tjphREF 12kHz to 5MHz 0.63 1.5 ps
(rms) 1,4
1Guaranteed by design and characterization, not 100% tested in production.
3 Default SMBus Value
4 When driven by a crystal.
5 When driven by an external oscillator via the X1 pin, X2 should be floating.
2
All Lon
g
Term Accuracy and Clock Period specifications are
g
uaranteed assumin
g
that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 10 JANUARY 24, 2018
9FGV0841 DATASHEET
General SMBus Serial Interface Information
How to Write
•Controller (host) sends a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) sends the byte count = X
•IDT clock will acknowledge
•Controller (host) starts sending Byte N through Byte
N+X-1
•IDT clock will acknowledge each byte one at a time
•Controller (host) sends a stop bit
Note: SMBus address is latched on SADR pin.
How to Read
•Controller (host) will send a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) will send a separate start bit
•Controller (host) sends the read address
•IDT clock will acknowledge
•IDT clock will send the data byte count = X
•IDT clock sends Byte N+X-1
•IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byt e 8)
•Controller (host) will need to acknowledge each byte
•Controller (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
JANUARY 24, 2018 11 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
SM Bus Ta bl e: Output Enabl e Re gi ste r 1
Byte 0 Nam e Control Function Type 0 1 De fa ul t
Bi t 7 DIF OE7 Output Enable RW Low/Low Enabled 1
Bi t 6 DIF OE6 Output Enable RW Low/Low Enabled 1
Bi t 5 DIF OE5 Output Enable RW Low/Low Enabled 1
Bi t 4 DIF OE4 Output Enable RW Low/Low Enabled 1
Bi t 3 DIF OE3 Output Enable RW Low/Low Enabled 1
Bi t 2 DIF OE2 Output Enable RW Low/Low Enabled 1
Bi t 1 DIF OE1 Output Enable RW Low/Low Enabled 1
Bi t 0 DIF OE0 Output Enable RW Low/Low Enabled 1
1. A low on these bits will override the OE# pin and force the differential output Low/Low
SM Bus Ta bl e: SS Re a dback and Control Re gi ste r
Byte 1 Nam e Control Function Type 0 1 De fa ul t
Bi t 7 SSENRB1 SS Enable Readback Bit1 RLatch
Bi t 6 SSENRB1 SS Enable Readback Bit0 RLatch
Bi t 5 SSEN_SWCNTRL Enable SW control of SS RW Values in B1[7:6]
control SS amount
Values in B1[4:3]
control SS amount. 0
Bi t 4 SSENSW1 SS Enable Software Ctl Bit1 RW10
Bi t 3 SSENSW0 SS Enable Software Ctl Bit0 RW10
Bi t 2 1
Bi t 1 AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bi t 0 AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SM Bus Ta bl e: DI F S l ew Ra te Control Re gi ste r
Byte 2 Nam e Control Function Type 0 1 De fa ul t
Bi t 7 SLEWRATESEL DIF7 Adjust Slew Rate of DIF7 RW Slow Setting Fast Setting 1
Bi t 6 SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 RW Slow Setting Fast Setting 1
Bi t 5 SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 RW Slow Setting Fast Setting 1
Bi t 4 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Slow Setting Fast Setting 1
Bi t 3 SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW Slow Setting Fast Setting 1
Bi t 2 SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW Slow Setting Fast Setting 1
Bi t 1 SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow Setting Fast Setting 1
Bi t 0 SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow Setting Fast Setting 1
SM Bus Ta bl e: Nom i nal V hi gh Ampl i tude Control / REF Control Re gi ste r
Byte 3 Nam e Control Function Type 0 1 De fa ul t
Bi t 7 RW 00 = Slowest 01 = Slow 0
Bi t 6 RW 10 = Fast 11 = Faster 1
Bi t 5 REF Power Down Function Wake-on-Lan Enable for REF RW
REF does not run in
Power Down
REF runs in Power
Down 0
Bi t 4 REF OE REF Output Enable RW Low Enabled 1
Bi t 3 1
Bi t 2 1
Bi t 1 1
Bi t 0 1
Byte 4 is Re se rve d
Reserved
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
Reserved
Controls Output Amplitude
Reserved
Reserved
Reserved
REF Slew Rate Control
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 12 JANUARY 24, 2018
9FGV0841 DATASHEET
Recommended Crystal Characteristics (3225 package)
SM Bus Ta bl e : Revision and Vendor ID Registe r
Byte 5 Name Control Functi on Type 0 1 De fa ul t
Bit 7 RID3 R0
Bit 6 RID2 R0
Bit 5 RID1 R0
Bit 4 RID0 R1
Bit 3 VID3 R0
Bit 2 VID2 R0
Bit 1 VID1 R0
Bit 0 VID0 R1
SMBus Table: De vice Type/De vice ID
Byte 6 Name Control Functi on Type 0 1 De fa ul t
Bit 7 Device Type1 R0
Bit 6 Device Type0 R0
Bit 5 Device ID5 R0
Bit 4 Device ID4 R0
Bit 3 Device ID3 R1
Bit 2 Device ID2 R0
Bit 1 Device ID1 R0
Bit 0 Device ID0 R0
SM Bus Ta bl e : Byte Count Re giste r
Byte 7 Name Control Functi on Type 0 1 De fa ul t
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 BC4 RW 0
Bit 3 BC3 RW 1
Bit 2 BC2 RW 0
Bit 1 BC1 RW 0
Bit 0 BC0 RW 0
0001 = IDTVENDOR ID
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Byte Count Programming
Reserved
A rev = 0001Revision ID
001000 binary or 08 hexDevice ID
Reserved
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
Device Type
Reserved
PARAMETER VALUE UNITS NOTES
Frequency 25 MHz 1
Resonance Mode Fundamental
-
1
Frequency Tolerance @ 25°C
±
20 PPM Max 1
Frequency Stability, ref @ 25°C Over
Operating Temperature Range ±20 PPM Max 1
Temperature Range (commercial) 0~70 °
C
1
Temperature Range (industrial) -40~85 °C2
Equivalent Series Resistance (ESR) 50
Ω
Max 1
Shunt Capacitance (C
O
)7pF Max1
Load Capacitance (C
L
)8pF Max1
Drive Level 0.3 mW Max 1
Aging per year ±5 PPM Max 1
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
JANUARY 24, 2018 13 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Thermal Characteristics
Marking Diagrams
Notes:
1. Line 2 is the truncated part number.
2. “L” denotes RoHS compliant package.
3. “I” denotes industrial temperature grade.
4. “YYWW” is the last two digits of the year and week that the part was assembled.
5. “COO” denotes country of origin.
6. “LOT” is the lot number.
PARAMETER SYMBOL CONDITIONS PKG TYP. UNITS NOTES
θ
JC
Junction to Case 33 °C/W 1
θ
Jb
Junction to Base 2.1 °C/W 1
θ
JA0
Junction to Air, still air 37 °C/W 1
θ
JA1
Junction to Air, 1 m/s air flow 30 °C/W 1
θ
JA3
Junction to Air, 3 m/s air flow 27 °C/W 1
θJA5 Junction to Air, 5 m/s air flow 26 °C/W 1
Thermal Resistance NDG48
1ePad soldered to board
ICS
GV0841AIL
YYWW
COO
LOT
ICS
FGV0841AL
YYWW
COO
LOT
8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS 14 JANUARY 24, 2018
9FGV0841 DATASHEET
Package Outline Drawings (NDG48P2, 6 x 6 mm 48-VFQFPN)
JANUARY 24, 2018 15 8-OUTPUT VERY LOW-POWER PCIE GEN1-4 CLOCK GENERATOR WITH ZO = 100OHMS
9FGV0841 DATASHEET
Package Outline Drawings (NDG48P2, 6 x 6 mm 48-VFQFPN), cont.
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating par ameters of the described products are determined in an independent state and are not guarantee d to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-
lectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
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1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
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Tech Support
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9FGV0841 JANUARY 24, 2018 16 ©2018 Integrated Device Technology, Inc.
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Orde r Num be r Shi pping P acka gi ng P acka ge Tem pe rature
9FGV0841AKLF Trays 48-VFQFPN 0 to +70° C
9FGV0841AKLFT Tape and Reel 48-VFQFPN 0 to +70° C
9FGV0841AKILF Trays 48-VFQFPN -40 to +85° C
9FGV0841AKLIFT Tape and Reel 48-VFQFPN -40 to +85° C
Issue Date Description Page #
11/12/2015 1. Updated POD diagram. 14
10/18/2016
Removed IDT crystal part number.
6/26/2017
Updated front page Gendes to reflect the PCIe Gen4 updates.
Updated Electrical Characteristics - Filtered Phase Jitter Parameters -
PCIe Common Clocked (CC) Architectures and added PCIe Gen4 Data.
1,7
1/24/2018 1. Corrected Byte 5 bit 4 to be '1' instead of '0'. 12
