IC61LV256
Integrated Circuit Solution Inc. 1
AHSR027-0A 04/19/2002
Document Title
32K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0 A Initial Draft April 19,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC61LV256
2Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• High-speed access times:
-- 8, 10, 12, 15 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
DESCRIPTION
The ICSI IC61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
600 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IC61LV256 is available in the JEDEC standard 28-pin,
300mil SOJ and the 8*13.4mm TSOP-1 package.
32K x 8 HIGH SPEED
CMOS STATIC RAM
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
256 X 1024
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
IC61LV256
Integrated Circuit Solution Inc. 3
AHSR027-0A 04/19/2002
PIN CONFIGURATION
28-Pin SOJ
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vcc Power
GND Ground
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to +4.6 V
VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias Com. –10 to +85 °C
Ind. –45 to +90
TSTG Storage Temperature –65 to +150 ° C
PDPower Dissipation 1 W
IOUT DC Output Current ±20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IC61LV256
4Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –1 1 µA
Ind. –5 5
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
OPERATING RANGE
Range Ambient Temperature Speed VCC
Commercial 0°C to +70°C 8, 10, 12 3.3V, +10%, –5%
15 3.3V ± 10%
Industrial –40°C to +85°C All 3.3V + 10%, –5%
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Sym. Parameter Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 120 — 110 — 100 — 90mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 130 — 120 — 110 — 100
ISB1TTL Standby Current VCC = Max., Com. — 2 5—25—25—25mA
(TTL Inputs) VIN = VIH or VIL Ind. — 30—30—30—30
CE
≥
VIH, f = 0
ISB2CMOS Standby VCC = Max., Com. — 2 — 2 — 2 — 2 mA
Current (CMOS Inputs) CE
≤
VCC – 0.2V, Ind. — 5 — 5 — 5 — 5
VIN
≥
VCC – 0.2V, or
VIN
≤
0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC61LV256
Integrated Circuit Solution Inc. 5
AHSR027-0A 04/19/2002
AC TEST LOADS
Figure 1. Figure 2.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 2 — 2 — 2 — 2 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 4 — 5 — 6 — 7 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output — 4 — 5 — 5 — 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — 3 — ns
tHZCE
(2)
CE to High-Z Output — 4 — 5 — 6 — 7 ns
tPU
(3)
CE to Power-Up 0 — 0 — 0 — 0 — ns
tPD
(4)
CE to Power-Down — 8 — 10 — 12 — 15 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
319 Ω
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
IC61LV256
6Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
ADDRESS
OE
CE
DOUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
IC61LV256
Integrated Circuit Solution Inc. 7
AHSR027-0A 04/19/2002
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATAIN VALID
t LZWE
t SD
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 8 — 10 — ns
tAW Address Setup Time 7 — 8 — 8 — 10 — ns
to Write End
tHA Address Hold 0 — 0 — 0 — 0 — ns
from Write End
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE
(4)
WE Pulse Width 7 — 10 — 12 — 15 — ns
tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 3.5 — 4 — 6 — 7 ns
tLZWE
(3)
WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
4. Tested with OE HIGH.
IC61LV256
8Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE NO. 2
(WE Controlled, OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(WE Controlled, OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
IC61LV256
Integrated Circuit Solution Inc. 9
AHSR027-0A 04/19/2002
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IC61LV256-8T 8*13.4mm TSOP-1
IC61LV256-8J 300mil SOJ
10 IC61LV256-10T 8*13.4mm TSOP-1
IC61LV256-10J 300mil SOJ
12 IC61LV256-12T 8*13.4mm TSOP-1
IC61LV256-12J 300mil SOJ
15 IC61LV256-15T 8*13.4mm TSOP-1
IC61LV256-15J 300mil SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
8 IC61LV256-8TI 8*13.4mm TSOP-1
IC61LV256-8JI 300mil SOJ
10 IC61LV256-10TI 8*13.4mm TSOP-1
IC61LV256-10JI 300mil SOJ
12 IC61LV256-12TI 8*13.4mm TSOP-1
IC61LV256-12JI 300mil SOJ
15 IC61LV256-15TI 8*13.4mm TSOP-1
IC61LV256-15JI 300mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
