SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219D – APRIL 1999 – REVISED MARCH 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Supports 5-V VCC Operation
D
Ioff Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G32 performs the Boolean function Y
+
A
)
BorY
+
A•B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
40°Cto85°C
SOP (SOT-23) – DBV Tape and reel SN74LVC1G32DBVR C32_
–
40°C
to
85°C
SOP (SC-70) – DCK Tape and reel SN74LVC1G32DCKR CG_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
‡The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS OUTPUT
A B Y
H X H
XHH
L L L
logic symbol§
1
A2
BY
4
§This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
≥1
logic diagram (positive logic)
1
24
A
BY
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
A
B
GND
VCC
Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219D – APRIL 1999 – REVISED MARCH 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219D – APRIL 1999 – REVISED MARCH 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Su
pp
ly voltage
Operating 1.65 5.5
V
V
CC
Supply
voltage
Data retention only 1.5
V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH
High level in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7
V
V
IH
High
-
level
input
voltage
VCC = 3 V to 3.6 V 2
V
VCC = 4.5 V to 5.5 V 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL
Low level in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7
V
V
IL
Low
-
level
input
voltage
VCC = 3 V to 3.6 V 0.8
V
VCC = 4.5 V to 5.5 V 0.3 ×VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current
VCC =3V
–16 mA
V
CC =
3
V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current
VCC =3V
16 mA
V
CC =
3
V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆vInput transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ±0.5 V 5
TAOperating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219D – APRIL 1999 – REVISED MARCH 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP†
MAX
UNIT
PARAMETER
TEST
CONDITIONS
V
CC
MIN
TYP†
MAX
UNIT
IOH = –100
m
A1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
V
IOH = –8 mA 2.3 V 1.9
V
V
OH IOH = –16 mA 3 V 2.4
V
IOH = –24 mA 3 V 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100
m
A1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
V
IOL = 8 mA 2.3 V 0.3
V
V
OL IOL = 16 mA 3 V 0.4
V
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
IIA or B inputs VI = 5.5 V or GND 0 to 5.5 V ±5
m
A
Ioff VI or VO = 5.5 V 0±10
m
A
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10
m
A
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500
m
A
CiVI = VCC or GND 3.3 V 4 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y2.8 8 1.2 5.5 1.1 4.5 1 4 ns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TEST
CONDITIONS
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz 20 20 21 22 pF
SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
SCES219D – APRIL 1999 – REVISED MARCH 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
W aveform 1
S1 at VLOAD
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH – V∆≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
11 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 2001, Texas Instruments Incorporated
