BQ3285LSS- - Texas Instruments - Datasheet.Directory

Features

➤Direct clock/calendar replace-

ment for IBM®AT-compatible

computers and other applications

➤Functionally compatible with the

DS1285

-Closely matches MC146818A

pin configuration

➤2.7–3.6V operation (bq3285L);

4.5–5.5V operation (bq3285E)

➤242 bytes of general nonvolatile

storage

➤32.768kHz output for power man-

agement

➤System wake-up capability—

alarm interrupt output active in

battery-backup mode

➤Less than 0.5µA load under bat-

tery operation

➤Selectable Intel or Motorola bus

timing

➤14 bytes for clock/calendar and

control

➤BCD or binary format for clock

and calendar data

➤Calendar in day of the week, day

of the month, months, and years,

with automatic leap-year adjust-

ment

➤Time of day in seconds,minutes,

and hours

-12- or 24-hour format

-Optional daylight saving

adjustment

➤Programmable square wave out-

put

➤Three individually maskable in-

terrupt event flags:

-Periodic rates from 122µs to

500ms

-Time-of-day alarm once per

second to once per day

-End-of-clock update cycle

➤24-pin plastic DIP, SOIC, or

SSOP (industrial SSOP only)

General Description

The CMOS bq3285E/L is a low-

power microprocessor peripheral

providing a time-of-day clock and

100-year calendar with alarm fea-

tures and battery operation. The

bq3285L supports 3V systems.

Other bq3285E/L features include

three maskable interrupt sources,

square-wave output, and 242 bytes

of general nonvolatile storage.

A 32.768kHz output is available for

sustaining power-management ac-

tivities. Wake-up capability is pro-

vided by an alarm interrupt, which

is active in battery-backup mode.

The bq3285E/L write-protects the

clock, calendar, and storage registers

during power failure. A backup

battery then maintains data and oper-

ates the clock and calendar.

The bq3285E/L is a fully compatible

real-time clock for IBM AT-compatible

computers and other applications.

The only external components are a

32.768kHz crystal and a backup bat-

tery.

Apr. 1999 D

bq3285E/L

Real-Time Clock (RTC)

AD0–AD7Multiplexed address/

data input/output

MOT Bus type select input

CS Chip select input

AS Address strobe input

DS Data strobe input

R/W Read/write input

INT Interrupt request

output

RST Reset input

SQW Square wave output

EXTRAM Extended RAM enable

RCL RAM clear input

BC 3V backup cell input

X1–X2 Crystal inputs

VCC Power supply

VSS Ground

PN3285E1.eps

24-Pin DIP or SOIC/SSOP

10 16

12 14

VCC

SQW

EXTRAM

INT

RST

VSS

R/W

MOT

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

VSS

RCL

Pin Connections Pin Names

Block Diagram

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola

or Intel architecture. This pin should be

tied to VCC for Motorola timing or to VSS for

Intel timing (see Table 1). The setting

should not be changed during system opera-

tion. MOT is internally pulled low by a

30KΩresistor.

AD0–AD7Multiplexed address/data input/

output

The bq3285E/L bus cycle consists of two

phases: the address phase and the data-

transfer phase. The address phase pre-

cedes the data-transfer phase. During the

address phase, an address placed on

AD0–AD7and EXTRAM is latched into the

bq3285E/L on the falling edge of the AS sig-

nal. During the data-transfer phase of the

bus cycle, the AD0–AD7pins serve as a bidi-

rectional data bus.

AS Address strobe input

AS serves to demultiplex the address/data

bus. The falling edge of AS latches the ad-

dress on AD0–AD7and EXTRAM. This de-

multiplexing process is independent of the

CS signal. For DIP and SOIC packages with

MOT=V

SS, the AS input is provided a signal

similar to ALE in an Intel-based system.

Apr. 1999 D

Bus

Type MOT

Level DS

Equivalent R/W

Equivalent AS

Equivalent

Motorola VCC DS, E, or

Φ2R/W AS

Intel VSS RD,

MEMR, or

I/OR

WR,

MEMW, or

I/OW ALE

Table 1. Bus Setup

bq3285E/L

DS Data strobe input

When MOT = VCC, DS controls data trans-

fer during a bq3285E/L bus cycle. During a

read cycle, the bq3285E/L drives the bus af-

ter the rising edge on DS. During a write

cycle, the falling edge on DS is used to latch

write data into the chip.

When MOT = VSS, the DS input is provided

a signal similar to RD, MEMR, or I/OR in

an Intel-based system. The falling edge on

DS is used to enable the outputs during a

read cycle.

R/W Read/write input

When MOT = VCC, the level on R/W identi-

fies the direction of data transfer. A high

level on R/W indicates a read bus cycle,

whereas a low on this pin indicates a write

bus cycle.

When MOT = VSS, R/W is provided a sig-

nal similar to WR, MEMW, or I/OW in an

Intel-based system. The rising edge on

R/W latches data into the bq3285E/L.

CS Chip select input

CS should be driven low and held stable

during the data-transfer phase of a bus cy-

cle accessing the bq3285E/L.

INT Interrupt request output

INT is an open-drain output. This allows

alarm INT to be valid in battery-backup

mode. To use this feature, INT must be con-

nected to a power supply other than VCC.

INT is asserted low when any event flag is

set and the corresponding event enable bit

is also set. INT becomes high-impedance

whenever register C is read (see the Con-

trol/Status Registers section).

SQW Square-wave output

SQW may output a programmable fre-

quency square-wave signal during normal

(VCC valid) system operation. Any one of

the 13 specific frequencies may be selected

through register A. This pin is held low

when the square-wave enable bit (SQWE)

in register B is 0 (see the Control/Status

Registers section).

A 32.768kHz output is enabled by setting

the SQWE bit in register B to 1 and the

32KE bit in register C to 1 after setting

OSC2–OSC0 in register A to 011 (binary).

EXTRAM Extended RAM enable

Enables 128 bytes of additional nonvolatile

SRAM. It is connected internally to a 30K

Ωpull-down resistor. To access the RTC

registers,EXTRAM must be low.

RCL RAM clear input

A low level on the RCL pin causes the con-

tents of each of the 242 storage bytes to be

set to FF(hex). The contents of the clock

and control registers are unaffected. This

pin should be used as a user-interface input

(pushbutton to ground) and not connected

to the output of any active component. RCL

input is only recognized when held low for

at least 125ms in the presence of VCC. Us-

ing RAM clear does not affect the battery

load. This pin is connected internally to a

30KΩpull-up resistor.

BC 3V backup cell input

BC should be connected to a 3V backup cell

for RTC operation and storage register non-

volatility in the absence of system power.

When VCC slews down past VBC (3V typical),

the integral control circuitry switches the

power source to BC. When VCC returns

above VBC, the power source is switched to

VCC.

Upon power-up, a voltage within the VBC

range must be present on the BC pin for

the oscillator to start up.

RST Reset input

The bq3285E/L is reset when RST is pulled

low. When reset, INT becomes high imped-

ance, and the bq3285E/L is not accessible.

Table 4 in the Control/Status Registers sec-

tion lists the register bits that are cleared

by a reset.

Reset may be disabled by connecting RST

to VCC. This allows the control bits to re-

tain their states through power-

down/power-up cycles.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an exter-

nal 32.768kHz quartz crystal, Daiwa DT-26

or equivalent, with 6pF load capacitance. A

trimming capacitor may be necessary for ex-

tremely precise time-base generation.

In the absence of a crystal, a 32.768kHz

waveform can be fed into the X1 input.

Apr. 1999 D

bq3285E/L

Functional Description

Address Map

The bq3285E/L provides 14 bytes of clock and con-

trol/status registers and 242 bytes of general nonvolatile

storage. Figure 1 illustrates the address map for the

bq3285E/L.

Update Period

The update period for the bq3285E/L is one second. The

bq3285E/L updates the contents of the clock and calen-

dar locations during the update cycle at the end of each

update period (see Figure 2). The alarm flag bit may

also be set during the update cycle.

The bq3285E/L copies the local register updates into the

user buffer accessed by the host processor. Whena1is

written to the update transfer inhibit bit (UTI) in regis-

ter B, the user copy of the clock and calendar bytes re-

mains unchanged, while the local copy of the same bytes

continues to be updated every second.

The update-in-progress bit (UIP) in register A is set

tBUC time before the beginning of an update cycle (see

Figure 2). This bit is cleared and the update-complete

flag (UF) is set at the end of the update cycle.

Apr. 1999 D

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

bq3285E/L

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ-

ten in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm,

and calendar:

1. Modify the contents of register B:

a. Write a 1 to the UTI bit to prevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary

format for all time, alarm, and calendar

bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and

calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes

in the selected format.

Apr. 1999 D

Address RTC Bytes

Range

Decimal Binary Binary-Coded

Decimal

0 Seconds 0–59 00H–3BH 00H–59H

1 Seconds alarm 0–59 00H–3BH 00H–59H

2 Minutes 0–59 00H–3BH 00H–59H

3 Minutes alarm 0–59 00H–3BH 00H–59H

4Hours, 12-hour format 1–12 01H–OCH AM;

81H–8CH PM 01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

5Hours alarm, 12-hour format 1–12 01H–OCH AM;

81H–8CH PM 01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H

6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H

7 Day of month 1–31 01H–1FH 01H–31H

8 Month 1–12 01H–0CH 01H–12H

9 Year 0–99 00H–63H 00H–99H

Table 2. Time, Alarm, and Calendar Formats

bq3285E/L

Square-Wave Output

The bq3285E/L divides the 32.768kHz oscillator fre-

quency to produce the 1Hz update frequency for the

clock and calendar. Thirteen taps from the frequency di-

vider are fed to a 16:1 multiplexer circuit. The output of

this mux is fed to the SQW output and periodic inter-

rupt generation circuitry. The four least-significant bits

of register A, RS0–RS3, select among the 13 taps (see

Table 3). The square-wave output is enabled by writing

a 1 to the square-wave enable bit (SQWE) in register B.

A 32.768kHz output may be selected by setting

OSC2–OSC0 in register A to 011 while SQWE=1and

32KE = 1.

Interrupts

The bq3285E/L allows three individually selected inter-

rupt events to generate an interrupt request. These

three interrupt events are:

nThe periodic interrupt, programmable to occur once

every 122µs to 500ms.

nThe alarm interrupt, programmable to occur once per

second to once per day, is active in battery-backup

mode, providing a “wake-up” feature.

nThe update-ended interrupt, which occurs at the end

of each update cycle.

Each of the three interrupt events is enabled by an indi-

vidual interrupt-enable bit in register B. When an event

occurs, its event flag bit in register C is set. If the corre-

sponding event enable bit is also set, then an interrupt

request is generated. The interrupt request flag bit

(INTF) of register C is set with every interrupt request.

Reading register C clears all flag bits, including INTF,

and makes INT high-impedance.

Two methods can be used to process bq3285E/L interrupt

events:

nEnable interrupt events and use the interrupt request

output to invoke an interrupt service routine.

nDo not enable the interrupts and use a polling routine

to periodically check the status of the flag bits.

The individual interrupt sources are described in detail

in the following sections.

Apr. 1999 D

OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 Frequency Units Period Units

0100000None None

0100001256 Hz 3.90625 ms

0100010128 Hz 7.8125 ms

0100011 8.192 kHz 122.070 µs

0100100 4.096 kHz 244.141 µs

0100101 2.048 kHz 488.281 µs

0100110 1.024 kHz 976.5625 µs

0100111512 Hz 1.95315 ms

0101000256 Hz 3.90625 ms

0101001128 Hz 7.8125 ms

010101064 Hz 15.625 ms

010101132 Hz 31.25 ms

010110016 Hz 62.5 ms

0101101 8 Hz 125 ms

0101110 4 Hz 250 ms

0101111 2 Hz 500 ms

011XXXX

32.768 kHz same as above defined

by RS3–RS0

Table 3. Square-Wave Frequency/Periodic Interrupt Rate

bq3285E/L

Periodic Interrupt

The mux output used to drive the SQW output also

drives the interrupt-generation circuitry. If the periodic

interrupt event is enabled by writinga1totheperiodic

interrupt enable bit (PIE) in register C, an interrupt re-

quest is generated once every 122µs to 500ms. The pe-

riod between interrupts is selected by the same bits in

ble 3). Setting OSC2–OSC0 in register A to 011 does not

affect the periodic interrupt timing.

Alarm Interrupt

The alarm interrupt is active in battery-backup mode,

providing a “wake-up” capability. During each update

cycle, the RTC compares the hours, minutes, and sec-

onds bytes with the three corresponding alarm bytes. If

a match of all bytes is found, the alarm interrupt event

flag bit, AF in register C, is set to 1. If the alarm event

is enabled,an interrupt request is generated.

An alarm byte may be removed from the comparison by

setting it to a “don’t care” state. An alarm byte is set to

a “don’t care” state by writinga1toeachofitstwo

most-significant bits. A “don’t care” state may be used to

select the frequency of alarm interrupt events as follows:

nIf none of the three alarm bytes is “don’t care,” the

frequency is once per day, when hours, minutes, and

seconds match.

nIf only the hour alarm byte is “don’t care,” the

frequency is once per hour, when minutes and

seconds match.

nIf only the hour and minute alarm bytes are “don’t

care,” the frequency is once per minute, when seconds

match.

nIf the hour, minute, and second alarm bytes are

“don’t care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set to

a 1 at the end of an update cycle. If the update interrupt

enable bit (UIE) of register B is 1, and the update transfer

inhibit bit (UTI) in register B is 0, then an interrupt request

is generated at the end of each update cycle.

Accessing RTC bytes

The EXTRAM pin must be low to access the RTC regis-

ters. Time and calendar bytes read during an update

cycle may be in error. Three methods to access the time

and calendar bytes without ambiguity are:

nEnable the update interrupt event to generate

interrupt requests at the end of the update cycle. The

interrupt handler has a maximum of 999ms to access

the clock bytes before the next update cycle begins (see

Figure 3).

nPoll the update-in-progress bit (UIP) in register A. If

UIP = 0, the polling routine has a minimum of tBUC

time to access the clock bytes (see Figure 3).

nUse the periodic interrupt event to generate

interrupt requests every tPI time, such that UIP = 1

always occurs between the periodic interrupts. The

interrupt handler has a minimum of tPI/2+t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285E/L and VCC is

above VPFD, the internal oscillator and frequency divider

are turned on by writing a 010 pattern to bits 4 through 6

of register A. A pattern of 011 behaves as 010 but addition-

ally transforms register C into a read/write register. This

allows the 32.768kHz output on the square wave pin to be

turned on. A pattern of 11X turns the oscillator on, but

keeps the frequency divider disabled. Any other pattern to

these bits keeps the oscillator off.

Figure 3. Update-Ended/Periodic Interrupt Relationship

Apr. 1999 D

bq3285E/L

Power-Down/Power-Up Cycle

The bq3285E and bq3285L power-up/power-down cycles are

different. The bq3285L continuously monitors VCC for out-of-

tolerance. During a power failure, when VCC falls below VPFD

(2.53V typical), the bq3285L write-protects the clock and stor-

age registers. The power source is switched to BC when VCC is

less than VPFD and BC is greater than VPFD, or when VCC is

less than VBC and VBC is less than VPFD. RTC operation and

storage data are sustained by a valid backup energy source.

When VCC is above VPFD, the power source is VCC. Write-

protection continues for tCSR time after VCC rises above VPFD.

The bq3285E continuously monitors VCC for out-of-tolerance.

During a power failure, when VCC falls below VPFD (4.17V

typical), the bq3285E write-protects the clock and storage

registers. When VCC is below VBC (3V typical), the power

source is switched to BC. RTC operation and storage data

are sustained by a valid backup energy source. When VCC is

above VBC, the power source is VCC. Write-protection contin-

ues for tCSR time after VCC rises above VPFD.

Control/Status Registers

The four control/status registers of the bq3285E/L are

accessible regardless of the status of the update cycle

(see Table 4).

nThe frequency of the square-wave and the periodic

event rate.

nOscillator operation.

nStatus of the update cycle.

RS0–RS3 - Frequency Select

These bits select one of the 13 frequencies for the SQW out-

put and the periodic interrupt rate,as shown in Table 3.

OS0–OS2 - Oscillator Control

These three bits control the state of the oscillator and

divider stages. A pattern of 010 enables RTC operation

by turning on the oscillator and enabling the frequency

divider. A pattern of 011 behaves as 010 but additionally

transforms register C into a read/write register. This al-

lows the 32.768kHz output on the square wave pin to be

turned on. A pattern of 11X turns the oscillator on, but

keeps the frequency divider disabled. When 010 is writ-

ten,the RTC begins its first update after 500ms.

UIP - Update Cycle Status

This read-only bit is set prior to the update cycle. When

UIP equals 1, an RTC update cycle may be in progress.

UIP is cleared at the end of each update cycle. This bit

is also cleared when the update transfer inhibit (UTI)

bit in register B is 1.

76543210

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

76543210

----RS3RS2RS1RS0

76543210

-OS2OS1OS0----

76543210

UIP-------

Reg. Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB) 6 5 4 3 2 1 0 (LSB)

A 0A Yes Yes1UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na

B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 SQWE 0 DF na HF na DSE na

C 0C Yes No2INTF 0 PF 0 AF 0 UF 0 - 0 32KE na - 0 - 0

D0DYesNoVRTna-0-0-0 - 0-0-0-0

Notes: na = not affected.

1. Except bit 7.

2. Read/write only when OSC2–OSC0 in register A is 011 (binary).

Table 4. Control/Status Registers

Apr. 1999 D

bq3285E/L

nUpdate cycle transfer operation

nSquare-wave output

nInterrupt events

nDaylight saving adjustment

nClock and calendar data formats

All bits of register B are read/write.

DSE - Daylight Saving Enable

This bit enables daylight-saving time adjustments when

written to 1:

nOn the last Sunday in October, the first time the

bq3285E/L increments past 1:59:59 AM, the time

falls back to 1:00:00 AM.

nOn the first Sunday in April, the time springs

forward from 2:00:00 AM to 3:00:00 AM.

HF - Hour Format

This bit selects the time-of-day and alarm hour format:

1 = 24-hour format

0 = 12-hour format

DF - Data Format

This bit selects the numeric format in which the time,

alarm,and calendar bytes are represented:

1 = Binary

0 = BCD

SQWE - Square-Wave Enable

This bit enables the square-wave output:

1 = Enabled

0 = Disabled and held low

UIE - Update Cycle Interrupt Enable

This bit enables an interrupt request due to an update

ended interrupt event:

1 = Enabled

0 = Disabled

The UIE bit is automatically cleared when the UTI bit

equals 1.

AIE - Alarm Interrupt Enable

This bit enables an interrupt request due to an alarm

interrupt event:

1 = Enabled

0 = Disabled

PIE - Periodic Interrupt Enable

This bit enables an interrupt request due to a periodic

interrupt event:

1 = Enabled

0 = Disabled

Apr. 1999 D

7654 3 210

---- - --DSE

7654 3 210

---- - -HF-

7654 3 210

---- -DF--

7654 3 210

----SQWE - - -

7654 3 210

---UIE- ---

7654 3 210

UTI PIE AIE UIE SQWE DF HF DSE

7654 3 210

--AIE- - ---

7654 3 210

-PIE-- - ---

bq3285E/L

UTI - Update Transfer Inhibit

This bit inhibits the transfer of RTC bytes to the user

buffer:

1 = Inhibits transfer and clears UIE

0 = Allows transfer

Bits 0,1, 3 - Unused Bits

These bits are always set to 0.

32KE - 32kHz Enable Output

This bit may be set to a 1 only when the OSC2–OSC0

bits in register A are set to 011. Setting OSC2–OSC0 to

anything other than 011 clears this bit. If SQWE in reg-

ister B and 32KE are set, a 32.768kHz waveform is out-

put on the square wave pin.

UF - Update Event Flag

This bit is set toa1attheendoftheupdate cycle.

Reading register C clears this bit.

AF - Alarm Event Flag

This bit is set to a 1 when an alarm event occurs. Read-

ing register C clears this bit.

PF - Periodic Event Flag

This bit is set to a 1 every tPI time, where tPI is the time

period selected by the settings of RS0–RS3 in register A.

Reading register C clears this bit.

INTF - Interrupt Request Flag

This flag is set to a 1 when any of the following is true:

AIE = 1 and AF = 1

PIE = 1 and PF = 1

UIE = 1 and UF = 1

Reading register C clears this bit.

Bits 0–6 - Unused Bits

These bits are always set to 0.

VRT - Valid RAM and Time

1 = Valid backup energy source

0 = Backup energy source is depleted

When the backup energy source is depleted (VRT = 0),

data integrity of the RTC and storage registers is not

guaranteed.

Apr. 1999 D

7654 3 210

INTF PF AF UF 0 32KE 0 0

7654 3 210

----0-00

7654 3 210

---UF- ---

7654 3 210

--AF- - ---

7654 3 210

-PF- - - - - -

7654 3 210

INTF - - - - - - -

7654 3 210

VRT000 0 000

7654 3 210

-000 0 000

7654 3 210

UTI--- - ---

7654 3 210

VRT--- - ---

7654 3 210

---- -32KE - -

bq3285E/L

Apr. 1999 D

Absolute Maximum Ratings—bq3285E

Symbol Parameter Value Unit Conditions

VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V

VTDC voltage applied on any pin excluding VCC

relative to VSS -0.3 to 7.0 V VT≤VCC + 0.3

TOPR Operating temperature 0 to +70 °C Commercial

-40 to +85 °C Industrial

TSTG Storage temperature -55 to +125 °C

TBIAS Temperature under bias -40 to +85 °C

TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Absolute Maximum Ratings—bq3285L

Symbol Parameter Value Unit Conditions

VCC DC voltage applied on VCC relative to VSS -0.3 to 6.0 V

VTDC voltage applied on any pin excluding VCC

relative to VSS -0.3 to 6.0 V VT≤VCC + 0.3

TOPR Operating temperature 0 to +70 °C Commercial

TSTG Storage temperature -55 to +125 °C

TBIAS Temperature under bias -40 to +85 °C

TSOLDER Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

bq3285E/L

Apr. 1999 D

Recommended DC Operating Conditions—bq3285E (TA= TOPR)

Symbol Parameter Minimum Typical Maximum Unit

VCC Supply voltage 4.5 5.0 5.5 V

VSS Supply voltage 0 0 0 V

VIL Input low voltage -0.3 - 0.8 V

VIH Input high voltage 2.2 - VCC + 0.3 V

VBC Backup cell voltage 2.5 - 4.0 V

Note: Typical values indicate operation at TA= 25°C.

Recommended DC Operating Conditions—bq3285L (TA= TOPR)

Symbol Parameter Minimum Typical Maximum Unit

VCC Supply voltage 2.7 3.15 3.6 V

VSS Supply voltage 0 0 0 V

VIL Input low voltage -0.3 - 0.6 V

VIH Input high voltage 2.2 - VCC + 0.3 V

VBC Backup cell voltage 2.4 - 4.0 V

Note: Typical values indicate operation at TA= 25°C.

Crystal Specifications—bq3285E/L (DT-26 or Equivalent)

Symbol Parameter Minimum Typical Maximum Unit

fOOscillation frequency - 32.768 - kHz

CLLoad capacitance - 6 - pF

TPTemperature turnover point 20 25 30 °C

k Parabolic curvature constant - - -0.042 ppm/°C

Q Quality factor 40,000 70,000 -

R1Series resistance - - 45 KΩ

C0Shunt capacitance - 1.1 1.8 pF

C0/C1Capacitance ratio - 430 600

DLDrive level - - 1 µW

∆f/fOAging (first year at 25°C) - 1 - ppm

bq3285E/L

Apr. 1999 D

DC Electrical Characteristics—bq3285E (TA= TOPR,V

CC = 5V ±10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILI Input leakage current - - ±1µAV

IN = VSS to VCC

ILO Output leakage current - - ±1µAAD0–AD7, INT, and SQW

in high impedance,

VOUT = VSS to VCC

VOH Output high voltage 2.4 - - V IOH = -2.0 mA

VOL Output low voltage - - 0.4 V IOL = 4.0 mA

ICC Operating supply current - 7 15 mA Min. cycle, duty = 100%,

IOH = 0mA, IOL = 0mA

ICCSB Standby supply current - 300 - µAVIN = VSS or VCC,

CS ≥VCC - 0.2

VSO Supply switch-over voltage - VBC -V

CCB Battery operation current - 0.3 0.5 µAV

BC = 3V, TA= 25°C

VPFD Power-fail-detect voltage 4.0 4.17 4.35 V

IRCL Input current when RCL = VSS. - - 185 µA Internal 30K pull-up

IMOTH Input current when MOT = VCC - - -185 µA Internal 30K pull-down

Input current when MOT = VSS --0

A Internal 30K pull-down

IXTRAM

Input current when EXTRAM =

VCC - - -185 µAInternal 30K pull-down

Input current when EXTRAM =

VSS --0

Internal 30K pull-down

Note: Typical values indicate operation at TA= 25°C, VCC = 5V or VBC = 3V.

bq3285E/L

Apr. 1999 D

DC Electrical Characteristics—bq3285L (TA= TOPR,V

CC = 3.15V ±0.45V)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

ILI Input leakage current - - ±1µAV

IN = VSS to VCC

ILO Output leakage current - - ±1µAAD0–AD7and INT in high

impedance,

VOUT = VSS to VCC

VOH Output high voltage 2.2 - - V IOH = -1.0 mA

VOL Output low voltage - - 0.4 V IOL = 2.0 mA

ICC Operating supply current - 5 9 mA Min. cycle, duty = 100%, IOH

= 0mA, IOL = 0mA

ICCSB Standby supply current - 100 - µAVIN = VSS or VCC,

CS ≥VCC - 0.2

VSO Supply switch-over voltage -V

PFD -VV

BC > VPFD

-V

BC -VV

BC < VPFD

ICCB Battery operation current - 0.3 0.5 µAVBC = 3V, TA= 25°C,

VCC < VBC

VPFD Power-fail-detect voltage 2.4 2.53 2.65 V

IRCL Input current when RCL = VSS. - - 120 µA Internal 30K pull-up

IMOTH Input current when MOT = VCC - - -120 µA Internal 30K pull-down

Input current when MOT = VSS --0

A Internal 30K pull-down

IXTRAM

Input current when EXTRAM =

VCC - - -120 µAInternal 30K pull-down

Input current when EXTRAM =

VSS --0

Internal 30K pull-down

Note: Typical values indicate operation at TA= 25°C, VCC = 3V.

bq3285E/L

Apr. 1999 D

AC Test Conditions—bq3285E

Parameter Test Conditions

Input pulse levels 0 to 3.0 V

Input rise and fall times 5 ns

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 4 and 5

Figure 4. Output Load A—bq3285E Figure 5. Output Load B—bq3285E

Capacitance—bq3285E/L (TA= 25°C, F = 1MHz, VCC = 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

CI/O Input/output capacitance - - 7 pF VOUT = 0V

CIN Input capacitance - - 5 pF VIN = 0V

Note: This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.

bq3285E/L

Apr. 1999 D

AC Test Conditions—bq3285L

Parameter Test Conditions

Input pulse levels 0 to 2.3 V

Input rise and fall times 5 ns

Input and output timing reference levels 1.2 V (unless otherwise specified)

Output load (including scope and jig) See Figures 6 and 7

Figure 6. Output Load A—bq3285L Figure 7. Output Load B—bq3285L

bq3285E/L

Apr. 1999 D

Read/Write Timing—bq3285E (TA= TOPR,V

CC = 5V ±10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

tCYC Cycle time 160 - - ns

tDSL DS low or RD/WR high time 80 - - ns

tDSH DS high or RD/WR low time 55 - - ns

tRWH R/W hold time 0 - - ns

tRWS R/W setup time 10 - - ns

tCS Chip select setup time 5 - - ns

tCH Chip select hold time 0 - - ns

tDHR Read data hold time 0 - 25 ns

tDHW Write data hold time 0 - - ns

tAS Address setup time 20 - - ns

tAH Address hold time 5 - - ns

tDAS Delay time, DS to AS rise 10 - - ns

tASW Pulse width, AS high 30 - - ns

tASD Delay time, AS to DS rise (RD/WR

fall) 35 - - ns

tOD Output data delay time from DS rise

(RD fall) - - 50 ns

tDW Write data setup time 30 - - ns

tBUC Delay time before update cycle - 244 - µs

tPI Periodic interrupt time interval ----See Table 3

tUC Time of update cycle - 1 - µs

bq3285E/L

Apr. 1999 D

Read/Write Timing—bq3285L (TA= TOPR,V

CC = 3.15V ±0.45V)

Symbol Parameter Minimum Typical Maximum Unit Notes

tCYC Cycle time 270 - - ns

tDSL DS low or RD/WR high time 135 - - ns

tDSH DS high or RD/WR low time 90 - - ns

tRWH R/W hold time 0 - - ns

tRWS R/W setup time 15 - - ns

tCS Chip select setup time 8 - - ns

tCH Chip select hold time 0 - - ns

tDHR Read data hold time 0 - 40 ns

tDHW Write data hold time 0 - - ns

tAS Address setup time 30 - - ns

tAH Address hold time 15 - - ns

tDAS Delay time, DS to AS rise 15 - - ns

tASW Pulse width, AS high 50 - - ns

tASD Delay time, AS to DS rise (RD/WR

fall) 55 - - ns

tOD Output data delay time from DS rise

(RD fall) - - 100 ns

tDW Write data setup time 50 - - ns

tBUC Delay time before update cycle - 244 - µs

tPI Periodic interrupt time interval ----See Table 3

tUC Time of update cycle - 1 - µs

bq3285E/L

Apr. 1999 D

Motorola Bus Read/Write Timing—bq3285E/L

bq3285E/L

Apr. 1999 D

Intel Bus Write Timing—bq3285E/L

Intel Bus Read Timing—bq3285E/L

bq3285E/L

Apr. 1999 D

Power-Down/Power-Up Timing—bq3285E (TA= TOPR)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tFVCC slew from 4.5V to 0V 300 - - µs

tRVCC slew from 0V to 4.5V 100 - - µs

tCSR CS at VIH after power-up 20 - 200 ms Internal write-protection

period after VCC passes VPFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing—bq3285E

bq3285E/L

Apr. 1999 D

Power-Down/Power-Up Timing—bq3285L

Power-Down/Power-Up Timing—bq3285L (TA= TOPR)

Symbol Parameter Minimum Typical Maximum Unit Conditions

tFVCC slew from 2.7V to 0V 300 - - µs

tRVCC slew from 0V to 2.7V 100 - - µs

tCSR CS at VIH after power-up 20 - 200 ms Internal write-protection

period after VCC passes VPFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

bq3285E/L

Apr. 1999 D

Interrupt Delay Timing—bq3285E/L

Interrupt Delay Timing—bq3285E/L (TA= TOPR)

Symbol Parameter Minimum Typical Maximum Unit

tRSW Reset pulse width 5 - - µs

tIRR INT release from RST --2

IRD INT release from DS - - 2 µs

bq3285E/L

Apr. 1999

bq3285E/L

24-Pin SOIC (S)

.004

24-Pin S (0.300" SOIC)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.095 0.105 2.41 2.67

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51

C 0.008 0.013 0.20 0.33

D 0.600 0.615 15.24 15.62

E 0.290 0.305 7.37 7.75

e 0.045 0.055 1.14 1.40

H 0.395 0.415 10.03 10.54

L 0.020 0.040 0.51 1.02

24-Pin DIP (P)

24-Pin DIP (0.600" DIP)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.160 0.190 4.06 4.83

A1 0.015 0.040 0.38 1.02

B 0.015 0.022 0.38 0.56

B1 0.045 0.065 1.14 1.65

C 0.008 0.013 0.20 0.33

D 1.240 1.280 31.50 32.51

E 0.600 0.625 15.24 15.88

E1 0.530 0.570 13.46 14.48

e 0.600 0.670 15.24 17.02

G 0.090 0.110 2.29 2.79

L 0.115 0.150 2.92 3.81

S 0.070 0.090 1.78 2.29

Apr. 1999 D

bq3285E/L

24-Pin SSOP (SS)

24-Pin SS (0.150" SSOP)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.061 0.068 1.55 1.73

A1 0.004 0.010 0.10 0.25

B 0.008 0.012 0.20 0.30

C 0.007 0.010 0.18 0.25

D 0.337 0.344 8.56 8.74

E 0.150 0.157 3.81 3.99

e .025 BSC 0.64 BSC

H 0.230 0.244 5.84 6.20

L 0.016 0.035 0.41 0.89

bq3285E/L

Apr. 1999 D

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 8 Register C, bit 2 Was 0; is na (not affected)

1 18 Output data delay time tOD Was 80 ns max; is 100 ns max

2 1, 24, 26 Package option change Last time buy for some package options.

3 1, 24, 26 Package option change Removed PLCC and added industrial SSOP pack-

age options.

Note: Change 1 = Jan. 1995 B “Final” changes from Dec. 1993 A “Preliminary.”

Change 2 = Jan. 1999 C changes from Jan. 1995 B

Change 3 = Apr. 1999 D changes from Jan. 1999 C.

Apr. 1999 D

bq3285E/L

Ordering Information

bq3285E/L -

Package Option:

P = 24-pin plastic DIP (0.600)

S = 24-pin SOIC (0.300)

Q = 28-pin PLCC—Last time buy

SS= 24-pin SSOP (0.150)

Device:

bq3285E Real-Time Clock with 242

bytes of general storage

bq3285L Real-Time Clock with 242

bytes of general storage

(3V operation)

Temperature:

blank = Commercial (0 to +70°C)

N = Industrial* (-40 to 85°C)

*bq3285E SSOP package only

bq3285L only available in 24-pin SSOP (0.150).

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