www.infineon.com
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to oer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon oers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
FM1808B
256-Kbit (32 K × 8) Bytewide F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-86209 Rev. *F Revised June 10, 2019
FM1808B, 256-Kbit (32 K × 8) Bytewide F-RAM Memory
Features
■256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32 K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (see the Data Retention and
Endurance table)
❐NoDelay™ writes
❐Advanced high-reliability ferroelectric process
■SRAM and EEPROM compatible
❐Industry-standard 32 K × 8 SRAM and EEPROM pinout
❐70-ns access time, 130-ns cycle time
■Superior to battery-backed SRAM modules
❐No battery concerns
❐Monolithic reliability
❐True surface mount solution, no rework steps
❐Superior for moisture, shock, and vibration
❐Resistant to negative voltage undershoots
■Low power consumption
❐Active current 15 mA (max)
❐Standby current 25 A (typ)
■Voltage operation: VDD = 4.5 V to 5.5 V
■Industrial temperature: –40 C to +85 C
■28-pin small outline integrated circuit (SOIC) package
■Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM1808B is a 32 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM1808B operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM1808B ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial temper-
ature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
Address Latch and Decoder
CE
Control
Logic
WE
A
I/O Latch & Bus Driver
OE
DQ
32 K x 8
F-RAM Array
14-0
7-0
A14-0
Document Number: 001-86209 Rev. *F Page 2 of 17
FM1808B
Contents
Pinout ................................................................................3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Architecture ................................................... 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Pre-charge Operation .................................................. 4
Endurance ......................................................................... 5
F-RAM Design Considerations ........................................ 5
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
SRAM Write Cycle ....................................................... 9
Power Cycle Timing ....................................................... 12
Functional Truth Table ................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 001-86209 Rev. *F Page 3 of 17
FM1808B
Pinout
Figure 1. 28-pin SOIC Pinout
Pin Definitions
Pin Name I/O Type Description
A14–A0Input Address inputs: The 15 address lines select one of 32,768 bytes in the F-RAM array.
DQ7–DQ0Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. Asserting WE LOW causes the FM1808B to
write the contents of the data bus to the address location latched by the falling edge of CE.
CE Input Chip Enable: The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
OE Input Output Enable: When OE is LOW, the FM1808B drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
DQ4
DQ5
DQ6
DQ7
OE
A8
A13
WE
A9
A10
A11
VDD
CE
DQ3
A14
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A12
A7
A6
A5
A428-pin SOIC
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
16
15
19
18
17
21
20
24
23
22
26
25
28
27
Document Number: 001-86209 Rev. *F Page 4 of 17
FM1808B
Device Operation
The FM1808B is a bytewide F-RAM memory logically organized
as 32,768 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM1808B requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 12 for a complete description of
read and write modes.
Memory Architecture
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The complete 15-bit address
specifies each of the 32,768 bytes uniquely. The F-RAM array is
organized as 4092 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance section.
The cycle time is the same for read and write memory opera-
tions. This simplifies memory controller logic and timing circuits.
Likewise the access time is the same for read and write memory
operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that VDD remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between VDD and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing” on page 12.
Memory Operation
The FM1808B is designed to operate in a manner similar to other
bytewide memory products. For users familiar with BBSRAM, the
performance is comparable but the bytewide interface operates
in a slightly different manner as described below. For users
familiar with EEPROM, the differences result from the higher
write performance of F-RAM technology including NoDelay
writes and much higher write endurance.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
The FM1808B will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM1808B, writes occur in the same interval as reads. The
FM1808B supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM1808B will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the page 11.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
Document Number: 001-86209 Rev. *F Page 5 of 17
FM1808B
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM1808B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, F-RAM
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 1014 cycles will allow
150,000 accesses per second to the same row for over 20 years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
falling edge of CE, users cannot ground it as they might with
SRAM.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in Figure 2. Also shown is a common SRAM signal
relationship that will not work for the FM1808B.
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
Figure 2. Chip Enable and Memory Address Relationships
A second design consideration relates to the level of VDD during
operation. Battery-backed SRAMs are forced to monitor VDD in
order to switch to battery backup. They typically block user
access below a certain VDD level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
F-RAM memories do not need this system overhead. The
memory will not block access at any VDD level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when VDD is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track VDD during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below VDD min. (4.5 V).
Valid Strobing of CE
F-RAM
Signaling
CE
Address A1 A2
Data D1 D2
Invalid Strobing of CE
SRAM
Signaling
CE
Address A1 A2
Data D1 D2
Document Number: 001-86209 Rev. *F Page 6 of 17
FM1808B
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 3. Use of Pull-up Resistor on CE
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If the chip is enabled
and WE is LOW during power cycles, data will be corrupted.
Figure 4 shows a pull-up resistor on WE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the WE pin tracks VDD to a high
enough value, so that the current drawn when WE is LOW is not
an issue.
Figure 4. Use of Pull-up Resistor on WE
MCU / MPU
CE
WE
OE
A14-0
DQ 7-0
FM1808B
VDD
MCU / MPU
CE
WE
OE
A14-0
DQ 7-0
FM1808B
VDD
Document Number: 001-86209 Rev. *F Page 7 of 17
FM1808B
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [1] Max Unit
VDD Power supply voltage 4.5 5.0 5.5 V
IDD VDD supply current
VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
––15mA
ISB1 Standby current (TTL)
VDD = 5.5 V, CE at VIH,
All other pins are static and at
TTL levels (0.8 V or 2.0 V)
TA 25 C––1.8mA
TA < 25 C––2.0mA
ISB2 Standby current (CMOS) VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V) –2550µA
ILI Input leakage current VIN between VDD and VSS ––+1µA
ILO Output leakage current VOUT between VDD and VSS ––+1µA
VIH Input HIGH voltage – 2.0 – VDD + 0.3 V
VIL Input LOW voltage – – 0.3 – 0.8 V
VOH1 Output HIGH voltage IOH = –2.0 mA 2.4 – – V
VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V
VOL1 Output LOW voltage IOL = 4.2 mA – – 0.4 V
VOL2 Output LOW voltage IOL = 150 µA – – 0.2 V
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-86209 Rev. *F Page 8 of 17
FM1808B
AC Test Conditions
Input pulse levels ....................................................0 V to 3V
Input rise and fall times (10%–90%) ......................... < 10 ns
Input and output timing reference levels .......................... 1.5
Output load capacitance ............................................. 100 pF
Figure 5. AC Test Loads
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention
At +85 C 10 – Years
At +75 C 38 – Years
At +65 C 151 – Years
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter Description Test Conditions Max Unit
CI/O Input/Output capacitance (DQ) TA = 25 C, f = 1 MHz, VDD = VDD(Typ) 8pF
CIN Input capacitance 6pF
Thermal Resistance
Parameter Description Test Conditions 28-pin SOIC Unit
JA
Thermal resistance
(junction to ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance,
in accordance with EIA/JESD51.
58 C/W
JC
Thermal resistance
(junction to case) 26 C/W
Document Number: 001-86209 Rev. *F Page 9 of 17
FM1808B
AC Switching Characteristics
Over the Operating Range
Parameters[2]
Description Min Max Unit
Cypress
Parameter Alt Parameter
SRAM Read Cycle
tCE tACE Chip enable access time – 70 ns
tCA –Chip enable active time 70 – ns
tRC –Read cycle time 130 – ns
tPC –Pre-charge time 60 – ns
tAS tSA Address setup time 0–ns
tAH tHA Address hold time 15 – ns
tOE tDOE Output enable access time – 12 ns
tHZ[3, 5] tHZCE Chip Enable to output HI-Z – 15 ns
tOHZ[3, 5] tHZOE Output enable HIGH to output HI-Z – 15 ns
SRAM Write Cycle
tWC tWC Write cycle time 130 – ns
tCA –Chip enable active time 70 – ns
tCW tSCE Chip enable to write enable HIGH 70 – ns
tPC –Pre-charge time 60 – ns
tWP tPWE Write enable pulse width 40 – ns
tAS tSA Address setup time 0 – ns
tAH tHA Address hold time 15 – ns
tDS tSD Data input setup time 30 – ns
tDH tHD Data input hold time 0 – ns
tWZ[4, 4] tHZWE Write enable LOW to output HI-Z – 15 ns
tWX[4] –Write enable HIGH to output driven 10 –ns
tHZ[4] –Chip enable to output HI-Z –15 ns
tWS[6] –Write enable to CE LOW setup time 0 – ns
tWH[6] –Write enable to CE HIGH hold time 0 – ns
Notes
2. Test conditions assume a signal transition time of 10 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. tWZ and tHZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
6. The relationship between CE and WE determines if a CE or WE controlled write occurs. There is no timing specification associated with this relationship.
Document Number: 001-86209 Rev. *F Page 10 of 17
FM1808B
Figure 6. Read Cycle Timing
Figure 7. Write Cycle Timing 1 (CE Controlled)
tAS
tOHZ
CE
OE
DQ
tAH
tCE
tOE
tCA
tRC
tPC
tHZ
7-0
A12-0
CE
WE
tAS
tAH
tCA
tWC
tPC
OE
tWS
tDS tDH
tWH
A12-0
DQ 7-0
Document Number: 001-86209 Rev. *F Page 11 of 17
FM1808B
Figure 8. Write Cycle Timing 2 (WE Controlled)
tWS
tDH
tWH
CE
WE
tAS
tAH
tCA
tWC
tPC
OE
tDS
tWP
tWZ tWX
tC W
A12-0
DQ7-0(out)
DQ7-0(in)
Document Number: 001-86209 Rev. *F Page 12 of 17
FM1808B
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up (after VDD min. is reached) to first access time 10 –ms
tPD Last write (WE HIGH) to power down time 0 – µs
tVR[7] VDD power-up ramp rate 30 –µs/V
tVF[7] VDD power-down ramp rate 30 –µs/V
Figure 9. Power Cycle Timing
Functional Truth Table
CE WE Operation[8, 9]
H X Standby/Pre-charge
↓X Latch Address (and begin write if WE = LOW)
LHRead
L↓Write
Notes
7. Slope measured at any point on the VDD waveform.
8. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = Toggle LOW, ↑ = Toggle HIGH.
9. The OE pin controls only the DQ output buffers.
VDD tVF
VDD min
min
VDD
tVR
tPU
tPD
Access Allowed
VIL(max)
VIH (min)
Document Number: 001-86209 Rev. *F Page 13 of 17
FM1808B
Ordering Code Definitions
Ordering Information
Ordering Code Package Diagram Package Type Operating Range
FM1808B-SG 51-85026 28-pin SOIC Industrial
FM1808B-SGTR 51-85026 28-pin SOIC
All the above parts are Pb-free.
Option:
blank = Standard; TR = Tape and Reel
Package Type:
SG = 28-pin SOIC
Voltage: 4.5 V to 5.5 V
I/O Width: × 8
256-Kbit Parallel F-RAM
Cypress
18FM 08 B - SG TR
Document Number: 001-86209 Rev. *F Page 14 of 17
FM1808B
Package Diagram
Figure 10. 28-pin SOIC Package Outline, 51-85026
51-85026 *H
Document Number: 001-86209 Rev. *F Page 15 of 17
FM1808B
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
CPU Central Processing Unit
CMOS Complementary Metal Oxide Semiconductor
JEDEC Joint Electron Devices Engineering Council
JESD JEDEC Standards
EIA Electronic Industries Alliance
F-RAM Ferroelectric Random Access Memory
I/O Input/Output
MCU Microcontroller Unit
MPU Microprocessor Unit
RoHS Restriction of Hazardous Substances
R/W Read and Write
SOIC Small Outline Integrated Circuit
SRAM Static Random Access Memory
Table 2. Units of Measure
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
Mmegaohm
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-86209 Rev. *F Page 16 of 17
FM1808B
Document History Page
Document Title: FM1808B, 256-Kbit (32 K × 8) Bytewide F-RAM Memory
Document Number: 001-86209
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3912933 GVCH 02/25/2013 New spec
*A 4000965 GVCH 05/15/2013 Added Appendix A - Errata for FM1808B
*B 4045491 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*C 4274813 GVCH 03/10/2014
Converted to Cypress standard format
Changed datasheet status from “Preliminary to Final”
Changed endurance value from 1012 to 1014 cycles
Updated Maximum Ratings table
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance table
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
*D 4562106 GVCH 11/05/2014 Added related documentation hyperlink in page 1.
Updated package diagram 51-85026 to current version.
*E 4881950 ZSK / PSR 09/04/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
*F 6572627 GVCH 06/10/2019
DC Electrical Characteristics: Updated ISB1 parameter test condition and
added ISB1 value for TA < 25 C.
Updated Copyright information.
Document Number: 001-86209 Rev. *F Revised June 10, 2019 Page 17 of 17
© Cypress Semiconductor Corporation, 2013-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.s in the
United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
FM1808B
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Arm® Cortex® Microcontrollers cypress.com/arm
Automotive cypress.com/automotive
Clocks & Buffers cypress.com/clocks
Interface cypress.com/interface
Internet of Things cypress.com/iot
Memory cypress.com/memory
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless
PSoC® Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support