Ss Dense-Pac Microsystems, Inc. 1 MEG X 16 FLASH EEPROM VERSA-STACK MODULE ADVANCED INFORMATION DESCRIPTION: The DPZ1MX16V3 VERSA-STACK module is a revolutionary new memory subsystem using Dense-Pac Microsystems ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 16 Megabits of FLASH EEPROM in a single package envelope of 1.090" x 1.090* x .490. The DPZ1MX16V3 is built with two stacks of 4 SLCC packages each containing two 128K x 8 FLASH memory devices. Each SLCC is hermetically sealed making the module suitable for commercial, industrial and military applications. By using SLCCs, the Versa-Stack family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module or hybrid techniques. FEATURES: * Organization: 1Meg x 16 or 2Megx 8 Fast Access Times: 120*, 150, 170, 200, 250ns (max.) * Fully Static Operation - No clock or refresh required FUNCTIONAL BLOCK DIAGRAM * TTL Compatible Inputs and Outputs cETa CES TE cETS * Common Data Inputs and TE CENT M5 = Outputs eB crs < oe M2 5 me 3 als * Automatic Erase Function cre < CEs 13 - Reduces CPU overhead os "| Ma 5 2 oad 5 : x * 10,000 Erase/Program WES = g WT cle Cycles (min.) o Ss z E al : x 1/081 /07 s 1/08-1/015 66 - Pin PGA VERSA-STACK Ad- AIG } AQ~AIE omy Package * Available in commercial only. PIN-OUT DIAGRAM PIN NAMES TED ty Nc. 12] CED CES. [45 woo [56 CET AO-Al6 Address Inputs TEE 2] NC. 13] CET 8 TET [46 NC. |S? OES TE 3| vss t4| CEB i) TET [47 wc. [$8 CES 00 - 1/015 | Data Input/Output ary 4| TENS 15] CETZ ag [48 ETS. [59 CETS CEO - CET5 Low Chip Enables aves} ae 16 OF 8 a? fas as [oe a2 WEO - WET Write Enables AIS 6 | All 174 VPP (TOP VIEW) @ N.C. [58 a4 61 At ale 7] ANZ 18) WED @ AB 51 a5 62 42 OE Output Enable N.C. &| VOD 19] 1/07 a9 52 WT [63 1/018 Vpp Programming oe 9 | NC. 28] 1706 @ os [53 Nc. [64 1/ote Voltage (+12V) 1701 18 NC. 21} 1/05 8 1709 [54 VSS) 168 1/013 Voo Power (+5V) 1/0211 | 1/03 22] 1/04 @ 17018 155 17011 168 1/012 Vss Ground 30A070-30 1 REV. ADPZ1MX16V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION DEVICE OPERATION: The FLASH devices are electrically erasable and program mable memories that function similarly to an EPROM device, but can be erased without being removed from the system and exposed to ultraviolet light. Each 128K x 8 device can be erased individually eliminating the need to reprogram the entire module when partial code changes are required. READ: With Ver = OV to Voo (Verto), the devices are read-only memories and can be read like a standard EPROM. By selecting the device to be read (see Truth Table and Functional Block Diagram), the data prograrnmed into the device will appear on the appropriate 1/O pins. When Vpp = +12.0V (Ver), reads can be accomplished in the same manner as described above but must be preceded by writing OOH to the command register prior to reading the device. When Vpp is raised to +12.0V the contents of the command register default to OOH and remain that way until the command register is altered. STANDBY: When the appropriate CEs are raised to a logichigh level, the standby operation disables the FLASH devices reducing the power consumption substantially. The outputs are placed in a high- impedance state, independent of the OE input. If the module is deselected during programming, erasure, or autoerase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. PROGRAM: The programming and erasing functions are accessed via the command register when high voltage is applied to Vpp. The contents of the command register control the functions of the memory device (see Command Definition Table). The command register is not an addressable memory location. The register stores the address, data, and command informa- tion required to execute the command. When Vpp = Vppto the command register is reset to OOH returning the device to the read-only mode. The command register is written by enabling the device upon which that the operation is to be performed (see Functional Block Diagram). While the device is enabled bring WE to a logictow (Vit). The address is latched on the falling edge of WE and data is latched on the rising edge of WE. Programming is initiated by writing 40H (program setup command) to the command register. On the next falling edge of WE the address to be programmed will be latched, followed by the data being latched on the rising edge of WE (see AC Operating and Characteristics Table). PROGRAM VERIFY: The FLASH devices are programmed one location at a time. Each location may be programmed sequentially or at random. Following each programming operation, the data written must be verified. To initiate the program-verify mode, COH must be written to the command register of the device just programmed. The programming operation is terminated on the rising edge of . The program-verify command is then written to the command register. After the program-verify command is written to the command tegister, the memory device applies an internally generated margin voltage to the location just written. After waiting 6ys the data written can be verified by doing a read. If true data is read from the device, the location write was successful and the next location may be programmed. If the device fails to verify, the program/verify operation is repeated up to 20 times. ERASE: The erase function is a command-only operation and can only be executed while Vpp = VepHi. To setup the chip-erase, 20H must be written to the command register. The chip-erase is then executed by once again writing 20H to the command register (see AC Operating and Charac- terstics Table). To ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data = OOH) prior to starting the erase operation. With the algorithm provided, this operation should typically take 8 seconds. ERASE VERIFY: The erase operation erases all locations in the device selected in parallel. Upon completion of the erase operation, each location must be verified. This operation is initiated by writing AOH to the command register. The address to be verified must be supplied in order to be latched on the falling edge of WE. The memory device internally generates a margin voltage and applies it to the addressed location. if FFH is read from the device, it indicates the location is erased. The erase/verify command is issued prior to each location verification to latch the address of the location to be verified. This continues until FFH is not read from the device or the last address for the device being erased is read. If FFH is not read from the location being verified, an addition- al erase operation is performed. Verification then resumes from the last location verified. Once all locations in the device being erased are verified, the erase operation is complete. The verify opertation should now be terminated by writing a valid command such as program set-up to the command register. 30A070-30 REV. ADense-Pac Microsystems, Inc. DPZ1MX16V3 ADVANCED INFORMATION AUTOMATIC ERASE: An automatic erase function is also available eliminating the need to program all locations to OOH or do an erase verify. The automatic erase will program all locations to OOH and do a continuous erase/verify until all locations in the device are erased. To setup the chip-erase, 30H must be written to the command register. The chip-erase is then executed by once again writing 30H to the command register (see AC Operating Charac- teristics Table). To determine if the automatic erase cycle is complete, the most significant I/O (MSB) pin for the device being erased (/O7, 1/015) is read. If the data = OH on the MSB of the device being erased, the cycle is not complete. The erase cycle is complete when the data = 1 on the MSB of the device being erased. DESIGN CONSIDERATIONS: Ver traces should use trace widths and layout considerations comparable to that of the Vop power bus. The Vep supply traces should also be decoupled to help decrease voltage spikes. Power-up sequencing should be such that Vpp doesnt go above Vpp + 2.0V before Vop reaches a steady state voltage, while on power-down Vpp should be below Vpp + 2.0V before Voo is lowered. While the memory module has high-frequency, low-induc- tance decoupling capacitors mounted on the substrate con- nected to Vop and Vss, it is recommended that a 4.7yF to 10pF electrolytic capacitor be placed near the memory module connected across Vpp and Vss for bulk storage. Decoupling capacitors should also be placed near the module, connected across Vpp and Vss. COMMAND DEFINITION TABLE Bus First Bus Cycle Second Bus Cycle COMMAND Read Operation Address oe lo 7. | Operation Address Noe - Ws i 5 Read Memory 1 Write x 00H - . - Setup Erase / Erase 2 Write x 20H Write x 20H Erase Verify 2 Write EA AOH Read xX EVD Setup Autoerase / Autoerase 2 Write x 30H Write xX 30H Setup Program / Program 2 Write xX 40H Write PA PD Program Verify 2 Write x COH Read x PVD Reset 2 Write x FFH Write xX FFH EA = Address to Verify EVD = Data Read from Location EA PA = Address to Program PD = Data to be Programmed at Location PA PVA = Data to be Read from Location PA at Program Verify TRUTH TABLE Not Selected Disable Read Not Selected Disable Read Write COMMAND PROGRAM Cin H L L H L L L Current Active Active Active Active 30A070-30 REV. ADPZ1MX16V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION CAPACITANCE 4: Ta= F = 1.0MHz RECOMMENDED OPERATING RANGE! Symbol Characteristic Min. | Typ.| Max. | Unit Voo | Supply Voltage 4.5 | 5.0 5.5 Vv Caper Vep Programming Voltage | 11.4/12.0| 12.6 Vv Cce Vii | Input LOW Voltage 0.32 08 Vv Vin Input HIGH Voltage 2.2 Vppt1.0| V Cor Ta _| Operating Temp. O | +25} +70 | C ABSOLUTE MAXIMUM RATINGS 3 Max.| Unit 100 30 100 400 80 Vin? = OV pF Temperature 65 to +150 c U Bias -55 to +125 to +7.0 Vv DC OUTPUT CHARACT ERISTICS Symbol| Parameter Conditions | Min. | Max/ Unit O.6to+140 | V Von |HIGH Voltage |lon= -400pA| 24 | - | V OH ge | lon A 0.6 to +7.0 Vv Voit | LOW Voltage low=2.1mA - 10.45) V DC OPERATING CHARACTERISTICS: Over operating ranges sont _ TYP. Limits . Symbol Characteristics Test Conditions (*) Min. Max. Unit lin Input Leakage Current Vin = OV to Vop . -30 +30 pA four (ealae Current z or oF yee or WE = Vin 15 +15 nA lee Active CE = Vi, Vin * Vac or Vin, x8 20 30 Supply Current lout = OmA, f = OMHz x16 25 45 mA lec2 Operating CE = Vig Vin @ Vin oF View x8 40 65 Supply Current lout = OmA, f = 8MHz x16 65 115 mA lees Voo Programming Current Programming in Progress 25 35 mA lees Voo Erase Current Erasure in Progress 35 95 mA ise1 Standby Current (TTL) CE = Vin 16 mA Isu2 Full Standby Supply Current (CMOS) | CE = Voo 0.2V 320 HA lpps Vep Leakage Current Vee = Verto 320 pA Ippr Ver Read Current Vep = 12.6V 3.2 mA lep2 Vep Programming Current Veep = Veen, Programming in Progress 10 60 mA Ipps Vpp Erase Current Vep = Vepru, Erasure in Progress 70 160 mA * Typical measurements made at +25C, Cycle = min., Voo = 5.0V. 4 30A070-30 REV. ADense-Pac Microsystems, Inc. DP Z1 MX1 6V3 ADVANCED INFORMATION AC TEST CONDITIONS Figure 1. Output Load Input Pulse Levels OV to 3.0V * including Probe and Jig Capacitance. Input Pulse Rise and Fall Times 5ns Input and Output 1.5V +3 Timing Reference Levels . 1.8KQ OUTPUT LOAD Dour load} C Parameters Measured car 9900 1 100 pF | except tor ] 30 pF! tor = = AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No.| Symbol Parameter 1 20 1 50 = 70 - -200 2250 Unit Min. | Max.| Min. | Max.) Min.) Max.| Min.| Max.) Min.| Max. 1 tce Chip Enable Access Time 120 150 170 200 250|_ns 2 tacc Address Access Time 120 150 170 200 250] ns 3 tor Output Enabe Access Time 60 70 75 80 90 | ns 4 tor Output Disable to Output in HIGH-Z 5 O | 40; 0; 50} 0 | 55 60 70 | ns 5 tou Output Hold from Address Change 5 5 5 5 5 ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 9: Over operating ranges No.| Symbol Parameter 1 20 -1 50 a 70 - -200 -250 Unit Min, | Max.| Min. | Max.| Min.| Max.| Min,| Max.) Min. | Max. 6 towc Wiite Cycle Time 120 150 170 200 250 ns 7 tas Address Setup Time 0 0 0 0 0 ns 8 tay Address Hold Time 60 60 60 60 60 ns 9 tos Data Setup Time 50 50 50 50 50 ns 10 tou Data Hold Time 10 10 10 10 10 ns 11 tces Chip Enable Setup Time 0 0 0 Oo 0 ns 12 tceH Chip Enable Hold Time Oo 0 0 oO 0 ns 13 tves Vpp Setup Time & 7 100 100 100 100 100 ns 14 tvPH Vpp Hold Time & 7 100 100 100 100 100 ns 15 twee Write Enable Pulse Width 70 70 80 80 90 ns 16 | tweH Write Enable Pulse Width HIGH Time 20 20 20 20 20 ns it Enable Setup Time before 17 | toews Conard Programming 0 9 0 0 0 ns 18 | _toers Output Enable Setup Time before Verify 6 6 6 6 6 ps 19 tva Verify Access Time 120 150 170 200 250; ns 20 | toers | Output Enable Setup Time before Status Polling | 20 20 20 20 20 ns 21 tspa Status Polling Access Time 120 150 170 200 250] ns 22 tppw Standby Time before Programming 25 25 25 25 25 ps 23 ter Standby Time in Erase 9;11{ 9111; 9{ 11} 9{ 11] 9 | 11] ms 24 tarT Total Erase Time in Autoerase 0.5} 30/05] 30} 0.5] 30 | 0.5 | 30 | 0.5 | 30 S 30A070-30 5 REV. ADPZ1 MX1 6V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION READ CYCLE TRC ADDRESS ADDRESS VALIO TCE CEO -CEI5 OE WE DATA OUT OUTPUT VALID PROGRAMMING CYCLE p- SETUP, PROGRAM ~fe beag PROGRAM VERIFY ~tmm4 Vop (5.0V) TVeS fae 12.0V Vep 5.0V OOXXKAANARA ANY ADDRESS ADDRESS FREAD mS TAS TCEH om) TAH TCEH CE0 - CETS K K I _ TCEH TCES = TES = co OF Xf TCWC tom pa TPP Wy __ee TOEWS TWEH pmt- TOERS ae TWEP TWEP WE \ / \ / Y y KS a, KS T TOF TOS | TOH Tos | 1DH TDS | TOH vA Lana DATAI/O sich-2 { Comano DATA Command K osi2., 6 30A070-30 REV.ADense-Pac Microsystems, Inc. . DPZIMX16V3 ADVANCED INFORMATION ERASE CYCLE pm SETUP ERASE ERASE ERASE VERIFY o Voo (5.0V) VPS sisi 12.0V Vep 5.0V TAS | TAH SORTS UTR RR RRR ADDRESS 2 ROR \ / CEO - CETS K \ / TCeS ee] ee TCES Lae TCES = a, XS TewC TET -m pawt-TOER S tom TOEWS TWEH TWEP TWEE TWEP \ y NY yo \ y WE NS ae, Na, TOS | TOH 1S | TDH 70S | 10H vA Oe DATA 1/0 HicH-z{ comuane coumano Command ott, 7 WAVEFORM KEY UM. _M BERR Data Valid Transition from HIGH to LOW Transition from LOW to HIGH 30A070-30 REV.A Data Undefined or Dont CareDPZ1 MXt1 6V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION AUTOMATIC ERASE CYCLE bnat-~- SETUP AUTO ERASE Pi AUTO ERASE & STATUS POLLING r| Vpo (5.0V) TVPH TVPS 12.0V Vep 5.0V ADDRESS | TCEH ~ TCEH CEO - CETS f TCES 4 TCES bee J TCES [ne OE 4 f TCWC pam-TOEPS om TOEWS TWEH TAET TWEP TWEP \ fo N / WE VS LS TOF _ TDS | TOH TDS | TDH TSPA lars 1/07, 1/015 HIGH-Z COMMAND Command f Reem paa STATUS POLLING ~f 1/00 - 1/06, __ . COMMAND COMMAND Wos- ora 1? " IN NOTES: 1. All voltages are with respect to Vss. 2. -2.0V min. for pulse width less than 20ns (Vit min. = -0.6V at DC level). 3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. This parameter is guaranteed and not 100% tested. 5. Transition is measured at the point of 500mV from steady state voltage. 6. Vcc must be applied before Vpp and removed after Ver. 7. Ver must not exceed 14V, including overshoot. 8. The total erase times shown are for one (1) 128Kx8 device, to erase the entire module would be 8x (x16 Mode) the times shown. 8 304070-30 REV.ADense-Pac Microsystems, Inc. DP Z1 MXt1 6V3 ADVANCED INFORMATION WRITE ALGORITHM START PROGRAMMING WRITE SETUP PROGRAM COMMAND i WRITE VALID DATA TIME OUT 25 us WRITE PROGRAM VERIFY COMMAND READ DATA FROM DEVICE NEXT ADDRESS YES SET VPP = LAST @Vv TO VDD +2.8V ADDRESS 2 PROGRAM YES ERROR WRITE READ COMMAND ! SET VPP = @V TO VOD +2.8V PROGRAMMING COMPLETED 30A070-30 9 REV.ADPZ1MX16V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION ERASE ALGORITHM START ERASURE PROGRAM ALL 8YTES TO 88H ADDRESS = ADDRESS MIN. COUNT = @ WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND TME OUT '@ms INCREMENT ADDRESS WRITE ERASE VERIFY COMMAND TME OUT 6 us READ DATA FROM DEVICE NO YES YES SET VPP = v TO VOD +2.2Vv YES WRITE READ COMMAND SET VPP = @V TO VOD +2.0V ERASURE COMPLETED 10 30A070-30 REV.ADense-Pac Microsystems, Inc. . DPZ1MX16V3 ADVANCED INFORMATION AUTOMATIC ERASE START AUTOMATIC ERASURE VPP = 12.8V WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND STATUS POLLING ON 1/07, 1/015 38 1707, 1/015 SECONDS LATER ~ 2 WRITE READ COMMAND SET vPP = QV TO VDD +2.8Vv ERASURE COMPLE TED 30A070-30 11 REV. ADPZ1 MX1 6V3 Dense-Pac Microsystems, Inc. ADVANCED INFORMATION ORDERING INFORMATION DP ZIMXi6 V3 ~XX xX PREFIx DEVICE TYPE PACKAGE SPPED GRADE C COMMERCIAL BC to +70C t INDUSTRIAL - 40C to +B5C Me MILITARY -55C to +125C Bs MIL-PROCESSED -55C to +125C DENSE-FAT 12. 128ns (COMMERCIAL ONLY) 15 15@ns 17 1780s 20 288ns 25 258ns ~~~] 66 PIN PIN GRID ARRAY (PGA)/(3-D) VERSA-STACK { 1 MEG x 16 FLASH EEPROM * Commercial available now, contact DensePac Sales for availability of *, M" and "B Grade devices. MECHANICAL DRAWING PEPE ee ree BEE 1.898 MAX. SQ. -492 MAX, .848 MAX t~ 218+.203 J Lreos.c10 on MAX. .18@ TYP. 1 BIO+t.O1B L100 TYP. 1.888 Dense-Pac Microsystems, Inc. 7321 Lincoln Way @ Garden Grove, California 92641-1428 (714) 898-0007 @ (800) 642-4477 (Outside CA) @ FAX: (714) 897-1772 12 30A070-30 REV.A