Revised February 1999 MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positivegoing transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Typical propagation delay: 20 ns Wide power supply range: 2-6V Low quiescent current: 40 A maximum (74HC Series) Low input current: 1 A maximum Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HC74AM MM74HC74ASJ MM74HC74AMTC MM74HC74AN Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs PR CLR CLK D Q L H X X H Q L H L X X L H L L X X H (Note 1) H (Note 1) H H H H L H H L L H H H L X Q0 Q0 Note: Q0 = the level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level. (c) 1999 Fairchild Semiconductor Corporation DS005106.prf www.fairchildsemi.com MM74HC74A Dual D-Type Flip-Flop with Preset and Clear September 1983 MM74HC74A Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions -0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) -1.5 to VCC +1.5V DC Output Voltage (VOUT) -0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) 20 mA DC Output Current, per pin (IOUT) 25 mA Min Max Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V -40 +85 C (VIN, OUT) Operating Temperature Range (TA) DC VCC or GND Current, per pin Input Rise or Fall Times 50 mA (ICC) Storage Temperature Range (TSTG) -65C to +150C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Power Dissipation (PD) (Note 4) 600 mW S.O. Package only 500 mW Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (TL) (Soldering 10 seconds) VIH VIL VOH Parameter Note 4: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C. 260C DC Electrical Characteristics Symbol Units Conditions (Note 5) TA = 25C VCC Typ TA = -40 to 85C TA = -55 to 125C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| 20 A 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| 4.0 mA 4.5V 4.3 3.98 3.84 3.7 V |IOUT| 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| 20 A 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V 0.1 1.0 1.0 A Maximum Quiescent VI N =VCC or GND 6.0V 4.0 40 80 A Supply Current IOUT = 0 A VIN = VIH or VIL IIN Maximum Input Current ICC Note 5: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC74A Absolute Maximum Ratings(Note 2) (Note 3) MM74HC74A AC Electrical Characteristics VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Conditions Guaranteed Typ Limit Units fMAX Maximum Operating Frequency 72 30 MHz tPHL, tPLH Maximum Propagation 10 30 ns 17 40 ns 6 5 ns 10 20 ns 0 0 ns 8 16 ns Delay Clock to Q or Q tPHL, tPLH Maximum Propagation Delay Preset or Clear to Q or Q tREM Minimum Removal Time, Preset or Clear to Clock ts Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock, Preset or Clear AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions TA = 25C VCC TA = -40 to 85C TA = -55 to 125C Typ Guaranteed Limits Units Maximum Operating 2.0V 22 6 5 4 MHz Frequency 4.5V 72 30 24 20 MHz 6.0V 94 35 28 24 MHz tPHL, tPLH Maximum Propagation 2.0V 34 110 140 165 ns Delay Clock to Q or Q 4.5V 12 22 28 33 ns 6.0V 10 19 24 28 ns 2.0V 66 150 190 225 ns Delay Preset or Clear 4.5V 20 30 38 45 ns To Q or Q 6.0V 16 26 33 38 ns Minimum Removal Time 2.0V 20 50 65 75 ns Preset or Clear 4.5V 6 10 13 15 ns ns fMAX tPHL, tPLH Maximum Propagation tREM ts tH To Clock 6.0V 5 9 11 13 Minimum Setup Time 2.0V 35 80 100 120 ns Data to Clock 4.5V 10 16 20 24 ns 6.0V 8 14 17 20 ns Minimum Hold Time 2.0V 0 0 0 ns 4.5V 0 0 0 ns 6.0V 0 0 0 ns Clock to Data tW Minimum, Pulse Width Clock, Preset or Clear tTLH, tTHL Maximum Output Rise and Fall Time tr , tf CPD 2.0V 30 80 101 119 ns ns 4.5V 9 16 20 24 6.0V 8 14 17 20 ns 2.0V 25 75 95 110 ns 4.5V 7 15 19 22 ns 6.0V 6 13 16 19 ns Maximum Input Rise 2.0V 1000 1000 1000 ns and Fall Time 4.5V 500 500 500 ns 6.0V 400 400 400 Power Dissipation (per flip-flop) 80 ns pF Capacitance (Note 6) CIN Maximum Input 5 10 10 10 Capacitance Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF MM74HC74A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HC74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)