MCP3911A0T-E/SS - Microchip Technology

MCP3911

Features

• Two Synchronous Sampling 16/24-bit Resolution

Delta-Sigma A/D Converters

• 94.5 dB SINAD, -106.5 dBc Total Harmonic

Distortion (THD) (up to 35th harmonic), 111 dB

SFDR for Each Channel

• 2.7V - 3.6V AVDD, DVDD

• Programmable Data Rate up to 125 ksps

- 4 MHz Maximum Sam pli ng Frequency

• Oversampling Ratio up to 4096

• Ultra Low Power Shutdown Mode with <2 µA

• -122 dB Crosstalk between the Two Channels

• Low Drift 1.2V Internal Voltage Reference: 7 ppm/°C

• Differential Voltage Reference Input Pins

• High Gain PGA on Each Channel (up to 32V/V)

• Phase Delay Comp ensation with 1 µs Time

Resolution

• Separate Modulator Output Pi ns for Each

Channel

• Separate Data Ready Pin f or Easy

Synchronization

• Individual 24-bit Digital Offset and Gain Error

Correction for Each Channel

• High-Speed 20 MHz SPI Interface with Mode 0,0

and 1,1 Compatibility

• Contin uou s Re ad/W r i te M od es for Minim um

Communication

• Low Power Consumption (8.9 mW at 3.3V,

5.6 mW at 3.3V in low-power mode, typical)

• Available in Small 20-lead QFN and SSOP Pack-

ages, Pin-to-pin Compatible with MCP3901

• Extended Temperature Range: -40°C to +125°C

Applications

• Energy Metering and Power Measurement

• Automotive

• Portable Instrumentation

• Medica l and Pow er Mo nito rin g

• Audio/Voice Recognition

Description

The MCP3911 is a 2.7V to 3.6V dual channel Analog

Front End (AFE) cont a ining two sync hronous samp ling

Delta-Sigma Analog-to-Digital Converters (ADC), two

PGAs, phase delay compensation block, low-drift

internal voltage reference, modulator output block,

digital offset and gain errors calibration registers, and

high-speed 20 MHz SPI compatible serial interface.

The MCP3911 ADCs are fully configurable with fea-

tures such as: 16/24-bit resolution, OSR from 32 to

4096, gain from 1x to 32x, independent shutdown and

reset, dithering and auto-zeroing. The communication

is largely simplified with the one-byte-long commands

including various continuous read/write modes that can

be accessed by the Direct Memory Access (DMA) of an

MCU, and with a separate data ready pin that can be

directly connected to an Interrupt Request (IRQ) input

of an MCU.

The MCP3911 is capable of interfacing a large variety

of voltage and current sensors including shunts,

current transformers, Rogowski coils and Hall effect

sensors.

Package Type

OSC1/CLKI

OSC2

SDI

RESET

DVDD

AVDD

CH0+

CH0-

CH1-

9DGND

MDAT0

MDAT1

DR CH1+

AGND

SDO

REFIN+/OUT

REFIN-

SCK

SDO

20-Lead

SSOP

20-Lead

QFN

CH1-

CH1+

CH0+ SCK

REFIN+/OUT

OSC2

REFIN-

DGND

MDAT1

OSC1/CLKI

AVDD

DVDD

RESET

SDI

CH0- EP

19 18 17

6789

510

AGND

MDAT0

3.3V Two-Channel Analog Front End

MCP3911

Functional block diagram

CH0+

CH0-

CH1+

CH1-

DUAL Δ–Σ ADC

ANALOG DIGITAL

SINC3+

SINC1

PGA

PGA Δ–Σ

Modulator

AMCLK

DMCLK/DRCLK

Phase

Shifter

ΦPHASE <11:0>

DATA_CH0

<23:0>

MOD<7:0>

REFIN+/OUT

REFIN-

AVDD

AGND DGND

DVDD

MOD<3:0>

MOD<7:4>

POR

AVDD

Monitoring

Δ–Σ

Modulator

Vref+Vref-

VREFEXT

Voltage

Reference

Vref

POR

DVDD

Monitoring

SDO

SDI

SCK

Xtal Oscillator

MCLK OSC1

OSC2

RESET

Digital SPI

Interface

Clock

Generation

Modulator

Output Block MDAT1

MDAT0

DMCLK OSR<2:0>

PRE<1:0>

MODOUT<1:0>

OFFCAL_CH0

<23:0>

GAINCAL_CH0

<23:0>

OFFCAL_CH1

<23:0>

GAINCAL_CH1

<23:0>

DATA_CH1

<23:0>

SINC3+

SINC1

MCP3911

1.0 ELECTRICAL

CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS †

VDD .....................................................................-0.3V to 4.0V

Digital inputs and outputs w.r.t. AGND.......... .. ....--0. 3 V to 4 .0 V

Analog input w.r.t. AGND........ ............. ............ ........-2V to +2V

VREF input w.r.t. AGND......... ......................-0.6V to V DD +0.6V

Storage temperature ............... .... .. .. ....... .. .. .. .-65°C to +150°C

Ambient temp. with power applied................-65°C to +125°C

Soldering temperature of leads (10 seconds).............+300°C

ESD on the analog inputs (HBM,MM ).................4.0 kV, 200V

ESD on all other pins (HBM,MM)........................4.0 kV, 200V

† Notice: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanen t damage to the device.

This is a stress rating only and functional operation of the

device at those or any other conditions, above those indi-

cated in the operational listings of this specification, is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.1 ELECTRICAL SPECIFICATIONS

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE

Electrical S pecificatio ns: Unless oth erwise indic ated, all p arameter s apply at A V DD = DVDD = 2.7V to 3.6V, MCLK =

4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11,

BOOST<1:0> = 10; VCM=0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz on both channels.

Sym Characteristic Min Typ Max Units Test Conditions

ADC Performance

Resolution (No Missing

Codes) 24 -- -- bits OSR = 256 or greater

fS(DMCLK) Sampling Frequency 1 4 MHz For maximum condi-

tion, BOOST<1:0> = 11

fD(DRCLK) Output Data Rate 4 125 ksps For maximum condi-

tion, BO OST<1: 0> = 11,

OSR = 32

CH0+/- Analog Inp ut Abs olu te Volt age

on CH0+, CH0-, CH1+, CH1-

pins

-1 +1 V All analog input

channels, measured to

AGND

IIN Analog Input Leakage Current +/-1 nA RESET<1:0>=11, MCLK

running con t in uou sl y

(CHn+-CHn-) Differential Input Voltage

Range -600/GAIN +600/ GAIN mV VREF=1.2V,

proportional to VREF

VOS Offset Error -1 0.2 +1 mV (Note 4)

Offset Error Drift 0.5 µV/°C

GE Gain Error -4 +4 % (Note 4)

Note 1: This specification implies that the ADC output is valid over this entire dif f erential range and that there is no distortion or

instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN =

1.2VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See terminology section for definition. This parameter is established

by characterization and not 100% tested. See performance graphs for other than default settings provided here.

2: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,

VREFE XT=0, CL KEXT=0 .

3: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=11, VREFEXT=1,

CLKEXT=1.

4: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical per-

formance.

5: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2 V can be applied continuously to

the part with no damage.

6: For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in

the Table 5-2 as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the pres-

caler settings (PRE<1:0>) limit AMCLK=MCLK/PRES CALE in the defined range in the Table 5-2.

MCP3911

Gain Error Drift 1 ppm/°C

INL Integral Non-Linearity 5 ppm

ZIN Differential Input Impedance 232 — — kΩG=1, proportional to 1/

AMCLK

142 — — kΩG=2, proportional to 1/

AMCLK

72 — — kΩG=4, proportional to 1/

AMCLK

38 — — kΩG=8, proportional to 1/

AMCLK

36 — — kΩG=16, proportional to 1/

AMCLK

33 — — kΩG=32, proportional to 1/

AMCLK

SINAD Signal-to-Noise and Distortion

Ratio (Note 1) 92 94.5 — dB

THD Tot al Harm oni c Di sto rtio n

(Note 1) -106.5 -103 dBc Includes the first 35 har-

monics

SNR Signal to Noise Ratio (Note 1) 92 95 dB

SFDR S purious Free Dynamic Range

(Note 1) 111 dBFS

CTALK Crosst alk (50, 60 Hz) — -122 — dB

AC PSRR AC Power Supply Reject ion — -73 — dB AVDD = DVDD = 3.3V +

0.6Vpp, 50/60 Hz,

100/120 Hz

DC PSRR DC Power Supply Rejection — -73 — dB AVDD = DVDD = 2.7V to

3.6V

DC CMRR DC Common Mode Rejection — -105 — dB VCM from -1V to +1V

Internal Voltage Reference

VREF Tolerance 1.176 1.2 1.224 V VREFEXT = 0, TA =

25°C only

TCVREF Temperature Coefficient — 7 — ppm/°C TA = -40°C to +125°C,

VREFEXT = 0

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical S pecificatio ns: Unless oth erwise indic ated, all p arameter s apply at A V DD = DVDD = 2.7V to 3.6 V, MCLK =

4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11,

BOOST<1:0> = 10; VCM=0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz on both channels.

Sym Characteristic Min Typ Max Units Test Conditions

Note 1: This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or

instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN =

1.2VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See terminology section for definition. This parameter is established

by characterization and not 100% tested. See performance graphs for other than default settings provided here.

2: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,

VREFEXT=0, CLKEXT =0.

3: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=11, VREFEXT=1,

CLKEXT=1.

4: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical per-

formance.

5: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2 V can be applied continuously to

the part with no damage.

6: For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in

the Table 5-2 as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the pres-

caler settings (PRE<1:0>) limit AMCLK=MCLK/PRES CALE in the defined range in the Table 5-2.

MCP3911

ZOUTVREF Output Impedance 2 — kΩVREFEXT = 0

AIDDVREF Internal Voltage Reference

Operating Current 25 — µA VREFEXT=0, SHUT-

DOWN<1:0>=11

Voltage Referen ce Input

Input Capacitance — — 10 pF

VREF Differential Input Voltage

Range (VREF+ - VREF -) 1.1 — 1.3 V VREFEXT = 1

VREF+ Absolute Voltage on

REFIN+ pin VREF- +

1.1 —V

REF- + 1.3 V VREFEXT = 1

VREF- Absolute Voltage REFIN- pin -0.1 — +0.1 V REFIN- should be con-

nected to AGND when

VREFEXT=0

Master Clock Input

fMCLK Master Clock Input Freq uency

Range — 2 0 MHz CLKEXT = 1, (Note 6)

fXTAL Crystal Oscillator Operating

Frequency Range 1 — 20 MHz CLKEXT = 0, (Note 6)

AMCLK Analog Master Clock — — 16 MHz (Note 6)

Power Supply

AVDD Operating Voltage, Analog 2.7 — 3.6 V

DVDD Operating Voltage, Digital 2.7 — 3.6 V

IDD,A Operating Current, Analog

(Note 2) — 1.5 2.3 mA BOOST<1:0>=00

— 1.8 2.8 mA BOOST<1:0>=01

— 2.5 3.5 mA BOOST<1:0>=10

— 4.4 6 .25 mA BOOST<1:0>= 11

IDD,D Operating Current, Digital — 0.2 0.3 mA MCLK = 4 MHz,

proportional to MCLK

— 0.7 — mA MCLK = 16 MHz, pro-

portional to MCLK

IDDS,A Shutdown Current, Analo g — — 1 µ A AVDD pin only (Note 3)

IDDS,D Shutdown Current, Digital — — 1 µA DVDD pin only (Note 3)

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical S pecificatio ns: Unless oth erwise indic ated, all p arameter s apply at A V DD = DVDD = 2.7V to 3.6V, MCLK =

4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11,

BOOST<1:0> = 10; VCM=0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz on both channels.

Sym Characteristic Min Typ Max Units Test Conditions

Note 1: This specification implies that the ADC output is valid over this entire dif f erential range and that there is no distortion or

instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range, VIN =

1.2VPP = 424 mVRMS, VREF = 1.2V @ 50/60 Hz. See terminology section for definition. This parameter is established

by characterization and not 100% tested. See performance graphs for other than default settings provided here.

2: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,

VREFE XT=0, CL KEXT=0 .

3: For these operating currents the following configuration bit settings apply: SHUTDOWN<1:0>=11, VREFEXT=1,

CLKEXT=1.

4: Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical per-

formance.

5: Outside of this range, ADC accuracy is not specified. An extended input range of +/-2 V can be applied continuously to

the part with no damage.

6: For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in

the Table 5-2 as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the pres-

caler settings (PRE<1:0>) limit AMCLK=MCLK/PRES CALE in the defined range in the Table 5-2.

MCP3911

1.2 SERIAL INTERFACE CHARACTERISTICS

TABLE 1-2: SERIAL DC CHARACTERISTICS TABLE

Electrical S pe cific ations: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to

+125°C, CLOAD = 30pF, applies to all digital I/O.

Sym Characteristics Min Typ Max Units Test Conditions

VIH Hi gh-l ev el Inp ut vol t age 0.7 DVDD — V Schmitt Triggered

VIL Low-level Input voltage — 0.3 DVDD V Schmitt Triggered

ILI Input leakage current — — ±1 µA CS = DVDD, VIN = DGND TO

DVDD

ILO Output leakage current — — ±1 µA CS = DVDD, VOUT = DGND OR

DVDD

VHYS Hysteresis of Schmitt Trig-

ger Inputs —200 mV(Note 2), DVDD = 3.3V only

VOL Low-level output

voltage ——0.4VIOL = +2.1mA, DVDD = 3.3V

VOH High-level output

voltage DVDD -0.5 — — V IOH = -2.1mA, DV DD = 3.3V

CINT Internal capacitance

(all inputs and

outputs)

——7 pFTA = 25°C, SCK = 1.0 MHz,

DVDD =3.3V (Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is established by characterization and not production tested.

TABLE 1-3: SERIAL AC CHARACTERISTICS TABLE

Electrical S pe cific ations: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to

+125°C, GAIN = 1, CLOAD = 30pF.

Sym Characteristics Min Typ Max Units Test Conditions

fSCK Serial Clock frequency — — 20 MHz

tCSS CS setu p time 25 — — ns

tCSH CS hold time 50 — — ns

tCSD CS disable time 50 — — ns

tsu Data setup time 5 — — ns

tHD Data hold time 10 — — ns

tHI Serial Clock high time 20 — — ns

tLO Serial Clock low time 20 — — ns

tCLD Serial Clock delay time 50 — — ns

tCLE Serial Clock enable time 50 — — ns

tDO Output valid from SCK low — — 25 ns

tDOMDAT Modulator output valid from

AMCLK high ——1/(2*AMCLK) s

tHO Output hold time 0 — — ns (Note 1)

tDIS Output disable time — — 25 ns (Note 1)

tMCLR Reset Pulse Width (RESET)100 — — ns

tDODR Data Transfer Time to DR

(Data Ready)—25 ns(Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is established by characterization and not production tested.

MCP3911

FIGURE 1-1: Serial Output Timing Diagram.

tMODSU Modulator Mode Entry to

Modulator Data Present —100 ns

tDRP Data Ready Pulse Low Time 1/DMCLK —µs

TABLE 1-3: SERIAL AC CHARACTERISTICS T ABLE (CONTINUED)

Electrical S pe cific ations: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to

+125°C, GAIN = 1, CLOAD = 30pF.

Sym Characteristics Min Typ Max Units Test Conditions

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is established by characterization and not production tested.

TABLE 1-4: TEMPERATURE SPECIFICATIONS TABLE

Electrical S pe cific ations: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V, DVDD = 2.7 to

3.6V.

Parameters Sym Min Typ Max Units Conditions

Te mperature Ranges

Operati ng Temperature

Range TA-40 — +125 °C (Note 1)

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 20L

SSOP θJA — 89.3 — °C/W

Thermal Resistance, 20L

QFN θJA —43 — °C/W

Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150C.

tCSH

tDIS

tHI tLO

fSCK

SCK

SDO MSB out LSB out

SDI

Mode 1,1

Mode 0,0

tHO

tDO

DON’T CARE

MCP3911

FIGURE 1-2: Serial Input Timing Diagram.

FIGURE 1-3: Data Ready Pulse / Sampling Timing Diagram.

SCK

SDI LSB in

MSB in

Mode 1,1

Mode 0,0

tCSS

tSU tHD

tCSD

tCSH tCLD

tCLE

SDO

HI-Z

tHI tLO

fSCK

SCK

tDRP

SDO

1 / fD

DODR

MCP3911

FIGURE 1-4: Timing Diagrams, continued.

CS VIH

Waveform for tDIS

HI-Z

90%

10%

tDIS

SDO

SCK

SDO

tDO

Timing Waveform for tDO

MDAT

OSC1/CLKI

Timing Waveform for MDAT0/1

Modulator Output Function

tDOMDAT

MCP3911

NOTES:

MCP3911

2.0 TYPICAL PE RFORMANCE CURVES

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-1: Spectral Response.

FIGURE 2-2: Spectral Response.

FIGURE 2-3: THD Histogram.

FIGURE 2-4: Spectr al Res pon se .

FIGURE 2-5: Spectr al Res pon se .

FIGURE 2-6: SINAD Histog ram.

Note: The g r ap hs and t ables provided fol low i ng thi s n ote are a statistical s umm ary based on a l im ite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

ncy of Occurrence

-107.3 -107.1 -107.0 -106.8 -106.7 -106.5 -106.4 -106.2 -106.1 -105.9 -105.8

Frequ

Total Harmonic Distortion (-dBc)

cy of Occurrence

94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5

Freque

Signal-to-Noise and Distortion Ratio (dB)

MCP3911

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-7: Spurio us F ree Dynam ic

Range Histogram.

FIGURE 2-8: SNR Histogram.

FIGURE 2-9: Noise Histogram.

FIGURE 2-10: ENOB SINAD Histogram.

FIGURE 2-11: ENOB SNR Histogram.

FIGURE 2-12: THD vs. OSR.

ncy of Occurrence

104.5 106 107.5 109 110.5 112 113.5 115

Frequ

Spurious Free Dynamic Range (dBFS)

ency of Occurrence

94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 95.6 95.8 95.9

Frequ

Signal to Noise Ratio (dB)

1000

1500

2000

2500

3000

3500

4000

4500

5000

ency Of Occurrence

Channel 1

VIN = 0V

TA= 25 C

16384 Consecutive

Readings

500

1000

Freq

Output Code (LSB)

uencyofOccurrence

15.3 15.4 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6

Fre

EffectiveNumberofBits(SINAD)

uencyofOccurrence

15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 15.6 15.6

Fre

EffectiveNumberofBits(SNR)

-70

-60

-50

-40

-30

-20

-10

onic Distortion (dBc)

rin

= M

Dithering = Minimum

Dithering = None

-120

-110

-100

-90

32 64 128 256 512 1024 2048 4096

Total Har

Oversampling Ratio (OSR)

Dithering = Maximum

te g

ed u

MCP3911

Note: Unles s otherwise in dicated, AVDD = 3.3V, DVDD = 3.3V ; TA = 25 °C, MCLK = 4 MHz; PRESCALE = 1; OSR

= 256; GAIN = 1; Ditherin g = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ

= 0; BOOST = 1X.

FIGURE 2-13: SI NAD vs. OSR .

FIGURE 2-14: SNR vs.OSR.

FIGURE 2-15: SFDR vs. OSR.

FIGURE 2-16: THD vs. MCLK.

FIGURE 2-17: SINAD vs. MCLK.

FIGURE 2-18: SNR vs. MCLK.

100

110

120

-Noise and Distortion

Ratio (dB)

Dithering = Maximum

Dithering = Medium

Dithering = Minimum

Dithering = None

32 64 128 256 512 1024 2048 4096

Signal-t

Oversampling Ratio (OSR)

100

110

120

to-Noise Ratio (dB)

Dithering = Maximum

Dithering = Medium

Dithering = Minimum

Dithering = None

32 64 128 256 512 1024 2048 4096

Signal

Oversampling Ratio (OSR)

100

110

120

130

140

ee Dynamic Range

(dBFS)

Dithering = Maximum

Dithering = Medium

Dithering = Minimum

Dithering = None

32 64 128 256 512 1024 2048 4096

Spurious F

Oversampling Ratio (OSR)

-80

-70

-60

-50

-40

-30

-20

-10

rmonic Distortion (dBc)

Boost = 0.5x

Boost = 0.66x

Boost = 1x

-120

-110

-100

0 5 10 15 20 25 30

Total Ha

MCLK Frequency (MHz)

Boost = 2x

100

110

120

Noise and Distortion

Ratio (dB)

Boost

=05x

Boost = 0.66x

Boost = 2x

Boost = 1x

0 5 10 15 20 25 30

Signal-to

MCLK Frequency (MHz)

Boost

100

110

120

al to Noise Ratio (dB)

Boost = 0.5x

Boost = 0.66x

Boost = 2x

Boost = 1x

0 5 10 15 20 25 30

Sign

MCLK Frequency (MHz)

MCP3911

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3 V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-19: SFDR vs. MCLK.

FIGURE 2-20: SINAD vs. GAIN.

FIGURE 2-21: SINAD vs. GAIN (Dithering

Off).

FIGURE 2-22: SINAD vs. GAIN vs. AZ

Speed Chart.

FIGURE 2-23: THD vs. Input Signal

Amplitude.

FIGURE 2-24: SINAD vs. Input Si gna l

Amplitude.

100

110

120

Free Dynamic Range

(dBFS)

Boost = 0.5x

Boost = 0.66x

Boost = 2x

Boost = 1x

0 5 10 15 20 25 30

Spurious

Frequency (MHz)

100

110

120

oise and Distortion

atio (dB)

OSR = 32 OSR = 64 OSR = 128 OSR = 256

OSR = 4096

OSR = 2048

OSR = 1024

OSR = 512

12481632

Signal to

Gain (V/V)

100

12481632

Signal to Noise and Distortion Ratio (dB)

Gain (V/V)

Auto Zero Speed = Fast

Auto Zero Speed = Slow

-70

-60

-50

-40

-30

-20

-10

nic Distortion (dBc)

-120

-110

-100

-90

-6 -5 -4 -3 -2 -1 0 1 2 3

Total Harm

Input Signal Amplitude (dBFS)

Channel 0

Channel 1

100

110

120

-6 -5 -4 -3 -2 -1 0 1 2 3

Signal to Noise and Distortion

Ratio (dB)

Input Signal Amplitude (dBFS)

Channel 0

Channel 1

MCP3911

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-25: SNR vs. Input Signal

Amplitude.

FIGURE 2-26: SFDR vs. Input Signal

Amplitude.

FIGURE 2-27: THD vs. Temperature.

FIGURE 2-28: SINAD vs. Tempera ture.

FIGURE 2-29: SNR vs. Temperature.

FIGURE 2-30: SFDR vs. Temperature.

100

110

120

to Noise Ratio (dB)

Channel 0

Channel 1

-6 -5 -4 -3 -2 -1 0 1 2 3

Signal

Input Signal Amplitude (dBFS)

100

110

120

Free Dyanmic Raneg

(dBFS)

Channel 0

Channel 1

-6 -5 -4 -3 -2 -1 0 1 2 3

Spuriou

Input Signal Amplitude (dBFS)

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-50 -25 0 25 50 75 100 125 150

Total Harominc Distortion

(dBc)

Temperature (°C)

G=32

G=16

G=8

G=4

G=2

G=1

100

-50 -25 0 25 50 75 100 125 150

Signal to Noise and Distortion

Ration (dB)

Temperature (°C)

G=32

G=16

G=8

G=4

G=2

G=1

100

-50 -25 0 25 50 75 100 125 150

Signal to Noise Ratio (dB)

Temperature (°C)

G=32

G=16

G=8

G=4

G=2

G=1

100

110

120

-50 -25 0 25 50 75 100 125 150

Spurious Free Dynamic Range

(dBFS)

Temperature (°C)

G=32

G=16

G=8

G=4

G=2

G=1

MCP3911

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-31: Channel 0 Offset vs.

Temperature.

FIGURE 2-32: Channel 1 Offset vs.

Temperature.

FIGURE 2-33: Channel to Channel Offset

Match vs. Temperature.

FIGURE 2-34: Gain Error vs. Temperature.

FIGURE 2-35: Internal Voltage Reference

vs. Temperature.

FIGURE 2-36: Internal Voltage Reference

vs. Supply Voltage.

100

150

200

250

300

350

400

nnel 0 Offset (

G=32

G=16

G=8

G=4

-100

-50

-50 -25 0 25 50 75 100 125 150

Temperature (°C)

G=2

G=1

100

150

200

250

300

350

400

nnel 1 Offset (

G=32

G=16

G=8

G=4

-100

-50

-50 -25 0 25 50 75 100 125 150

Temperature (°C)

G=2

G=1

-80

-60

-40

-20

ffset Error (

CHANNEL 0

CHANNEL 1

-120

-100

-50 -25 0 25 50 75 100 125 150

Temperature (°C)

CHANNEL 0

1.1997

1.1998

1.1999

1.2000

1.2001

1.2002

1.2003

2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

Internal Voltage Reference (V)

VDD (V)

MCP3911

Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1;

OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1,

AZ_FREQ = 0; BOOST = 1X.

FIGURE 2-37: VREF Drift Data Histogram

Chart.

FIGURE 2-38: Integral Non-Linearity

(Dithering Maximum).

FIGURE 2-39: Integral Non-Linearity

(Dithering Off).

FIGURE 2-40: Operating Current vs.

MCLK, VDD = 3.3V.

FIGURE 2-41: Operating Current vs.

MCLK, VDD = 2.7V.

03691215182124

Frequency of Occurrence

Internal Voltage Reference Drift (ppm/C)

-5

n Linearity Error (ppm)

Channel 1

-25

-20

-15

-0.6 -0.3 0 0.3 0.6

Integral No

Input Voltage (V)

Channel 0

-5

n Linearity Error (ppm)

Channel 0

Channel 1

-25

-20

-15

-0.6 -0.3 0 0.3 0.6

Integral No

Input Voltage (V)

Channel 1

2.5

3.5

4.5

IDD (mA)

AIDD, Boost = 2x

AIDD, Boost = 1x

AIDD, Boost = 0.6x

0.5

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30

MCLK Frequency (MHz)

AIDD, Boost = 0.5x

DIDD, All Boost Settings

1.5

2.5

3.5

IDD (mA)

AIDD, Boost = 2x

AIDD, Boost = 1x

AIDD, Boost = 0.6x

0.5

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30

MCLK Frequency (MHz)

AIDD, Boost = 0.5x

DIDD, All Boost Settings

MCP3911

NOTES:

MCP3911

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Master Reset (RESET)

This pin is active low and places the entire chip in a

reset state when active.

When RESET=0, all registers are reset to their default

value, no communication can take place, and no clock

is distributed inside the pa rt, except in the input struc-

ture if MCLK is applied (if idle, then no clock is distrib-

uted). This state is equivalent to a POR state.

Since the default state of the ADCs is on, the analog

power consumption, when RESET=0, is equivalent to

when RESET=1. Only the digital power consumption is

largely reduced because this current consumption is

essentially dynamic and is reduced drastically when

there is no clock running.

All the analog biases are enabled during a reset so that

the part is fully operational just after a RESET rising

edge, if the MCLK is applied during the rising edge. If

not applied, there is a small time after RESET where

the conversion may not be accurate corresponding to

the startup of the charge pump of the input structure.

This input is Schmitt triggered.

3.2 Digital VDD (DVDD)

DVDD is the power supply pin for the digital circuitry

within the MCP3911. This pin requires appropriate

bypass capacitors and should be maintained between

2.7V and 3.6V for specified operation.

3.3 Analog VDD (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP3911. This pin requires appropriate

bypass capacitors and should be maintained to 2.7V

and 3.6V for specified operation.

3.4 ADC Differential Analog inputs

(CHn+/CHn-)

CH0- and CH0+, and CH1- and CH1+, are the two

fully-differential analog voltage inputs for the

Delta-Sigma ADCs.

Pin No.

SSOP Pin No.

QFN Symbol Function

1 18 RESET Master Reset Logic Input Pin

219 DV

DD Digital Power Supply Pin

320 AV

DD Analog Power Supply Pin

4 1 CH0+ Non-Inverting Analog Input Pin for Channel 0

5 2 CH0- Inverting Analog Input Pin for Channel 0

6 3 CH1- Inverting Analog Input Pin for Channel 1

7 4 CH1+ Non-Inverting Analog Input Pin for Channel 1

8 5 AGND Analog Ground Pin, Return Path for internal analog circuitry

9 6 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin

10 7 REFIN- Inverting Voltage Reference Input Pin

11 8 DGND Digital Ground Pin, Return Path for internal digital circuitry

12 9 MDAT1 Modulator Data Output Pin for Channel 1

13 10 MDAT0 Modulator Data Output Pin for Channel 0

14 11 DR Data Ready Signal Output Pin

15 12 OSC1/CLKI Oscillato r Cryst a l Co nne cti on Pin or Extern al Cloc k Inpu t Pin

16 13 OSC2 Oscillator Crystal Connection Pin

17 14 CS Serial Inte rfac e Chip Sele ct Pin

18 15 SCK Serial Interface Clock Input Pin

19 16 SDO Serial Interface Data Input Pin

20 17 SDI Serial Interface Data Input Pin

- 21 EP Exposed Thermal Pad. Must be connected to AGND.

MCP3911

The linear and specified region of the channels are

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV/GAIN with

VREF=1.2V.

The maximum differential voltage is proportional to the

VREF voltage. The maximum absolute voltage, with

respect to AGND, for each CHn+/- input pin is +/-1V

with no distortion and ±2V with no breaking after con-

tinuous voltage. This maximum absolute voltage is not

proportional to the VREF voltage.

3.5 Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry (See the “Functional block diagram”). To

ensure accuracy and noise cancellati on, this pin must

be conn ected to the s ame ground a s DGND, prefer ably

with a star connection. If an analog ground plane is

availa ble, it is rec omme nded th at this pin be tied to this

plane of the PCB. This plane should also reference all

other analog circuitry in the system.

3.6 Non-inve rting Reference Input,

Internal Reference Output

(REFIN+/OUT)

This pin is the non-inverting side of the differential

voltage reference input for both ADCs or the internal

voltage reference output.

When VREFEXT=1, an external voltage reference

source can be used, the internal voltage reference is

disabled. When using an external differential voltage

reference, it should be connected to its VREF+ pin.

When using an external single-ended reference, it

should be connected to this pin.

When VREFEXT=0, the internal voltage reference is

enabled and connected to this pin through a switch.

This voltage reference has minimal drive capability and

thus needs proper buffering and bypass capacitances

(a 0.1 µF ceramic capacitor is sufficient in most cases)

if used as a voltage source.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not nece ssary for keeping ADC accuracy , but a minimal

0.1 µF ceram ic cap ac ita nce ca n be conn ect ed to avoi d

EMI/EMC susceptibility issues due to the antenna cre-

ated by the REFIN+/OUT pin if left floating.

3.7 Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage

referenc e input for both ADCs. Whe n using an ext ernal

differential voltage reference, it should be connected to

its VREF- pin. When using an external single-ended

voltage reference, or when VREFEXT=0 (Default) and

using the internal voltage reference, this pin should be

directly connected to AGND.

3.8 Digital Ground Connection

(DGND)

DGND is the ground connection to internal digital

circuitry (See the MCP3911 Block diagram). To ensure

optimal accuracy and noise cancellation, DGND must

be connec ted to the same ground as AGND, pre ferably

with a star connection. If a digital ground plane is

availa ble, it is recomm ended that th is pin be tie d to thi s

plane of the Printed Circuit Board (PCB). This plane

should also reference all other digital circuitry in the

system.

3.9 Modulator Data Output Pin for

Channel 1 and Channel 0 (MDAT1/

MDAT0)

MDAT0 and MDAT1 are the output pins for the

modulator serial bitstreams of ADC channels 0 and 1,

respectively. These pins are high impedance when

their corresponding MODOUT bit is logic low . When the

MODOUT<1:0> are enabled, the modulator bitstream

of the corresponding channel is p r esent on the pi n an d

updated at the AMCLK frequency. (See Section 5.4

“Modulator O utput Block ” for a complete description

of the modulator outputs). These pins can be directly

connected to a MCU or DSP when a specific digital

filtering is needed.

3.10 Data Ready Output (DR)

The data ready pin indica tes if a new conversion re su lt

is ready to be read. The default state of this pin is high

when DR_HIZ=1 and is high impedance when

DR_HIZ=0 (Defaul t). Af te r eac h co nv ers ion is finis he d,

a logic low pulse will take place on the data ready pin

to indicate the conversion result is ready as an inter-

rupt. This pulse is synchronous with the master clock

and has a defined and constant width.

The data ready pin is independent of the SPI interface

and acts like an interrupt output. The data ready pin

state is not la tched and th e pulse wid th (and period) are

both determined by the MCLK frequency,

over-sampling rate, and internal clock pre-scale

settings. The DR pulse width is equal to one DMCLK

period and the frequency of the pulses is equal to

DRCLK (see Figure 1-3).

Note: This pin should not be left floating when

DR_HIZ bit is low; a 100 kΩ pull-up

resistor connected to DVDD is

recommended.

MCP3911

3.11 Oscillator And Master Clock Input

Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock

(MCLK) for the device. When CLKEXT=0, a resonant

crystal or clock source with a similar sinusoidal wave-

form must be placed across these pins to ensure

prope r operati on. The typic al clo ck frequen cy sp ecifie d

is 4 MHz. For prope r operatio n, and for optimizing ADC

accuracy, AMCLK should be limited to the maximum

frequency defined in the Table 5-3 in function of the

BOOST and PGA setting chosen. MCLK can take

larger values as long as the prescaler settings

(PRE<1:0>) limit AMCLK=MCLK/PRESCALE in the

defined range in the Table 5-3. Appropriate load

capacitance should be connected to these pins for

proper operation.

3.12 Chip Select (CS)

This pin is the SPI chip select that enables the serial

communication. When this pin is high, no

communication can take place. A chip select falling

edge initiates the serial communication and a chip

select rising edge terminates the communication. No

communication can take place even when CS is low

when RESET is low.

This input is Schmitt-triggered.

3.13 Serial Data Clock (SCK)

This is the serial clock pin for SPI communication.

Data is clocked into the device on the RISING edge of

SCK. Dat a is cl ocked o ut of the d evice on the FALLING

edge of SCK.

The MC P391 1 inte rface is comp atible with bo th SPI 0,0

and 1,1 modes. SPI modes can be changed during a

CS high time.

The maximum clock speed specified is 20 MHz.

This input is Schmitt triggered.

3.14 Serial Data Output (SDO)

This i s the SP I data out put pin . Data is cl ocked ou t of

the device on the FALLING edge of SCK.

This pin stays high impedance during the first

comma nd byte. It also s tays high impedance durin g the

whole communication for write commands and when

CS pin is high or when RESET pin is low. This pin is

activ e on ly wh en a rea d comm an d is pr oc es se d. Ea ch

read is processed by packet of 8 bits.

3.15 Serial Data Input (SDI)

This is the SPI data input pin. Data is clocked into the

device on the RISING edge of SCK.

When CS is low , th is pin is use d to commun icate with a

series of 8-bit commands.

The interface is half-duplex (inputs and outputs do not

happen at the same time).

Each communication starts with a chip select falling

edge followed by an 8-bit command word entered

through t he SDI pin. Ea ch command is either a R ead or

a Write command. Toggling SDI during a Read

command has no effect.

This input is Schmitt triggered.

MCP3911

NOTES:

MCP3911

4.0 TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this data sheet. The following terms are

defined:

MCLK - Mast er Clock

AMCLK - Analog Maste r Clock

DMCLK - Digital Master Clock

DRCLK - Data Rate Clock

OSR - Oversampling Ratio

Offset Error

Gain Error

Integral N on-L ine ari ty Error

Signal-To-Noise Ratio (SNR)

Signal-To-Noise Ratio And Distortion (SINAD)

Total Harmonic Distortion (THD)

Spurious-Free Dynamic Range (SFDR)

MCP3911 Delta-Sigma Architecture

Idle Tones

Dithering

Crosstalk

PSRR

CMRR

ADC Reset Mode

Hard Reset Mode (RESET = 0)

ADC Shutdown Mode

Full Shutdown Mode

4.1 MCLK - Master Clock

This is the fastest clock present in the device. This is

the frequency of the crystal placed at the OSC1/OSC2

inputs when CLKEXT=0 or the frequency of the clock

input at the OSC1/CLKI when CLKEXT=1. See

Figure 4-1.

4.2 AMCLK - Analog Master Clock

This is the clock frequency th at is present on the analog

portion of the device, after prescaling has occurred via

the CONFIG PRE<1:0> register bits. The analog

portion includes the PGAs and the two Delta-Sigma

modulators.

FIGURE 4-1: Clock Sub-circuitry.

4.3 DMCLK - Digital Master Clock

This is the clock frequency that is present on the digital

portion o f the de vice, af ter pr escalin g and divi sion by 4.

This is also the sampling frequency, that is the rate at

which the modulator outputs are refreshed. Each

period o f this clock corresponds to one sample an d one

modulator output. See Figure 4-1.

EQUATION 4-1:

4.4 DRCLK - Data Rate Clock

This is the output data rate, i.e., the rate at which the

ADCs ou tput ne w da ta. Each n ew dat a is sign aled b y a

dat a read y pul se on the DR pin .

This data rate is depending on the OSR and the

prescaler with the following formula:

EQUATION 4-2:

TABLE 4-1: MCP3911 OVERSAMPLING

RATIO SETTINGS

Config Analog Master Clock

Prescale

PRE<1:0>

0 0 AMCLK = MCLK/ 1 (default)

01 AMCLK = MCLK/ 2

10 AMCLK = MCLK/ 4

11 AMCLK = MCLK/ 8

AMCLK MCLK

PRESCALE

-------------------------------=

DMCLK AMCLK

---------------------MCLK

4 PRESCALE

----------------------------------------== DRCLK DMCLK

OSR

---------------------- AMCLK

4OSR

--------------------- MCLK

4 OSR PRESCALE

××

-----------------------------------------------------------===

MCP3911

Since this is the output data rate, and since the

decimation filter is a SINC (or notch) filter, there is a

notch in the filter transfer function at each integer

multiple of this rate.

The follow ing tab le describe s the various combination s

of OSR and PRESCALE an d thei r associa ted AM CLK,

DMCLK and DRCLK rates.

TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR , AND PRESCALE, MCLK=4MHZ

PRE

<1:0> OSR <2:0> OSR AMCLK DMCLK DRCLK DRCLK

(ksps)

SINAD

(dB)

Note 1

ENOB

from

SINAD

(bits)

Note 1

1 1 1 1 1 4096 MCLK/8 MCLK/32 MCLK/131072 0.035 98 16

1 1 1 1 1 2048 MCLK/8 MCLK/32 MCLK/65536 0.061 98 16

1 1 1 1 1 1024 MCLK/8 MCLK/32 MCLK/32768 0.122 97 15.8

1 1 1 1 1 512 MCLK/8 MCLK/32 MCLK/16384 0.244 96 15.6

1 1 0 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.488 95 15.5

1 1 0 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7

1 1 0 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5

1 1 0 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3

1 0 1 1 1 4096 MCLK/4 MCLK/16 MCLK/65536 0.061 98 16

1 0 1 1 1 2048 MCLK/4 MCLK/16 MCLK/32768 0.122 98 16

1 0 1 1 1 1024 MCLK/4 MCLK/16 MCLK/16384 0.244 97 15.8

1 0 1 1 1 512 MCLK/4 MCLK/16 MCLK/8192 0.488 96 15.6

1 0 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976 95 15.5

1 0 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7

1 0 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5

1 0 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3

0 1 1 1 1 4096 MCLK/2 MCLK/8 MCLK/32768 0.122 98 16

0 1 1 1 1 2048 MCLK/2 MCLK/8 MCLK/16384 0.244 98 16

0 1 1 1 1 1024 MCLK/2 MCLK/8 MCLK/8192 0.488 97 15.8

0 1 1 1 1 512 MCLK/2 MCLK/8 MCLK/4096 0.976 96 15.6

0 1 0 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95 95 15.5

0 1 0 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7

0 1 0 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5

0 1 0 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3

0 0 1 1 1 4096 MCLK MCLK/4 MCLK/16384 0.244 98 16

0 0 1 1 0 2048 MCLK MCLK/4 MCLK/8192 0.488 98 16

0 0 1 0 1 1024 MCLK MCLK/4 MCLK/4096 0.976 97 15.8

0 0 1 0 0 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6

0 0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9 95 15.5

0 0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7

0 0 0 0 1 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5

0 0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3

Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD

values are given from GAIN = 1.

MCP3911

4.5 OSR - Oversampling Ratio

This is the ratio of the sampling frequency to the output

data rate. OSR= DMCLK/DRCLK. The default OSR is

256, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK

= 4 MHz, fS = 1 MHz, fD = 3.90625 ksps. The followin g

bits in the CONFIG register are used to change the

oversampling ratio (OSR).

4.6 Offset Error

This is the error induced by the ADC when the inputs

are shorted together (VIN = 0V). The specification

incorporates both PGA and ADC offset contributions.

This error varies with PGA and OSR settings. The

offs et is dif fere nt on ea ch channel and varie s from chi p

to chip. The offset is specified in µV. The offset error

can be digitally compensated independently on each

channel through the OFFCAL registers with a 24-bit

calibration word.

The offset on the MCP3911 has a low temperature

coefficient, see typical performance curves for more

information, Figure 2-33.

4.7 Gain Error

This is the er ror induced by the AD C on the slope of th e

transfer function. It is the deviation expressed in %

compared to the ideal transfer function defined by

Equation 5-3. Th e sp ec ific at ion incorpor ate s both PG A

and ADC gain error contributions, but not the VREF

contribution (it is measured with an external VREF).

This error v aries wi th PGA and OSR settings . The gai n

error can be digitally compensated independently on

each channel through the GAINCAL registers with a

24-bit calibratio n word.

The gain error on the MCP3911 has a low temperature

coefficient; for more information, see Figure 2-34.

4.8 Integral Non-Linearity Error

Integral non-linearity error is the maximum deviation of

an ADC transition point from the corresponding point of

an ideal transfer function, with the offset and gain

errors removed, or with the end points equal to zero.

It is the maximum remaining error after calibration of

offset and gain errors for a DC input signal.

4.9 Signal-To-Noise Ratio (SNR)

For the MCP3911 ADCs, the signal-to-noise ratio is a

ratio of the output fundamental signal power to the

noise p ower (not inclu ding the harmo nics of the sig nal),

when the input is a sinewave at a predetermined

frequency. It is measured in dB. Usually, only the

maximum signal to noise ratio is specified. The SNR

figure depends mainly on the OSR and DITHER

settings of the device.

EQUATION 4-3: SIGNAL-TO-NOISE RATIO

4.10 Signal-To-Noise Ratio And

Distortion (SINAD)

The most important figure of merit for the analog

performance of the ADCs present on the MCP3911 is

the Signal-to-Noise And Distortion (SINAD)

specification.

Signal-to-noise and distortion ratio is similar to signal-

to-noise ratio, with the exception that you must include

the harmonics power in the noise power calculation.

The SINAD specification depends mainly on the OSR

and DITHER settings.

EQUATION 4-4: SINAD EQUATION

The calculated combination of SNR and THD per the

following formula also yields SINAD:

EQUATION 4-5: SINAD, THD, AND SNR

RELATIONSHIP

TABLE 4-3: MCP3911 OVERSAMPLING

RATIO SETTINGS

CONFIG OVER SAMPLING

RATIO

OSR

OSR<2:0>

000 32

001 64

010 128

0 1 1 256 (DEFAULT)

100 512

1 0 1 1024

1 1 0 2048

1 1 1 4096

SNR dB() 10 SignalPower

NoisePower

----------------------------------

⎝⎠

⎛⎞

log=

SINAD dB() 10 SignalPower

Noise HarmonicsPower+

--------------------------------------------------------------------

⎝⎠

⎛⎞

log=

SINAD dB() 10 10

SNR

-----------

⎝⎠

⎛⎞

THD–10

----------------

⎝⎠

⎛⎞

+log=

MCP3911

4.11 Total Harmonic Distortion (THD)

The total harmonic distortion is the ratio of the output

harmoni cs power to the funda menta l signal p ower for a

sinewave input and is defined by the following

equation.

EQUATION 4-6:

The THD calculation includes the first 35 harmonics for

the MCP3911 specifications. The THD is usually only

measured with respect to the 10 first harmonics. THD

is sometimes expressed in %. For converting the THD

in %, here is the formula:

EQUATION 4-7:

This specification depends mainly on the DITHER set-

ting.

4.12 Spurious-Free Dynamic Range

(SFDR)

The ratio between the output power of the fundamental

and the highest spur in the frequency spectrum. The

spur frequency is not necessarily a harmonic of the

fundamental even though it is usually the case. This

figure represents the dynamic range of the ADC when

a full- scale sig nal is us ed at the input. Th is specific ation

depends mainly on the DITHER setting.

EQUATION 4-8:

4.13 MCP3911 Delta- Sigma

Architecture

The MCP3911 incorporates two Delta-Sigma ADCs

with a mul ti-b it arc hitec ture . A De lta-Si gma A DC is an

oversampling converter that incorporates a built-in

modulator which is digitizing the quantity of charge

integrated by the modulator loop (see Figure 5-1). The

quantizer is the block that is performing the

analog-to-digital conversion. The quantizer is typically

1-bit, or a simple comparator which helps to maintain

the linearity performance of the ADC (the DAC

structure is, in this case, inherently linear).

Multi-b it qua nti zer s help to lower the qua nti zat ion error

(the error fed back in the loop can be very large with

1-bit quantizers) without changing the order of the

modulator or the OSR which leads to better SNR

figures. However, typically, the linearity of such

archi tec tur es is m ore difficult to achieve s in ce the DAC

is no more simple to realize and its linearity limits the

THD of such ADCs.

The MCP3911’s 5-level quantizer is a flash ADC

composed of four comparators arranged with equally

spaced thresholds and a thermometer coding. The

MCP3911 also includes proprietary 5-level DAC

architecture that is inherently linear for improved THD

figures.

4.14 Idle Tones

A Delta-Sigma converter is an integrating converter. It

also has a fi nite quantization step (LSB) which can be

detected by its quantizer. A DC input voltage that is

below the quantization step should only provide an all

zeros result since the input is not large enough to be

detected. As an integrating device, any Delta-Sigma

will show in this case idle tones. This means that the

output will hav e spurs in the fre quenc y cont ent that a re

depending on the ratio between quantization step

voltage and the input voltage. These spurs are the

result of the integrated sub-quantization step inputs

that will eventually cross the quantization steps after a

long enough integration. This will induce an AC

frequency at the output of the ADC and can be shown

in the ADC output spectrum.

These idle tones are residues that are inherent to the

quantization process and the fact that the converter is

integrating at all times without being reset. They are

residues of the finite resolution of the conversion

process. They are very difficult to attenuate and they

are heavily signal dependent. They can degrade both

SFDR and THD of the converter, even for DC inputs.

They can be loc alized in the baseb and of the convert er

and thus difficult to filter from the actual input signal.

For pow er metering a pplications , idle tones can be very

disturbi ng becau se ene rgy can be detected even at th e

50 or 60 Hz frequency, depending on the DC offset of

the ADCs, while no power is really present at the

inputs. The o nly p r ac tical way to suppres s or a tten ua te

idle tones phenomenon is to apply dithering to the

ADC. The idle tones amplitudes are a function of the

order of the modulator, the OSR and the number of

levels in the qu antize r of the mo dulato r. A highe r order,

a higher OSR or a higher number of levels for the

quantizer will attenuate the idle tones amplitude.

THD dB() 10 HarmonicsPower

FundamentalPower

-----------------------------------------------------

⎝⎠

⎛⎞

log=

THD %() 100 10THD dB()

------------------------

SFDR dB() 10 FundamentalPower

HighestSpurPower

-----------------------------------------------------

⎝⎠

⎛⎞

log=

MCP3911

4.15 Dithering

In order to suppress, or attenuate, the idle tones pres-

ent in any De lta -Sigma ADC s, ditheri ng can be app lied

to the ADC. Dithering is the process of adding an error

to the ADC feedback loop in order to “decorrelate” the

outputs and “break” the idle tones behavior. Usually a

random or pseudo-random generator adds an analog

or digital error to the feedback loop of the Delta-Sigma

ADC in order to ensure that no tonal behavior can

happen at it s outputs. This error is filter by the feedback

loop and typica ll y ha s a z ero averag e va lue so that the

convert er static trans fer function is not disturbed by the

dithering process. However, the dithering process

slightly increases the noise floor (it adds noise to the

part) while reducing its tonal behavior and thus

improving SFDR and THD. (See Figure 2-14 and

Figure 2-18). The dithering process scrambles the idle

tones into baseband white noise and ensures that

dynamic specs (SNR, SINAD, THD, SFDR) are less

signal dependent. The MCP3911 incorporates a

propriet ary dithering al gorithm on both ADCs in order to

remove idle tones and improve THD, which is crucial

for power metering applications.

4.16 Crosstalk

The crosstalk is defined as the perturbation caused by

one ADC channel on the other ADC channel. It is a

measurement of the isolation between the two ADCs

present in the chip.

This measurement is a two-step procedure:

1. Measur e on e AD C i npu t w it h no pe rturb ati on o n

the other ADC (ADC inputs shorted).

2. Measure the same ADC input with a

perturbation sine wave signal on the other ADC

at a certain predefined frequency.

The crosstalk is then the ratio between the output

power of the ADC wh en the pe rturbation is present an d

when it is not divided by the power of the perturbation

signal.

A lower crosstalk value implies more independence

and isolation between the two channels.

The meas urement of this signal is perform ed under the

default conditio ns at MCLK = 4 MHz:

•GAIN = 1,

• PRESCALE = 1,

• OSR = 256,

• MCLK = 4 MHz

Step 1

• CH0+=CH0-=AGND

• CH1+=CH1-=AGND

Step 2

• CH0+=CH0-=AGND

• CH1+ - CH1-=1.2VP-P @ 50/60 Hz (Full-scale

sine wave)

The crosstalk is then calculated with the following

formula:

EQUATION 4-9:

4.17 PSRR

This is th e ratio betwee n a c han ge i n the pow e r sup pl y

voltage and the ADC output codes. It measures the

influence of the power supply voltage on the ADC

outputs.

The PSRR specification can be DC (the power supply

is ta king mu ltipl e DC v alues ) or AC (the power supp ly

is a sinewave at a certain frequency with a certain

common mode). In AC, the amplitude of the sinewave

is representing the change in the power supply.

It is defined as:

EQUATION 4-10:

Where VOUT is the equivalent input voltage that the

output code translates to with the ADC transfer

function. In the MCP3911 specification, AVDD varies

from 2.7V to 3.6V, and for AC PSRR a 50/60 Hz

sinewave is chosen centered around 3.3V with a

maximum 300 mV amplitude. The PSRR specification

is measured with AVDD = DVDD.

4.18 CMRR

This is the ratio between a change in the

common-mode input voltage and the ADC output

codes. It m eas ure s t he i nfl uence of the comm on-m od e

input voltage on the ADC outputs.

The CMRR specification can be DC (the

common-mode input voltage is taking multiple DC

values) or AC (the common-mode input voltage is a

sinewav e at a certa in frequenc y with a cert ain commo n

mode). In AC, the amplitude of the sinewave is

represen ting the chan ge in the pow e r suppl y.

It is defined as:

CTalk dB() 10

CH0Power

CH1Power

---------------------------------

⎝⎠

⎛⎞

log=

PSRR dB() 20

VOUT

AVDD

-------------------

⎝⎠

⎛⎞

log=

MCP3911

EQUATION 4-11:

Where VCM= (CHn+ + CHn-)/2 is the common-mode

input voltage and VOUT is the equivalent input voltage

that the out put code tran slates to wit h the ADC trans fer

function. In the MCP3911 specification, VCM varies

from -1V to +1V.

4.19 ADC Reset Mode

ADC Reset mode (called also soft reset mode) can only

be entered through setting high th e RESET<1:0> bits in

the configuration register. This mode is defined as the

condition where the converters are active but their

output is forced to 0.

The registers are not affected in this reset mode and

retai n their exce pt the dat a registers of the correspon d-

ing channel which are reset to 0.

The ADCs can immediately output meaningful codes

after l eaving reset mode (and after the sinc filter settling

time). This mode is both entered and exited through

setting of bits in the configuration register.

Each converter can be placed in soft reset mode

independently. The configuration registers are not

modified by the soft reset mode.

A data ready pulse will not be generated by any ADC

while in reset mode.

Reset mode also effects the modulator output block,

i.e., the MDAT pin, corresponding to the channel in

reset. If enabled, it provides a bitstream corresponding

to a zero output (a series of 0011 bits continuously

repeated).

When an ADC exits ADC reset mode, any phase delay

present be fore reset was entered will sti ll be prese nt. If

one ADC was not in reset, the ADC leaving reset mode

will resynchronize automatically the phase delay

relative to the other ADC channel per the phase delay

If an ADC is placed in Reset mode while the other is

converting, it is not shutting down the internal clock.

When go ing ba ck o ut of reset, it will be res yn ch ronized

automatically with the clock that did not stop during

reset.

If both ADCs a re in so ft re set th e clo ck i s no longer dis-

tributed to the digital core for low power operation.

Once any of the ADC is back to normal operation, the

clock is automatically distributed again.

However, when the two channels are in soft reset, the

input structure is still clocking if MCLK is applied in

order to bias properly the inpu ts so that no leaka ge cur-

rent is observed. If MCLK is not applied, large analog

input lea ka ge c urre nt s ca n be obs erv ed fo r hig hl y ne g-

ative input voltages (typically below -0.6V referred to

AGND).

4.20 Hard Reset Mode (RESET = 0 )

This mode is only available during a POR or when the

RESET pin is pulled low. The RESET pin low state

places the device in a hard reset mode.

In this mode all internal registers are reset to their

default state.

The DC biases for the analog blocks are still active, i.e.,

the MCP3911 is ready to convert. However, this pin

clears all conversion data in the ADCs. In this mode,

the MDAT outputs are in high impedance. The

comparator’s outputs of both ADCs are forced to their

reset s tate (0 011). The SINC filters are all r eset, as well

as their double output buffers. See serial timing for

minimum pulse low time, in Section 1.0 “Electrical

Characteristics”.

During a hard reset, no communication with the part is

possible. The digital interface is maintained in a reset

state.

During this state, the clock MCLK can be applied to the

part in ord er to properly bias the input structures of both

channels. If not a pplied, large analog input leakage cur-

rents can be observed fo r hig hly ne gati ve inp ut s ign al s

and after removing the RESET state a certain start up

time is necessary to bias the input structure properly.

Durin g th i s d ela y t h e AD C co nv ers i on s c an be in ac cu -

rate.

4.21 ADC Shutdown Mode

ADC shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. When Shutdown bit is reset to 0, the

analog bia ses wi ll be enable d, as well as the clo ck and

the digi tal c ircuitry. The ADC wi ll give a data ready af ter

the SINC filter settling time has occurred. However,

since the analog biases are not completely settled at

the be gi n nin g of the co nv er s ion , t he sa mp li n g may no t

be accurate during about 1 ms (corresponding to the

settlin g ti me of the biasin g i n w o rst case conditions). In

order to guarantee the accuracy, the data ready pulse,

coming within the delay of 1 ms + settling time of the

SINC filter, should be discarded.

Each converter can be placed in shutdown mode

indepen dently. The C ON FIG re gi ste rs are not modi fie d

by the shutdown mode. This mode is only available

through programming of the SHUTDOWN<1:0> bits

the CONFIG register.

The output data is flushed to all zeros while in ADC

shutdown. No data ready pulses are generated by any

ADC while in ADC shutdown mode.

CMRR dB() 20

VOUT

VCM

-----------------

⎝⎠

⎛⎞

log=

MCP3911

ADC shut d own mod e also e ffe ct s the modul ator outp ut

block, i.e., if MDAT of the cha nnel in shut dow n mode i s

enabled , this pi n will provide a bits tream co rrespondin g

to a zero output (series of 0011 bits continuously

repeated).

When an ADC exits ADC shutdown mode, any phase

delay present b efore shutdown w as e nte red w ill s til l b e

present. If one ADC was not in shutdown, the ADC

leaving shutdown mode will automatically

resynchronize the phase delay, relative to the other

ADC channel, per the phase delay register block and

give data ready pulses accordingly.

If an ADC is placed in shutdown mode while the other

is converting, it is not shutting down the internal clock.

When going back out of shutdown, it will be

resync hronized auto matically with t he clock that di d not

stop during reset.

If both ADCs are AD C shut down modes, the cl ock is no

more distributed to the digital core for low power oper-

ation. The clock is no more distributed to the input

structure too. This can cause potential high analog

input leakage currents at the analog inputs if the input

voltage is highly negative (typically below -0.6V,

referred to AGND). Once any of the ADC is back to nor-

mal operation, the clock is automatically distributed

again.

4.22 Full Shut down Mode

The lowest power consumption can be achieved when

SHUTDOWN<1:0>=11, VREFEXT=CLKEXT=1. This

mode is called “Full shutdown mode”, and no analog

circuit ry is en abled . In this mode, b oth AVDD and DVDD

POR monitoring are also disabled. No clock is propa-

gated thro ughout the ch ip. Both ADCs are in shu tdown,

and the internal voltage reference is disabled.

The clock is no more distributed to the input structure

too. This can cause potential high analog inputs leak-

age currents at the analog inputs if the input voltage is

highly negative (typically below -0.6V, referred to

AGND).

The only circuit that remains active is the SPI interface

but this circuit does not induce any static power

consumption. If SCK is idle, the only current

consum ption co mes f rom the le akage cu rrent s induce d

by the transistors and is less than 1 µA on each power

supply.

This mode can be used to power down the chip

completely and avoid power consumption when there

is no data to convert at the analog inputs. Any SCK or

MCLK edge coming while in this mode will induce

dynamic power consumption.

Once any of the SHUTDOWN, CLKEXT and V REFEXT

bits return to 0, the two POR monitoring blocks are

back to operation and AVDD and DVDD moni tor i ng c an

take place.

When exiting full Shutdown mode, the device resets to

its default configuration state. The Configuration bits all

reset to their default value, and the ADCs reset to their

initial state, requiring 3 DRCLK periods for an initial

data ready pulse. Exiting full Shutdown mode is effec-

tively identical to an internal reset or returning from a

POR condition.

MCP3911

NOTES:

MCP3911

5.0 DEVICE OVERVIEW

5.1 Analog Inputs (CHn+/-)

The MC P3911 analog in puts can b e conn ected d irectl y

to current and voltage transducers (such as shunts,

current transformers, or Rogowski coils). Each input

pin is protected by specialized ESD structures that are

certified to pass 4.0 kV HBM and 200V MM contact

charge. These structu r es al low bi pol ar ±2 V con tin uou s

voltage with respect to AGND, to be present at their

inputs without the risk of perma nen t dam age.

Both channels have fully differential voltage inputs for

better no ise performance. The absolute volt age at each

pin, relati ve t o AGND, s hould be maint ain ed in the ± 1V

range du ring operati on, in orde r to ensure the spec ified

ADC accuracy. The common-mode signals should be

adapted to respect both the previous conditions and

the differential input voltage range. For best

performance, the common-mode signals should be

maintained to AGND.

5.2 Programmable Gain Amplifiers

(PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each Delta-Sigma ADC. They have

two functions: translate the common-mode of the input

from AGND to an internal level between AGND and

AVDD, and amplify the input differential signal. The

tran slation o f the comm on mode doe s not chan ge the

differential signal but recenters the common-mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded. The PGA is

controll ed by the PGA_ CHn<2 :0> bit s in the GAIN reg-

ister. The following table represents the gain settings

for the PGA:

5.3 Delta-Sigma Modulator

5.3.1 ARCHITECTURE

Both ADCs are identical in the MCP3911, and they

include a proprietary second-order modulator with a

multi-bi t 5-level DAC ar chitecture (s ee Figure 5-1). The

quantizer is a flash ADC composed of four compara-

tors, with equally spaced thresholds, and a thermome-

ter output coding. The proprietary 5-level architecture

ensures minimum quantization noise at the outputs of

the modulators without disturbing linearity or inducing

additional distortion. The sampling frequency is

DMCLK (typically 1 MHz with MCLK=4 MHz) so the

modula tor outpu ts a re ref reshed at a DMCLK rat e. The

modulator outputs are available in the MOD register or

serially transferred on each MDAT pin.

Figure 5-1 represent s a s im pl ifie d bl oc k d iag ram of th e

Delta-Sigma ADC present on MCP3911.

FIGURE 5-1: Simplified Delta-Sigma ADC

Block D iagram.

5.3.2 MODULATOR INPUT RANGE AND

SATURATION POINT

For a specified voltage reference value of 1.2V, the

modulators specified differential input range is

±600 mV. The input range is proportional to VREF and

scales according to the VREF voltage. This range is

guaranteeing the stability of the modulator over

amplitude and frequency. Outside of this range, the

Note: If the analog inputs are held to a potential

of -0.6 to -1V, for extended p eriods of time,

the clock MCLK must be present inside

the devi ce in ord er to avoid large lea kage

currents at the analog inputs. This is true

even during the hard reset mode or the

soft res et of bot h ADCs. How ever dur ing

shutdo wn mode of th e two ADCs or POR

stat e, the clo ck is no t distribu ted insid e the

circuit. During these states, it is recom-

mended to k eep the a nalog input v oltages

above -0.6V referred to AGND, to avoid

high analog inputs leakage currents.

TABLE 5-1: PGA CONFIGURATION

SETTING

Gain

PGA_CHn<2:0> Gain

(V/V) Gain

(dB) VIN Range

(V)

000 1 0±0.6

001 2 6±0.3

010 4 12±0.15

0 1 1 8 18 ±0.075

1 0 0 16 24 ±0.0375

1 0 1 32 30 ±0.01875

Note: The 2 u ndefined settings a r e G= 1 ; t his table

is defined with VREF = 1.2V.

Second-

Order

Integrator

Loop

Filter Quantizer

DAC

Differential

Voltage Input Output

Bitstream

5-level

Flash AD C

MCP3911 Delta-Sigma Modulator

MCP3911

modulator is still functional, however its stability is no

longer gu aranteed and therefore it is not recommended

to exceed this limit (see FIGURE 2-24: “SINAD vs.

Input Signal Am plitude.” for extend ed dynamic range

performance limitations). The saturation point for the

modula tor is VREF/1.5 si nc e t he transfer fu nc tio n o f th e

ADC includes a gain of 1.5 by default (independent

from the PGA setting. See Section 5.6 “ADC Output

Coding”).

5.3.3 BOOST SETTINGS

The Delta-Sigma modulators include a programmable

biasing circuit in order to further adjust the power con-

sumption to the sampling speed applied through the

MCLK. This can be programmed through the

BOOST<1:0> bits which are applied to both channels

simultaneously.

The maximum achievable analog master clock speed

(AMCLK) and the maximum sampling frequency

(DMCLK), and th erefore the m aximum achiev able dat a

rate (DRCLK), highly depend on BOOST<1:0> and

PGA_CHn<2:0> settings. The following table specifies

the maximum AMCLK possible to keep optimal accu-

racy in function of BOOST<1:0> and PGA_CHn<2:0>

settings.

TABLE 5-2: MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN

Conditions VDD = 3.0V to 3. 6V, TA from -40°C to 125°C VDD = 2.7V to 3.6V, TA from -40°C to 125°C

Boost Gain Maximum AMCLK

(MHz) (SINAD within

-3 dB from its

maximum)

Maximum AMCLK

(MHz) (SINAD

within -5 dB from its

maximum)

Maximum AMCLK

(MHz) (SINAD

within -3 dB from

its maximum)

Maximum AMCLK

(MHz) (SINAD within -

5 dB from its

maximum)

0.5x 1 3 3 3 3

0.66x 1 4 4 4 4

1x 1 10 10 10 10

2x 1 16 16 16 16

0.5x 2 2.5 3 3 3

0.66x 2 4 4 4 4

1x 2 10 10 10 10

2x 2 14.5 16 13.3 14.5

0.5x 4 2.5 2.5 2.5 2.5

0.66x 4 4 4 4 4

1x 4 10 10 8 10

2x 4 13.3 16 10.7 11.4

0.5x 8 2.5 2.5 2.5 2.5

0.66x 8 4 4 4 4

1x 8 10 11.4 6.7 8

2x 8 10 14.5 8 8

0.5x 16 2 2 2 2

0.66x 16 4 4 4 4

1x 16 10.6 10.6 8 10

2x 16 12.3 16 8 10.7

0.5x 32 2 2 2 2

0.66x 32 4 4 4 4

1x 32 10 11.4 8 10

2x 32 13.3 16 8 10

MCP3911

5.3.4 AUTOZEROING FREQUENCY

SETTING (AZ_FREQ)

The MCP391 1 modulators include an autozeroing algo-

rithm to improve the offset error performance and

greatly diminish 1/f noise in the ADC. This algorithm

permit s it to reac h very high SNR and fl attens th e noise

spectrum at the output of the ADC (see performance

graphs Figure 2-1, Figure 2-2, Figure 2-3 and Figure 2-

4). This autozeroing algorithm is performed synchro-

nously with the M CLK coming t o the de vice, and it s rate

can be adjusted throughout the AZ_FREQ bit in the

CONFIG register.

When AZ_FREQ=0 (default) the autozeroing is hap-

pening at the slowest rate, which diminishes the 1/f

noise whi le not impacting the THD performance. This

mode i s r e commende d fo r l ow v al u es of th e P GA ga in

(GAIN=1x or 2x).

When AZ_FREQ=1, the autozeroing is happening at

the fastest rate, which further diminishes the 1/f noise

and further improves the SNR, especially at higher gain

settings. The THD may slightly be impacted in this

mode (see Figure 2-22). This mode is recommended

for higher PGA gain settings to improve SNR (GAIN

superior or equal to 4x).

5.3.5 DITHER SETTINGS

Both mod ula tors al so inc lu de a dithering al gori thm th at

can be enabled through the DITHER<1:0> bits in the

configuration register. This dithering process improves

THD and SFDR (for high OSR settings) while

increasing slightly the noise floor of the ADCs. For

power metering applications and applications that are

distortion-sensitive, it is recommended to keep

DITHE R at ma xi mu m se ttings for best THD and SFDR

performance. In the case of power metering applica-

tions, THD and SFDR are critical specifications. Opti-

mizing SNR (noise floor) is not really problematic due

to large averaging factor at the output of the ADCs,

therefore ev en for low OSR settings , the dithering alg o-

rithm wil l show a po sitive i mp act on the pe rforman ce of

the application.

5.4 Modulator Output Block

If the user wishes to use the modulator output of the

device, the appropriate bits to enable the modulator

output must be set in the configuration register.

When MODOUT<1:0> bits are enabled, the modulator

output of the corresponding channel is present at the

corresponding MDAT output pin as soon as the

command is placed. Additionally, the corresponding

SINC filt er is dis abled in o rder to consume le ss curren t.

The corresponding DR pulse is also not present at the

DR output pin. When MODOUT<1:0> bits are cleared,

the corresponding SINC filters are back to normal op er-

ation and the corresponding MDAT outputs are in high

impedance.

Since the Delta-Sigma modulators have a 5-level out-

put given by the state of four comparators with ther-

mometer coding, their outputs can be represented on

four bits, each bit giving the state of the corresponding

comparator (See Table 5-3). The se bits are present on

the MOD register and are updated at the DMCLK rate.

In order to output the c omparators result on a s eparate

pin (MDAT0 and MDAT1), these comp arator output bit s

have be en arrange d to be serially o utput a t the AMCLK

rate (See Figure 5-2).

This 1-bit serial bitstream is the same that would be

produced by a 1-bit DAC modulator with a sampling

frequency of AMCLK. The modulator can either be

consid ered like a 5 l evel-outp ut at DMCLK rate, or 1-b it

output at AMCLK rate. These two representations are

interchangeable. The MDAT outputs can therefore be

used in any application that requires 1-bit modulator

outputs. These applications will often integrate and

filter the 1-bit output with SINC, or more complex

decimation filters computed by a MCU or a DSP.

TABLE 5-3: DELTA-SIGMA MODULATOR

CODING

Comp<3:0>

Code Modulator

Output Code MDAT S erial

Stream

1111 +2 1111

0111 +1 0111

0011 00011

0001 -1 0001

0000 -2 0000

MCP3911

FIGURE 5-2: MDAT Serial Outputs in

Function of the Modulator Output Code.

Since the reset and shutdown SPI commands are

async hron ous , the M DAT pins are re sy nc hro niz ed w i th

DMCLK after each time the part goes out of reset and

shutdown.

This means that the first output of MDAT, after a soft

reset or a shutdown, is always 0011 after the first

DMCLK rising edge.

The tw o MDAT outpu t pins are i n high imp edanc e if th e

RESET pin is low.

5.5 SINC3 + SINC1 Filter

The decimation filter present in both channels of the

MCP3911 is a cas ca de o f two s in c f ilte r s ( sin c3+sinc1):

a third order sinc filter with a decimation ratio of OSR3

followed by first order sinc filter with a decimation ratio

of OSR1 (mo v ing average of OSR1 values). Figure 5-3

represen t s the dec im ati on fil ter arch itecture.

FIGURE 5-3: MCP3911 Decimation Filter Block Diagram.

The f ormul a for calc ulati ng th e tran sfer funct ion o f the

digital decimation filter and settling time of the ADC is

as follows:

EQUATION 5-1: SINC FILTER TRANSFER FUNCTION

DMCLK

MDAT+2

MDAT+1

MDAT+0

MDAT-1

MDAT-2

COMP

AMCLK

<3> COMP

<2> COMP

<1> COMP

<0>

Modulator

Output SINC3SINC1Decimation

Filter Output

OSR3OSR1

416 (WIDTH=0)

24 (WIDTH=1)

Decimation Filter

OSR1=1

Hz() 1z- OSR3

–

⎝⎠

⎛⎞

OSR31z1–

–()()

--------------------------------------------- 1z

- OSR1OSR3

–

⎝⎠

⎛⎞

OSR11z- OSR3

–

⎝⎠

⎛⎞

-----------------------------------------------------------

×where,=

z EXP 2πjf

⋅⋅ DMCLK⁄()=

MCP3911

EQUATION 5-2: SETTING TIME OF THE ADC AS A FUNCTION OF DMCLK PERIODS

The SINC1 filter following the SINC3 filter is only

enabled for the high OSR settings. This SINC1 filter

provides additional rejection at a low cost with little

modification to the -3 dB bandwidth. For 24-Bit Output

mode (WIDTH = 1), the output of the sinc filter is pad-

ded on the right with least significant zeros, up to 24

bits , for any re solution les s than 24 bits. For 16-Bit Out-

put modes , the output of the sinc filte r is rounded to the

closest 16-bit number, in order to conserve only 16-bit

words and to minimize truncation error.

The gain o f the transfe r functio n of this filter is 1 at each

multiple of DMCLK (typically 1 MHz) so a proper anti-

aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

convert er. This anti-alia si ng fi lte r can be a sim ple , firs t-

order RC network with a sufficiently low time constant

to generate high rejection at DMCLK frequency.

Any unsettled data is automatically discarded to avoid

data corruption. Each data ready pulse corresponds to

fully settled data at the output of the decimation filter.

The first data available at the output of the decimation

filter is present af ter the comple te settling time of the fil-

ter (see Table 5-4). After the first data has been pro-

cessed, the delay between two data ready pulses is 1/

DRCLK. The data stream from input to output is

delayed by an amount equal to the settling time of the

filter (which is the group delay of the filter).

The achievable resolution, the -3 dB bandwidth and th e

settling time at the output of the decimation filter (the

output of the ADC), is dependent on the OSR of each

sinc filter and is summarized with the following table:

SettlingTime DMCLKPeriods()3OSR3

×OSR11–()OSR3

×+=

TABLE 5-4: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

OSR<2:0> OSR3OSR1TOTAL OSR RESOLUTION IN

BITS (NO MISSING

CODES)

SETTLING

TIME -3 dB BANDWIDTH

0 0 0 32 1 32 17 96/DMCLK 0.26*DRCLK

0 0 1 64 1 64 20 192/DMCLK 0.26*DRCLK

0 1 0 128 1 128 23 384/DMCLK 0.26*DRCLK

0 1 1 256 1 256 24 768/DMCLK 0.26*DRCLK

1 0 0 512 1 512 24 1536/DMCLK 0.26*DRCLK

1 0 1 512 2 1024 24 2048/DMCLK 0.37*DRCLK

1 1 0 512 4 2048 24 3072/DMCLK 0.42*DRCLK

1 1 1 512 8 4096 24 5120/DMCLK 0.43*DRCLK

MCP3911

FIGURE 5-4: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE<1:0> = 00.

FIGURE 5-5: SINC Filter Frequency Response, OSR = 4096 (pink), OSR = 512 (blue), MCLK = 4

MHz, PRE<1:0> = 00.

MCP3911

5.6 ADC Output Coding

The s econd o rder m odulator, SINC3+SINC1 filt er , PGA,

VREF and analog input structure, all work together to

produce the device transfer function for the analog to

digita l conversion, Equation 5-3.

The channel data is either a 16-bit or 24-bit word,

presented in 23-bit or 15-bit plus sign, two’s

comple me nt form at and is MSB (lef t) just ifie d.

The ADC dat a is tw o or three byt es wide dep endin g on

the WIDTH bit of the associated channel. The 16-bit

mode includes a round to the closest 16-bit word

(instead of truncation), in order to improve the accuracy

of the ADC data.

In case of positive saturation (CHn+ - CHn- > VREF/

1.5), the output is locked to 7FFFFF for 24 bit mode

(7FFF for 16 bit mode). In case of negative saturation

(CHn+ - CHn- <-VREF/1.5), t he ou tput c ode is l ocked to

800000 for 24-bit mode (8000 for 16 bit mode).

Equation 5-3 is only true for DC inputs. For AC inputs,

this transfer function needs to be multiplied by the

transfer function of the SINC3+SINC1 filter (see

Equation 5-1 and Equation 5-3).

EQUATION 5-3:

The ADC resolution is a function of the OSR

(Section 5.5 “SINC3 + SINC1 Filter”). The resolution

is the same for both ch annels. No mat ter what the res-

olution is, the ADC output data is always presented in

24-bit w ords, with a dded zeros at the end , if the OSR i s

not large enough to produce 24-bit resolution (left

justification).

DATA_CHn CHn+ CHn-

–()

VREF+ VREF-

–

-------------------------------------

⎝⎠

⎛⎞

8,388,608 G 1.5

×××

DATA_CHn CHn+ CHn-

–()

VREF+ VREF-

–

-------------------------------------

⎝⎠

⎛⎞

32 768,G1.5

×××

(For 24-bit Mode Or WIDTH = 1)

(For 16-bit Mode Or WIDTH = 0)

TABLE 5-5: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES

ADC Output Code (MSB First) Hexadecimal Decimal, 24-bit

Resolution

0111 1111 1111 1111 111 1 1111 0x7FFFFF + 8,388,607

0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606

0000 0000 0000 0000 000 0 0000 0x000000 0

1111 1111 1111 1111 1111 1111 0xFFFFFF -1

1000 0000 0000 0000 000 0 0001 0x800001 - 8,388,607

1000 0000 0000 0000 000 0 0000 0x800000 - 8,388,608

TABLE 5-6: OSR = 128 OUTPUT CODE EXAMPLES

ADC Output Code (MSB First) Hexadecimal Decimal

23-bit Resolution

0111 1111 1111 1111 1111 1110 0x7FFFFE + 4,194,303

0111 1111 1111 1110 1111 1100 0x7FFFFC + 4,194,302

0000 0000 0000 0000 0000 0000 0x000000 0

1111 1111 1111 1111 1111 1110 0xFFFFFE -1

1000 0000 0000 0000 0000 0010 0x800002 - 4,194,303

1000 0000 0000 0000 0000 0000 0x800000 - 4,194,304

MCP3911

5.7 Voltage Reference

5.7.1 INTERNAL VOLTAGE REFERENCE

The MCP3911 contains an internal voltage reference

source specially designed to minimize drift over

temperature. In order to enable the internal voltage

reference, the VREFEXT bit in the configuration

VREF supplies refere nc e v oltage to both channels. The

typica l val ue o f th is vol t age referenc e is 1.2V ±2%. The

internal reference has a very low typical temperature

coefficient of ±7 ppm/°C, allowing the output to have

minimal variation with respect to temperature since

they are proportional to (1/VREF).

The noise of the internal voltage reference is low

enough not to significantly degrade the SNR of the

ADC if compared to a precision external low-noise

voltage reference. The output pin for the internal volt-

age reference is REFIN+/OUT.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not nece ssary for keeping ADC accuracy , but a minimal

0.1 µF ceram ic cap ac ita nce ca n be conn ect ed to avoi d

EMI/EMC s uscep tibili ty issu es, due t o the antenna cre-

ated by the REFIN+/OUT pin if left floating.

The bypass capacitors also help applications where the

voltage reference output is connected to other circuits.

In this ca se, additio nal buf feri ng may be neede d as the

output drive capability o f this output is low.

Adding too much capacitance on the REFIN+/OUT pin

may slightly degrade the THD performance of the

ADCs.

5.7.2 DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS

When the VREFEXT bit is high, the two reference pins

(REFIN+/OUT, REFIN-) become a differential voltage

reference input. The inte rnal volta ge reference ci rcuit is

placed into shutdown and the switch connecting this

circuit to the reference voltage input of the ADC is

opened. Th e internal v oltage referenc e circuit is pla ced

into shutdown and the switch connecting this circuit to

the reference voltage input of the ADC is opened. The

voltage at the REFIN+/OUT is noted VREF+ and the

volt age at the REFIN- pin is noted VREF-. The differen-

tial voltage input value is given by the following equa-

tion:

EQUATION 5-4:

The specified VREF range is from 1.1V to 1.3V. The

REFIN- pin voltage (VREF-) should be limited to ±0.1V,

with resp ect to AGND. Typical ly, for sin gle-ended ref er-

ence applications, the REFIN- pin should be directly

connected to AGND, with its own separate track to

avoid any spike due to switching noise.

TABLE 5-7: OSR = 64 OUTPUT CODE EXAMPLES

ADC Output code (MSB First) Hexadecimal Decimal

20-bit resolution

0111 1111 1111 1111 1111 0000 0x7FFFF0 + 524, 287

0111 1111 1111 1111 1110 0000 0x7FFFE0 + 524, 286

0000 0000 0000 0000 0000 0000 0x000000 0

1111 1111 1111 1111 1111 0000 0xFFFFF0 -1

1000 0000 0000 0000 0001 0000 0x800010 - 524, 287

1000 0000 0000 0000 0000 0000 0x800000 - 524, 288

TABLE 5-8: OSR = 32 OUTPUT CODE EXAMPLES

ADC Output code (MSB First) Hexadecimal Decimal

17-bit resolution

0111 1111 1111 1111 1000 0000 0x7FFF80 + 65, 535

0111 1111 1111 1111 0000 0000 0x7FFF00 + 65, 534

0000 0000 0000 0000 0000 0000 0x000000 0

1111 1111 1111 1111 1000 0000 0xFFFF80 -1

1000 0000 0000 0000 1000 0000 0x800080 - 65, 535

1000 0000 0000 0000 0000 0000 0x800000 - 65, 536

VREF=VREF+ - VREF-

MCP3911

5.7.3 TEMPERATURE COMPENSATION

(VREFCAL REGISTER)

The internal voltage reference comprises a proprietary cir-

cuit and algorithm to compen sate first order and second

order temperature coefficients. The compensation allows

very low temperature coefficients (typically 7 ppm/°C) on

the entire range of temperatures from -40°C to 125°C.

This temperature coefficient varies from part to part.

This temperature coefficient can be adjusted on each

part through the VREFCAL register (address 0x1A).

This register is only for advanced users. This register

should not be written unless the us er want s to calibra te

the temperature coefficient of the whole system or

application. The default value of this register is set to

0x42. The typical variation of the temperature coeffi-

cient of the internal voltage reference, with respect to

VREF CAL r egist er code, is gi ven by Figure 5-6. Modi-

fying the value stored in the VREFCAL register may

also vary the output voltage, in addition to the

temperature coefficien t.

FIGURE 5-6: VREF Tempco vs. VR EFCAL

Trimcode Chart.

5.8 Power-on Reset

The MCP3911 contains an internal POR circuit that

monitors both analo g and digi tal su pply volt ages during

operation. The typical threshold for a power-up event

detectio n is 2.1 V ±5% and a typical start-up time (tPOR)

of 50 µs. The POR circuit has a built-in hysteresis for

improved transient spikes immunity that has a typical

value of 200 mV. Prope r decoup ling cap aci tors (0.1 µ F

ceramic and 10 µF tantalum) should be mounted as

close as possible to the A VDD and DVDD pins, pro viding

additional transient immunity.

Figure 5-7 illustrates the different conditions at

power-up and a power-down event in typical

conditi ons. All internal DC bias es are not settled until at

least 1 m s, i n worst c ase con ditions, af ter sy stem PO R.

Any data ready pulse that occurs within 1 ms, plus the

sinc filter settling time after system reset, should be

ignored to guarant ee pr oper accura cy. After POR, dat a

ready pulses are present at the pin with all the default

conditions in the configuration registers.

Both AVDD and DVDD are monitored so either power

supply can sequence first.

FIGURE 5-7: Power-on Reset Operation.

0 64 128 192 256

VREF Drift (ppm)

VREFCAL Register Trim Code (decimal)

POR

State Power-Up Normal Operation POR

State

Biases are

unsettled.

Conversions

started here may

not be accurate.

Biases are settled .

Conversions started

here are accurate.

Analog biases

settling ti me SINC filter

settling

time

Any data read pulse occuring during this

time can yield inaccurate output data. It is

recommended to discard them.

Voltage

(AVDD, DVDD)

Time

POR Threshold

up (2.1V typ.)

(1.9V typ.) tPOR

MCP3911

5.9 RESET Effect On Delta-Sigma

Modulator/SINC Filter

When the RESET pin is logic low, both ADCs will be in

Reset and output code 0x0000h. The RESET pin per-

forms a hard reset (DC biases still on, part ready to

convert) and clears all charges contained in the Delta-

Sigma modulators. The comparator’s output is 0011

for each ADC.

The SINC filters are all reset, as well as their double

output buffers. This pin is independent of the serial

interface. It brings all the registers to the default state.

When RESET is logic low, any write with the SPI

interface, will be disabled and will have no effect. All

output pins (SDO, DR, MDAT0/1) are high impedance.

If MCLK is app lied, the input struct ure is enabled and is

properly biasing the substrate of the input transistors.

In this case , the leakage current o n the a nalog inp uts i s

low, if the analog inputs are between -1V and +1V.

If MCLK is not applied, when in reset mode, the leak-

age can be high if the analog inputs are below -0.6V,

referred to AGND.

5.10 Phase Delay Block

The MCP3911 incorporates a phase delay generator,

which ensures that the two ADCs are converting the

inputs with a f ix ed d el ay between the m. The tw o AD Cs

are synchronously sampling but the averaging of

modulator outputs is delayed, so that the SINC filter

outputs (thus the ADC outputs), show a fixed phase

delay, as determined by the PHASE register’s setting.

The phase value (PHASE<11:0>) is a 11 bit + sign,

MSB first, two's complement code that indicates how

much phase delay there is to be between Channel 0

and Cha nnel 1. The four MSB of the fi rst phase register

(address 0x07) are undefined and set to 0. The refer-

ence channel for the delay is Channel 1 (typically the

voltage channel for power metering applications).

When PHASE<11:0> is positive, Channel 0 is lagging

versus Channel 1. When PHASE<11:0> is negative,

Channel 0 is leading versus Channel 1. The amount of

delay between two ADC conversions is shown in the

following formula.

EQUATION 5-5:

The timing resolution of the phase delay is 1/DMCLK,

or 1 µs in the default co nfiguration w ith MCLK = 4 MHz.

The data ready signa ls are af fect ed by the pha se de lay

settings. T ypically, the time difference between the data

ready pu lses of channel 0 and channel 1, is equal to the

phase delay setting.

5.10.1 PHASE DELAY LIMITS

The Phase delay ca n only go f rom -OSR/2 to + OSR/2 -

1. This sets the fine phase resolution. The phase

If larger delays between the two channels are needed,

they can be im pl em ent ed ex tern all y to the chip with an

MCU. A FIFO in the MCU can s ave incomin g data from

the leading channel for a number N o f DRCLK clocks.

In this case, DRCLK would represent the coarse timing

resolution, and DMCLK the fine timing resolution. The

total delay will then be equal to:

Delay = N/DRCLK + PHASE/DMCLK

The Phase delay register can be programmed once,

with the OSR=4096 setting, and will adjust to the OSR

automatically afterwards without the need to change

the value of the PHASE register.

•OSR=4096: the delay can go from -2048 to

+2047.PHASE<11> is the sign bit. Phase<10> is

the MSB and PHASE<0> the LSB.

•OSR=2048: the delay can go from -1024 to

+1023. PHASE<10> is the sign bit. Phase<9> is

the MSB and PHASE<0> the LSB.

•OSR=1024: the delay can go from -512 to +511.

PHASE<9> is the sign bit. Phase<8> is the MSB

and PHASE<0> the LSB.

•OSR=512: the delay can go from -256 to +255.

PHASE<8> is the sign bit. Phase<7> is the MSB

and PHASE<0> the LSB.

•OSR=256: the delay can go from -128 to +127.

PHASE<7> is the sign bit. Phase<6> is the MSB

and PHASE<0> the LSB.

•OSR=128: the delay can go from -64 to +63.

PHASE<6> is the sign bit. Phase<5> is the MSB

and PHASE<0> the LSB.

•OSR=64: the delay can go from -32 to +31.

PHASE<5> is the sign bit. Phase<4> is the MSB

and PHASE<0> the LSB.

•OSR=32: the delay can go from -16 to +15.

PHASE<4> is the sign bit. Phase<3> is the MSB

and PHASE<0> the LSB.

Delay Phase Register Code

DMCLK

--------------------------------------------------=

Note: A detailed explanation of the data ready

pin (DR) with pha se delay is Figure 6-9.

Note: Re-writing the PHASE registers with the

same value resets and automatically

res tarts both ADCs.

MCP3911

5.11 Crystal Oscillator

The MC P3911 inc lud es a P ier ce- typ e cry stal o sci llat or

with very high stability and ensures very low tempco

and jitter for the clock generation. This oscillator can

handle up to 20 MHz cr ys tal frequencies , provided th at

prop er lo ad c apacita nce s an d qu artz qual ity f act or ar e

used.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND and

between OSC2 and DGND. They should also respect

the following equation:

EQUATION 5-6:

When CLKEXT= 1, th e c rys t al os ci lla tor is bypassed b y

a digita l buf fer to allow direct clock inp ut for an external

clock (see Figure 4-1).

When CLKEXT=1, it is recommended to connect

OSC2 pin to DGND directly at all times. The external

clock should not be higher than 20 MHz before pres-

caler (MCLK < 20 MHz) for proper operation.

5.12 Digital System Offset and Gain

Errors

The MCP3911 incorporates two sets of additional reg-

isters per channel, to perform system digital offset and

gain errors calibr ation. Eac h chan nel has it s ow n set of

registers ass ocia ted th at will mod ify th e out put re sult of

the channel, if the calibration is enabled. The gain and

offset calibrations can be enabled or disabled through

two configuration bits (EN_OFFCAL and

EN_GAINCAL). These two bits enable or disable sys-

tem calibration on both channels at the same time.

When both calibrations are enabled, the output of the

ADC is modified as follows:

EQUATION 5-7: DIGITAL OF FSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS

TABLE 5-9: PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 4096

Phase Register Value Hex Delay

(CH0 relative

to CH1)

011111111111 0x7FF + 2047 µs

011111111110 0x7FE + 2046 µs

000000000001 0x001 + 1 µs

000000000000 0x000 0 µs

111111111111 0xFFF - 1 µs

100000000001 0x801 - 2048 µs

100000000000 0x800 -2048 µs

RM1.6 106

fC•LOAD

------------------------

⎝⎠

⎛⎞

Where:

f = crystal frequency in MHz

CLOAD = load cap acit an ce in pF incl uding

parasitics from the PCB

RM= motional resistance in ohms of

the quartz

Note: In addition to the conditions defining the

maximum MCLK input frequency range,

the AMCLK frequency should be main-

tained inferior to the maximum limits

defined in Table 5-2 to guarantee the

accuracy of the ADCs. If these limits are

exceeded, it is recommended to either

choose a larger OSR , or a large prescal er

value, so that AMCLK can respect these

limits.

DATA_CHn post cal–()DATA_CHn pre cal–()OFFCAL_CHn+()1GAINCAL_CHn+()×=

MCP3911

5.12.1 DIGITAL OFFSET ERROR

CALIBRATION

The OFFCAL_CHn registers are 23-bit plus sign two’s

complement register, which LSB value is the same as

the Channel ADC Data. These two registers are then

added bit-by-bit to the ADC output codes, if the

EN_OFFC AL bit is enabl ed. Enabling t he EN_OFFCAL

bit does not create any pipeline delay, the offset addi-

tion is i nstant aneous. For low O SR values, only th e sig-

nificant digits are added to the output (up to the

resolution of the ADC. For example, at OSR=32, only

the 17 first bits are added).

The offset is not added when the corresponding chan-

nel is in reset or shutdown mode. The corresponding

input voltage offset value added by each LSB in these

24-bit registers is:

OFFSET(1LSB)= VREF /(PGA_CHn*1.5*8388608)

This register is a Don't Care if EN_OFFCAL=0 (Offset

calibration d isabled), but its val ue is not cleared by the

EN_OFFCAL bit.

5.12.2 DIGITAL GAIN ERROR

CALIBRATION

This register is 24-bit signed MSB first coding with a

range of -1x to +0.9999999x (from 0x80000 to

0x7FFFFF). The gain calibration adds 1x to this regis-

ter and multiplies it to the output code of the channel

bit-by-bit, after offset calibration. The range of the gain

calibration is thus from 0x to 1.9999999x (from

0x80000 to 0x7FFFF F). The LSB correspo nds to a 2-23

increment in the multiplier.

Enabling EN_GAINCAL creates a pipeline delay of 24

DMCLK periods on both channels. All data ready

pulses are delayed by 24 DMCL K periods, starting from

the data ready, following the command enabling

EN_GAINCAL bit. The gain calibration is effective on

the next data ready, following the command enabling

EN_GAINCAL bit.

The digital gain calibration does not function when the

corresponding channel is in reset or shutdown mode.

The gai n multipl ier valu e for an L SB in these 2 4-bit reg-

isters is:

GAIN (1LSB)= 1/8388608

This reg is ter is a D o n't C are i f EN_G AINC AL =0 (Off set

calibration disabled) but its value is not cleared by the

EN_GAINCAL bit.

The output dat a on each ch annel is kept to either 7FFF

or 8000 (16-bit mode) or 7FFFFF or 800000 (24-bit

mode) if the outp ut res ul t is ou t of bo und s, after all cal-

ibrations are performed.

MCP3911

6.0 SERIAL INTERFACE

DESCRIPTION

6.1 Overview

The MCP391 1 device is compatible with SPI Modes 0 ,0

and 1,1. Data is clocked out of the MCP3911 on the

falling edge of SCK and data is clocked into the

MCP3911 on the rising edge of SCK. In these modes,

SCK can Idle either high or low.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI

commu nicat ion is inde penden t. When CS is high, SDO

is in high-impedance, transitions on SCK, and SDI

have no effect. Additional controls: RESET, DR and

MDAT0/1 are also provided on separate pins for

adva nc ed co mm uni cation.

The MCP3911 interface has a simple command

structure. The first byte transmitted is always the

CONTROL byte and is followed by data bytes that are

8-bits wide. Both ADCs are continuously converting

data by default and can be reset or shut down through

a CONFIG register setting.

Since each ADC data is either 16 or 24 bits (depending

on the WIDTH bits), the internal registers can be

grouped together with various configurations (through

the READ bits) in order to allow easy data retrieval within

only one communication. For device reads, the internal

address counter can be automatically incremented in

order to loop through groups of data within the register

map. The SDO will then output the data located at the

ADDRESS (A<4:0>) defined in the control byte a nd then

ADDRESS + 1 depending on the READ<1:0> bits,

which select the groups of registers. These groups are

defined in Section 7.1 “CHANNEL REGISTERS - ADC

Channel Dat a Output Registers” (Register Map).

The Data Ready pin (DR) can be us ed as an interr upt

for an MCU and outputs pulses when a new ADC

channel data is available. The RESET pin acts like a

Hard Reset and can reset the part to its default power-

up con figuration . The MDAT0/1 pin s give the modulator

outputs (see Section 5.4 “Modulator Output Block”).

6.2 Control Byte

The control byte of the MCP3911 contains two device

Address bits, A<6:5>, 5 register Address bits, A<4:0>,

and a Read/Write bit (R/W). The first byte transmitted

to the MCP3911 is always the control byte.

The MCP391 1 interface is device addressable (through

A<6:5>) so that multiple MCP3911 chips can be pres-

ent on the same SPI bus with no data bus contention.

This functionality enables three-phase power metering

systems, containing three MCP3911 chips, controlled

by a single SPI bus (single CS, SCK, SDI and SDO

pins).

FIGURE 6-1: Control Byte.

The default device address bits are ‘00’. Contact the

Microc hip factory for addition al device address b its. For

more information, please see the Product Identif icatio n

System section.

A read on undefined addresses will give an all zeros

output on the first, and all subsequent transmitted

bytes. A write on an undefined address will have no

ef fe ct, a nd a ls o will not i nc r ement the addre ss cou nte r.

The register map is defined in Table 7-1.

6.3 Reading from the Device

The first data byte read is the one defined by the

address given in the CONTROL byte. After this first

byte is transmitted, if the CS pin is maintained low, the

communication continues and the address of the next

transmitted byte is determined by the status of the

READ bits in the STATUSCOM register. Multiple

looping configurations can be defined through the

READ<1:0> bits for the address increment (see

Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/

Write Examples”).

6.4 Writing to the Device

The first data byte written is the one defined by the

address gi ve n in the control byte. Two write mo de con-

figurations for the address increment can be defined

through the WRITE bit in the STATUSCOM register.

When WRITE = 1, the write communication automati-

cally increment s the address for subsequent bytes. The

address of the next transmitted byte within the same

communication (CS stays logic low) is the next address

defined on the register map. At the end of the register

map, the addres s loop s to the be ginni ng o f the wr it able

part of the register map (address 0x06). Writing a non-

writable register has no effect. When WRITE = 0, the

address is not incremented on the subsequent writes.

The SDO pin stays in high-impedance during a write

communication.

A6 A5 A4 A3 A2 A1 A0 R/W

Read/

Write Bit

Device Address Bits

Address

Bits

MCP3911

6.5 SPI MODE 1,1 – Clock Idle High,

Read/Write Examples

In this SPI mode, SCK idles high. For the MCP3911,

this means that there will be a falling edge on SCK

before there is a rising edge.

FIGURE 6-2: Device Read (SPI Mode 1,1 – SCK Idles High).

FIGURE 6-3: Device Write (SPI Mode 1,1 – SCK Idles High).

Note: Chang ing from an SPI Mode 1,1 to an SPI

Mode 0,0 is possible and can be done

while CS pin is logic high.

SCK

SDI

SDO

A6 A5 A4 A3 A2 A1 A0

D6 D5 D4 D3 D2 D1 D0

(ADDRESS) DATA (ADDRESS + 1) DATA

D6 D5 D4 D3 D2 D1

Data T ransitions on

the Falling Edge

MCU and MC P391 1 Latch

Bits on the Rising Edge

HI-Z HI-Z

D7 D7

R/W

HI-Z

SCK

SDI

SDO

R/W

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

(ADDRESS) DATA (ADDRESS + 1) DATA

D6 D5 D4 D3 D2 D1

Da ta Tr ansition s on

the F allin g Ed ge

MCU and MCP3911 Latch

Bits on the Rising Edge

HI-Z HI-Z

HI-Z

MCP3911

6.6 SPI MODE 0,0 – Clock Idle Low,

Read/Write Examples

In this SPI mod e, SCK idles low. For the MCP3911, this

means that there will be a rising edge on SCK before

there is a falling edge.

FIGURE 6-4: Device Read (SPI Mode 0,0 – SCK Idles Low).

FIGURE 6-5: Device Write (SPI Mode 0,0 – SCK Idles Low).

SCK

SDI

SDO

R/W

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

(ADDRESS) DATA (ADDRESS + 1) DATA

D7 D6 D5 D4 D3 D2 D1

Data T ransitions on

the Falling Edge

MCU and MCP39 1 1 Latch

Bits on the Rising Edge

D0 D7 OF (ADDRESS + 2) DATA

HI-Z HI-Z

HI-Z

SCK

SDI

SDO

R/WA6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D7

(ADDRESS) DATA (ADDRESS + 1) DATA

D6 D5 D4 D3 D2 D1 D7 OF (ADDRESS + 2) DATA

Data T ransitions on

the Falling Edge

MCU and MC P391 1 Latch

Bits on the Rising Edge

HI-Z HI-Z

HI-Z

MCP3911

6.7 Continuous Communication,

Looping on Address Sets

If the user wishes to read back either of the ADC

channels continuously, or both channels continuously,

the internal address counter of the MCP3911 can be

set to loop on specific register sets. In this case, there

is only one control byte on SDI to start the

communication. The part stays within the same loop

until CS pin re tur ns logic high.

This internal address counter allows the following

functionality:

• Read one ADC channel data continuously

• Read bo th ADC chan nels da ta co ntinuo usly (both

ADC data can be independent or linked with

DRMODE settings)

• Continuously read/write the entire register map

• Continuously read/write each separate register

• Continuously read all Configuration registers

• Write all Configuration registers in one

communication (see Figure 6-8)

6.7.1 CONTINUOUS READ

The STATUSCOM register contains the loop settings

for the internal address counter (READ<1:0> bits and

WRITE bit). The internal address counter can either

stay constant (READ<1:0> = 00) and continuously

read the same byte, or it can auto-increment and loop

through the register groups defined below (READ<1:0>

= 01), register types (READ<1:0> = 10) or the entire

Each ADC channel is configured independently as

either a 16-bit or 24-bit data word, depending on the

setting of the corresponding WIDTH bit in the

STATUSCOM register.

For continuous reading, in the case of WIDTH = 0

(16-bit), the lower byte o f the AD C data is not accesse d

and the part jumps automatically to the following

address (the user does not have to clock out the lower

byte since it becomes undefined for WIDTH = 0).

Figure 6-6 and Figure 6-7 represent a typical, continuous

read communication with the default settings

(DRMODE<1:0> = 00, READ<1:0> = 10) for both

WIDTH settings in case of the SPI Mode 0,0 (Figure 6-

6) and SPI Mode 1,1 (Figure 6-7). This configuration is

typically used for power metering applications.

Note: For c ontinuous re ading of ADC da ta in SPI

Mode 0,0 (see Figure 6-6), once the data

has been completely read after a data

ready , the SDO pin will t ake the MSB value

of the previous data at the end of the

reading (falling edge of the last SCK

clock). If SCK stays idle at logic low (by

definition of Mode 0,0), the SDO pin will be

updated at the falling edge of the next data

ready pulse (synchronously with the DR

pin falling edge with an output timing of

tDODR) with the new MSB of the data

corresponding to the data ready pulse.

This mechanism allows the MCP3911 to

continu ously use read mode seamlessly in

SPI Mode 0,0. In SPI Mode 1,1, the SDO

stays in the last state (LSB of previous

data) after a complete reading which also

allows seamless continuous read mode.

(see Figure 6-7).

MCP3911

FIGURE 6-6: Typical Continuous Read Communication (SPI Mode 0,0).

FIGURE 6-7: Typical Continuous Read Communication (SPI Mode 1,1).

CH0 ADC

ADDR/R

SCK

SDI

CH0 ADC

Upper byte

SDO CH0 ADC

Middle byte

CH0 ADC

Lower byte

CH1 ADC

Upper byte

CH1 ADC

Middle byte

CH1 ADC

Lower byte

CH0 ADC Upper byte

New ADC data

CH0 ADC

Middle byte

CH0 ADC

Lower byte

CH1 ADC

Upper byte

CH1 ADC

Middle byte

CH1 ADC

Lower byte

These bytes are not present when WIDTH=0 (16-bit mode)

HiZ CH0 ADC MSB

Old ADC data

CH0 ADC Upper byte

Old ADC data

CH0 ADC Old MSB data –Previous MSB data present on SDO until the data ready pulse updates the

SDO with the new incoming MSB dta

data

CH0 ADC

ADDR/R

SCK

SDI

CH0 ADC

Upper byte

SDO CH0 ADC

Middle byte

CH0 ADC

Lower byte

CH1 ADC

Upper byte

CH1 ADC

Middle byte CH1 ADC Lower byte CH0 ADC

Upper byte

CH0 ADC

Middle byte

CH0 ADC

Lower byte

CH1 ADC

Upper byte

CH1 ADC

Middle byte CH1 ADC Lower byte

These bytes are not present when WIDTH=0 (16-bit mode)

HiZ

MCP3911

6.7.2 CONTINUOUS WRITE

Both ADCs are powered up with their default

configurations, and begin to output data ready pulses

immediately (RESET<1:0> and SHUTDOWN<1:0>

bits are off by default).

The default output codes for both ADCs are all zeros.

The default modulator output for both ADCs is ‘0011’

(corresponding to a theoretical zero voltage at the

inputs). The default phase is zero between the two

channels.

It is recommended to enter into ADC Reset mode for

both ADCs, just after power-up, because the desired

MCP39 11 regist er conf igurati on may no t be the defau lt

one, and i n th is cas e, t he ADC wou ld o utput undesire d

data . Within the ADC Reset m ode (RESET<1:0> = 11),

the user can configure the whole part with a single

communication. The write commands automatically

increm ent the addres s so that the us er can sta rt writing

the PHASE register and finish with the CONFIG

The RESET<1:0> bits are in the last byte of the

CONFIG register to allow exiting the Soft Reset mode,

and have the whol e part configu red an d ready to run in

only one command.

6.7.3 REGISTER GROUPS AND TYPES

The following register sets are defined as groups:

The following register sets are defined as types:

6.8 Situations that Reset ADC Data

Immediately after the following actions, the ADCs are

reset and automatically restarted in order to provide

proper operation:

1. Change in PHASE register

2. Change in the OSR setting

3. Change in the PRESCALE setting

4. Overwrite of the same PHASE register value

5. Change in the CLKEXT setting

6. Change in the VREFEXT setting

7. Change in the MODOUT setting

After these temporary resets, the ADCs go back to the

normal operation, with no need for an additional

command. The PHASE regis ter ca n be used to s eria ll y

Soft Reset the ADCs, without using the RESET bits in

the Configuration register, if the same value is written

in the PHASE register.

FIGURE 6-8: Recommended Configuration Sequence at Power-up.

TABLE 6-1: REGISTER GROUPS

Group Addresses

ADC DATA CH0 0x00-0x02

ADC DATA CH1 0x03-0x05

MOD, PHASE, GAIN 0x06-0x09

CONFIG, STATUSCOM 0x0A-0x0D

OFFCAL_C H0, GAI N CAL_C H0 0x0E-0x13

OFFCAL_C H1, GAI N CAL_C H1 0x14-0x19

VREFCAL 0x1A

TABLE 6-2: REGISTER TYPES

Type Addresses

ADC DATA

(both channels) 0x00-0x05

CONFIGURATION 0x06-0x1A

00011010

SCK

SDI

, DV

11XXXXXX

CONFIG2

ADDR/W

CONFIG2

Optional RESET of both ADCs One command for writing complete configuration (without calibration)

PHASE ADDR/W GAIN STATUSCOM CONFIGPHASE

00001110 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx

MCP3911

6.9 Data Ready Pin (DR)

To signify when cha nn el dat a is re ady for tr ansmi ssio n,

the dat a ready signa l is available on the Dat a Ready pin

(DR) through an active-low pulse at the end of a

channel conversion.

The data ready pin outputs an active-low pulse with a

period that is equal to the DRCLK clock period, and

with a width equal to one DMCLK period.

When not active-low, this pin can either be in high-

impedance (when DR_HIZ = 0) or in a defined logic

high state (when DR_HIZ = 1). This is controlled

through th e STA TUSCO M register. This allows mul tiple

devices to share the same data ready pin (with a

pull-up resistor connected between DR and DVDD) in

3-phase, energy meter designs to reduce pin count. A

single device on the bus does not require a pull-up

resistor and therefore it is recommended to use

DR_HIZ = 1 configuration for such applications.

After a data ready pulse has occurred, the ADC output

data can be read through SPI communication. T wo sets

of latches at the output of the ADC prevent the

communication from outputting corrupted data (see

Section 6.10 “ADC Data Latches and Data Ready

Modes (DRMODE<1:0>)”).

The CS pin has no effect on the DR pin, which means

eve n if CS is logic high, data ready pulses will be pro-

vided (except when the configuration prevents them

from output ting data ready pulses). The DR pin can be

used as an interrupt when connected to an MCU or

DSP. While the RESET pin is logic low, the DR pin is

not active.

6.10 ADC Data Latches and Dat a Ready

Modes (DRMODE<1:0>)

To ensure that both channels’ ADC data is present at

the same time for SPI read, regardless of phase delay

settings for either or both channels, there are two sets

of ADC data latches in series with both the data ready

and the ‘read start’ triggers.

The first se t of latches hold s each output w hen the data

is ready and latches both outputs together when

DRMODE<1:0> = 00. When this mode is on, both

ADCs work together and produce one set of available

data after each data ready pulse (that corresponds to

the laggin g ADC data ready). The second set of latches

ensures that when reading sta rts on an ADC output, th e

corresponding data is latched so that no data

corruption can occur.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

completed (all bits must be read from the ADC Output

Data registers).

6.10.1 DATA READY PIN (DR) CONTROL

USING DRMODE BITS

There are four modes that control the data ready

pulses and these modes are set with the

DRMODE<1:0> bits in the STATUSCOM register. For

power metering applications, DRMODE<1:0> = 00 is

recomm end ed (D efa ult mo de).

The posi tion of t he data ready puls es vary, with respect

to this mode, to the OSR and to the PHASE settings:

•DRMODE<1:0> = 11: Both data ready puls es

from ADC Channel 0 and ADC Channel 1 are

output on the DR pin.

•DRMODE<1:0> = 10: Data ready pul ses from

ADC Channel 1 are output on th e DR pin. The

data ready pulse from ADC Channel 0 is not

present on the pin.

•DRMODE<1:0> = 01: Data ready pul ses from

ADC Channel 0 are output on th e DR pin. The

data ready pulse from ADC Channel 1 is not

present on the pin.

•DRMODE<1:0> = 00 (Recommended and

Default mode): Data ready pulses from the

lagging ADC between the two are output on the

DR pin. The lag ging ADC depend s on the PHASE

ADCs are linked together so their data is latched

together when the lagging ADC output is ready.

6.10.2 DATA READY PULSES WITH

SHUTDOWN OR RESET

CONDITIONS

There wi ll be n o da ta ready pulses if DRMODE< 1:0 > =

00 when e ither one or both of the AD Cs are in Re set or

shutdown. In Mode 0,0, a data ready pulse only hap-

pens when bot h ADCs are ready. Any data rea dy pulse

will correspond to one data on both ADCs. The two

ADCs are linked together and act as if there was only

one channel with the combined data of both ADCs.

This mode is very practical when both ADC channels’

dat a retrieval and proces sing need to be synchroni zed,

as in power metering applications.

Figure 6-9 represents the behavior of the data ready

pin with the different DRMODE configurations, while

shutdown or reset are applied.

Note: If DRMODE<1:0> = 11, the user will still

be able to retrieve the dat a ready puls e for

the ADC not in shutdown or Reset (i.e.,

only 1 ADC ch annel nee ds to be awake).

MCP3911

FIGURE 6-9: Data Ready Behavior.

D0 D1 D2

D0 D1 D2 D3 D4 D5

D3 D4 D5

D0 D1 D2 D3 D4 D5 D6 D7 D8

D1 D3 D5 D6 D7 D8 D10 D12D0 D2 D4 D9 D11 D13 D14

D6 D12

D9 D13

D16 D17 D18 D19 D21 D24D15 D20 D22 D25 D26

D7 D8 D9 D10 D11

D10 D11 D12

D10D7 D8 D9

D23

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D11D10 D12 D13 D14 D15 D16

D0 D1 D2 D4 D5D3 D7 D8 D9 D10 D11 D12 D13D6 D15 D16

D14

D0 D1 D2 D6 D10 D11 D12 D13

D11

D13 D14 D15 D16

D12 D13 D14

D14

D28 D29 D31 D33D27 D30 D32 D34

D15 D16 D17

D8D7 D9D4 D5D3

RESET<1> or

SHUTDOWN<1>

RESET<0> or

SHUTDOWN<0>

RESET

D0 D1 D2 D3 D4 D5

D0 D1 D2 D3 D4 D5 D6 D7 D8

D1 D3 D5 D6 D7 D8 D11 D13D0 D2 D4 D10 D12 D14 D15

D9 D13

D17 D18 D21 D24D16 D19 D22 D25 D26

D10 D11 D12

D10D8 D9

D23

D11 D12 D13 D14

D28 D29 D31 D33D27 D30 D32 D34

D14 D15 D16

D0 D1 D2 D3 D4 D5 D12D11 D13 D15 D16 D17D8 D9 D10

PHASE < 0 PHASE = 0 PHASE > 0

D6 D7

DRCLK Period DRCLK period

Internal reset synchronisation

(1 DMCLK period)

3*DRCLK period3*DRCLK period

D14

D9 D20

DRMODE=00; DR

DRMODE=01; DR

DRMODE=10; DR

DRMODE=11; DR

DRMODE=00; DR

DRMODE=01; DR

DRMODE=10; DR

DRMODE=11; DR

DRMODE=00; DR

DRMODE=01; DR

DRMODE=10; DR

DRMODE=11; DR

DRMODE=0 0: Select the lagging Data Ready

DRMODE=0 1: Select the Data Ready on channel 0

DRMODE=1 0: Select the Data Ready on channel 1

DRMODE=1 1: Select both Dat a ready

DRCLK Period1 DMCLK Period

Internal data ready pulse (filtered because it corresponds to unsettled data)

MCP3911

7.0 INTERNAL REGISTERS

The addresses associated with the internal registers

are listed below. A detailed description of the registers

follows. All registers are split in 8-bit long registers,

which can be addressed and read separately. Read

and Write modes define the groups and types of regis-

ters for continuous read/write communication or loop-

ing on address sets as shown in Register 7-2.

TABLE 7-1: REGISTER MAP

Address Name Bits R/W Description

0x00 CHANNEL0 24 R Channel 0 ADC 24-bit Data <23:0>, MSB first

0x03 CHANNEL1 24 R Channel 1 ADC 24-bit Data <23:0>, MSB first

0x06 MOD 8 R/W Modulator Output Register for both ADC channels

0x07 PHASE 16 R/W Pha se Delay Config uration Regist er

0x09 GAIN 8 R/W Gain and Boost Configuration Register

0x0A STATUSCOM 16 R/W Status and Communication Register

0x0 C CON FIG 16 R/W Configuration Register

0x0E OFFCAL_CH0 24 R/W Offset Correction Register - Channel 0

0x11 GAINCAL_CH0 24 R/W Gain Correction Register - Channel 0

0x14 OFFCAL_CH1 24 R/W Offset Correction Register - Channel 1

0x17 GAINCAL_CH1 24 R/W Gain Correction Register - Channel 1

0x1A VREFCAL 8 R/W Internal Voltage reference Temperature Coefficient Adjustment

MCP3911

TABLE 7-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/W RITE MODES

Function Address

READ<1:0> WRITE

= “11” = “10” = “01” = “00” = “1” = “0”

CHANNEL 0 0x00

LOOP ENTIRE REGISTER MAP

TYPE

GROUP

Static

LOOP ENTIRE

MAP

Static

0x01 Static Static

0x02 Static Static

CHANNEL 1 0x03

GROUP

Static Static

0x04 Static Static

0x05 Static Static

MOD 0x06

TYPE

GROUP

Static Static

PHASE 0x07 Static Static

0x08 Static Static

GAIN 0x09 Static Static

STATUSCOM 0x0A

GROUP

Static Static

0x0B Static Static

CONFIG 0x0C Static Static

0x0D Static Static

OFFCAL_CH0 0x0E

GROUP

Static Static

0x0F Static Static

0x10 Static Static

GAINCAL_CH0 0x11 Static Static

0x12 Static Static

0x13 Static Static

OFFCAL_CH1 0x14

GROUP

Static Static

0x15 Static Static

0x16 Static Static

GAINCAL_CH1 0x17 Static Static

0x18 Static Static

0x19 Static Static

VREFCAL 0x1A

GROUP

Static Static

MCP3911

7.1 CHANNEL REGISTERS - ADC

CHANNEL DATA OUTPUT

REGISTERS

The ADC Channel Data Output registers always con-

tain the most recent A/D conversion data for each

channel. These registers are read-only. They can be

accessed independently or linked together (with

READ<1:0> bit s). These regi sters are latche d when an

ADC read communication occurs. When a data ready

event occurs during a read communication, the most

current ADC data is also latched to avoid data corrup-

tion issues. The three bytes of each channel are

updated synchronously at a DRCLK rate. The three

bytes can be accessed separately if needed, but are

refreshed synchronously.

Name Bits Address R/W

CHANNEL0 24 0x00 R

CHANNEL1 24 0x03 R

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn

<23> (MSB) DATA_CHn

<22> DATA_CHn

<21> DATA_CHn

<20> DATA_CHn

<19> DATA_CHn

<18> DATA_CHn

<17> DATA_CHn

<16>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn

<15> DATA_CHn

<14> DATA_CHn

<13> DATA_CHn

<12> DATA_CHn

<11> DATA_CHn

<10> DATA_CHn

<9> DATA_CHn

<8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DATA_CHn

<7> DATA_CHn

<6> DATA_CHn

<5> DATA_CHn

<4> DATA_CHn

<3> DATA_CHn

<2> DATA_CHn

<1> DATA_CHn

<0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:0 DATA_CHn: Output code from ADC Channel n. This data is post-calibration if the EN_OFFCAL or

EN_GAINCAL bits are enabled.

MCP3911

7.2 MOD REGISTER - MODULATORS

OUTPUT REGISTER

The MOD register contains the most recent modulator

data output. The default value corresponds to an equiv-

alent inp ut of 0V on both ADCs. Eac h bit in this reg ister

corresponds to one comparator output on one of the

channels.

Name Bits Address Cof

MOD 8 0x06 R/W

Comparator3

Channel 1 Comparator2

Channel 1 Comparator1

Channel 1 Comparator0

Channel 1 Comparator3

Channel 0 Comparator2

Channel 0 Comparator1

Channel 0 Comparator0

Channel 0

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1

COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7:4 COMPn_CH1: Comparator Outputs from ADC Channel 1

bit 3:0 COMPn_CH0: Comparator Outputs from ADC Channel 0

MCP3911

7.3 PHASE Register - Phase

Configurati on Register

Any write to one of these two addresses (0x07 and

0x08) creates an internal reset and restart sequence.

Name Bits Address Cof

PHASE 16 0x07 R/W

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — PHASE<11> PHASE<10> PHASE<9> PHASE<8>

bit 11 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASE<7> PHASE<6> PHASE<5> PHASE<4> PHASE<3> PHASE<2> PHASE<1> PHASE<0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15:12 U nimplemen ted, read as ‘0’

bit 11:0 CH0 relative to CH1 phase delay

PHASE<11:0>: CH0 Relative to CH1 Phase Delay bits

Delay = PHASE Register’s two’s complement code/ DMCLK (Default PHASE = 0).

MCP3911

7.4 Gain - GAIN AND BOOST

CONFIGURATION REGISTER

Name Bits Address Cof

GAIN 8 0x09 R/W

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BOOST<1> BOOST<0> PGA_CH1<2> PGA_CH1<1> PGA_CH1<0> PGA_CH0<2> PGA_CH0<1> PGA_CH0<0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7:6 BOOST<1:0> Bias Current Selection

11 = Both channels have current x 2

10 = Both channels have current x 1(DEFAULT)

01 = Both channels have current x 0.66

00 = Both channels have current x 0.5

bit 5:3 PGA_CH1<2:0>: PGA Setting for Channel 1

111 = Reserved (Ga in = 1)

110 = Reserved (Gain = 1)

101 = Gain is 32

100 = Gain is 16

011 = Gain is 8

010 = Gain is 4

001 = Gain is 2

000 = Gain is 1 (DEFAULT)

bit 2:0 PGA_CH0<2:0>: PGA Setting for Channel 0

111 = Reserved (Ga in = 1)

110 = Reserved (Gain = 1)

101 = Gain is 32

100 = Gain is 16

011 = Gain is 8

010 = Gain is 4

001 = Gain is 2

000 = Gain is 1 (DEFAULT)

MCP3911

7.5 STATUS COM Register - Status

And Communication Regist er

Name Bits Address Cof

STATUSCOM 16 0x0A R/W

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

MODOUT<1> MODOUT<0> — DR_HIZ DRMODE<1> DRMODE<0> DRSTATUS<1> DRSTATUS<0>

bit 15 bit 8

R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0

READ<1> READ<0> WRITE WIDTH<1> WIDTH<0> EN_OFFCAL EN_GAINCAL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15:14 MODOUT<1:0>: Modulator Output Setting for MDAT pins

11 = Both CH0 and CH1 modulator outputs are present on MDAT1 and MDAT0 pins, both SINC fil-

ters are off, no data ready pulse is present

10 = CH1 ADC Modulator output present on MDAT1 pin, SINC filter on channel 1 is off, data ready

pulse from channel 1 is not present on DR pin

01 = CH0 ADC Modulator output present on MDAT0 pin, SINC filter on channel 0 is off, data ready

pulse from channel 0 is not present on DR pin

00 = No Modulator ou tput is enabl ed, SINC filter s are on, da ta readys are pr esent on DR pin for both

channel s (DEFAULT)

bit 13 Unimplemented, read as 0

bit 12 DR_HIZ: Data Ready Pin Inactive State Control

1 = The DR pin stat e is a logic high when data is NOT r eady

0 = The DR pin s tate is high impedance when data i s NOT r eady(DEFAULT)

bit 11:10 DRMODE<1:0>: Data Ready Pin (DR) mode configuration bits

11 = Both Data Ready pulses from CH0 and CH1 are output on DR pin

10 = Data Ready pulses from CH1 ADC are output on DR pin. Data ready pulses from CH0 are not

present on the DR pin.

01 = Data Ready pulses from CH0 ADC are output on DR pin. Data ready pulses from CH1 are not

present on the DR pin.

00 = Data Ready pulses from the lagging ADC between the two are output on DR pi n. T he l agg in g

ADC depends on the PHASE register and on the OSR. (DEFAULT)

bit 9:8 DRSTATUS<1:0>: Data Ready Status

11 = ADC Channel 1 and Channel 0 data not ready (DEFAULT)

10 = ADC Channel 1 data not ready, ADC Channel 0 data ready

01 = ADC Channel 0 data not ready, ADC Channel 1 data ready

00 = ADC Channel 1 and Channel 0 data ready

bit 7:6 READ<1:0>: Address Loop Setting

11 = Address counter incremented, cycle through entire register set

10 = Address counter loops on register types (DEFAULT)

01 = Address coun ter loops on regist er groups

00 = Address not incremented, continually read single register

bit 5 WRITE: Address Loop Setting for Write mode

1 = Address counter loops on entire register map (DEFAULT)

0 = Address not incremented, continually write same single register

MCP3911

bit 4:3 WIDTH<1:0> ADC Channel output data word width

11 = Both channels are in 24-bit mode(DEFAULT)

10 = Channel1 in 24-bit mode, Channel0 in 16-bit mode

01 = Channel1 in 16-bit mode, Channel0 in 24-bit mode

00 = Both channels are in 16-bit mode

bit 2 EN_OFFCAL Enables or disables the 24-bit digital offset calibration on both channels

1 = Enabled; this mode does not add any group delay

0 = Disabled (DEFAULT)

bit 1 EN_GAINCAL Enables or disables the 24-bit digital offset calibration on both channels

1 = Enabled; this mode adds a group delay on both channels of 24 DMCLK periods. All data ready

pulses are delayed by 24 clock periods compared to the mode with EN_GAINCAL=0

0 = Disabled(DEFAULT)

bit 0 Unimplemented, re ad as 0

MCP3911

7.6 CONFIG Register - Configuration

Name Bits Address Cof

CONFIG 16 0x0C R/W

R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0

PRE<1> PRE<0> OSR<2> OSR<1> OSR<0> DITHER<1> DITHER<0> AZ_FREQ

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 U-0

RESET<1> RESET<0> SHUT-

DOWN<1> SHUT-

DOWN<0> — VREFEXT CLKEXT —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15:14 PRE<1:0> Analog Master Clock (A MCLK) Pres caler Value

11 = AMCLK = MCLK / 8

10 = AMCLK = MCLK / 4

01 = AMCLK = MCLK / 2

00 = AMCLK = MCLK (DEFAULT)

bit 13:11 OSR<2:0> Oversampling Ratio for Delta-Sigma A/D Conversion (ALL CHANNELS, fd / fS)

111 = 4096 (fd = 244 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

110 = 2048 (fd = 488 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

101 = 1024 (fd = 976 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

100 = 512 (fd = 1.953 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

011 = 256 (fd = 3.90625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) (DEFAULT)

010 = 128 (fd = 7.8125 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

001 = 64 (fd = 15.625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

000 = 32 (fd = 31.25 ksps for MCLK = 4 MH z, fs = AMCLK = 1 MHz)

bit 10:9 DITHER<1:0> Control for dithering circuit for idle tones cancellation and improved THD

11 = Dithering ON, both channels, Strength = Maximum(MCP3901 Equivalent) - (DEFAULT)

10 = Dithering ON, both channels, Strength = Medium

01 = Dithering ON, both channels, Strength = Minimum

00 = Dithering turned OFF

bit 8 AZ_ FREQ Auto-zero fr equency setting

1 = Auto-zeroing algorithm running at higher speed

0 = Auto-zeroing algorithm running at lower speed (Default)

bit 7:6 RESET<1:0>: Reset mode setting for ADCs

11 = Both CH0 and CH1 ADC are in reset mode

10 = CH1 ADC in reset mode

01 = CH0 ADC in reset mode

00 = Neither ADC in reset mode(default)

bit 5:4 SHUTDOWN<1:0>: Shutdown mode setting for ADCs

11 = Both CH0 and CH1 ADC in Shutdown

10 = CH1 ADC in Shutdown

01 = CH0 ADC in Shutdown

00 = Neither Channel in Shutdown(default)

bit 3 Not implemented, read as 0

MCP3911

7.7 OFFCAL_CHn REGISTERS -

DIGITAL OFFSET ERROR

CALIBRATION REGISTERS

bit 2 VREFEXT Internal Voltage Reference Shutdown Control

1 = Internal Voltage Reference Disabled

0 = Internal Voltage Reference Enabled (Default)

bit 1 CLKEXT Internal Clock selection bits

1 = External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power

consumption) (Default)

0 = Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins.

bit 0 Not implemented, read as 0

REGISTERS

Name Bits Address Cof

OFFCAL_CH0 24 0x0E R/W

OFFCAL_CH1 24 0x14 R/W

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0

OFFCAL_CHn

<23> OFFCAL_CHn

<22> OFFCAL_CHn

<21> ... OFFCAL_CHn

<3> OFFCAL_CHn

<2> OFFCAL_CHn

<1> OFFCAL_CHn

<0>

bit 23 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown

bit 23:0 Digital Of fset ca libration value for the corresp onding ch annel CHn . This register s imply is ad ded t o the

output code of the channel bit-by-bit. This register is 24-bit two's complement MSB first coding.

CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a Don't Care if

EN_OFFCAL=0 (Offset calibration disabled) but its value is not cleared by the EN_OFFCAL bit.

MCP3911

7.8 GAINCAL_CHn REGISTERS -

DIGITAL GAIN ERROR

CALIBRATION REGISTERS

REGISTERS

Name Bits Address Cof

GAINCAL_CH0 24 0x11 R/W

GAINCAL_CH1 24 0x17 R/W

R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0

GAINCAL_CHn

<23> GAINCAL_CHn

<22> GAINCAL_CHn

<21> ... GAINCAL_CHn

<3> GAINCAL_CHn

<2> GAINCAL_CHn

<1> GAINCAL_CHn

<0>

bit 23 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 23:0 Digital gain error calibration value for the corresponding channel CHn. This register is 24-bit signed

MSB first co ding with a range of -1x to +0.9999999 x (from 0x8000 0 to 0x7FFFFF). Th e gain calibration

adds 1x to thi s regi ster and multiplies it to t he out put code of the channel bit by bi t, a fter offset c al ibra-

tion. The range of the ga in calib ration is th us from 0 x to 1.99 99999x (f rom 0x80 000 to 0x 7FFFFF). The

LSB corresponds to a 2-23 increment in the multiplier.

CHn Output Code = (GAINCAL_CHn+1)*ADC CHn Output Code. This register is a Don't Care if

EN_GAINCAL=0 (Offset calibration disabled) but its value is not cleared by the EN_GAINCAL bit.

MCP3911

7.9 VREFCAL Register – Internal

Voltage Reference Temperature

Coefficient Adjustment Register

This register is only for advanced users. This register

should not be written unless the us er want s to calibra te

the temperature coefficient of the whole system or

application. The default value of this register is set to

0x42.

Name Bits Address Cof

VREFCAL 8 0x1A R/W

R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0

VREFCAL<7> VREFCAL<6> VREFCAL<5> VREFCAL<4> VREFCAL<3> VREFCAL<2> VREFCAL<1> VREFCAL<0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7:0 Internal Voltage Temperature coefficient register value. (See Section 5.7.3 “Temperature

compensation (VREFCAL register)” for complete description).

MCP3911

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

20-Lead QFN (4x4x0.9 mm) Example:

20-Lead SSOP (SS) Example:

PIN 1 PIN 1

E/ML^^

122256

3911A0

E/SS^^

1122256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the ev ent the full Micr och ip p art numb er canno t be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

MCP3911

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EXPOSED

PAD

TOP VIEW NOTE 1

BOTTOM VIEW

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MCP3911

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MCP3911

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A2 c

NOTE 1

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MCP3911

APPENDIX A: REVISION HISTORY

Revision A (March 2012)

• Original Rel ease of this Document.

MCP3911

NOTES:

MCP3911

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3911A0: Two Channel Analog Font End Converter

Address Optio ns: XX A6 A5

A0* = 0 0

A1 = 0 1

A2 = 1 0

A3 = 1 1

* Default option. Contact Microchip factory for other

address options

Tape and Reel: T = Tape and Reel

Temperature Range: E = -40°C to +125°C

Package: ML = Plastic Quad Flat No Lead Package (QFN)

SS = Small Shrink Output Package (SSOP-20)

Examples:

a) MCP3911A0- E / ML: E xt end ed Temper atu re ,

Two Channel Analog

Front End Converter,

20LD QFN package.

b) MCP39 11A0T-E/ML:Tape an d Reel,

Extended Temperature,

Two Channel Analog

Front End Converter,

20LD QFN package.

c) MCP3911A0-E/ SS: Exte nd ed Temperatu re,

Tw o Chan ne l Anal o g

Front End Converter,

20LD SSOP package.

d) MCP3911A0T-E/SS:Tape and Reel,

Extended Temperature,

Tw o Chan ne l Anal o g

Front End Converter,

20LD SSOP package.

PART NO. X

Temperature

Range

Device

/XX

Package

Tape and

Reel

Address

Options

MCP3911

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is provided only f or yo ur convenience

and may be supers ed ed by u pda t es . It is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI C START,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62076-094-9

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

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http://www.microchip.com/

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EUROPE

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Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Worldwide Sales and Service

11/29/11