Cal-Chip ~ Multilayer Ceramic Chip Capacitors GMC Series introduction Multilayer Surface Mount Ceramic Capacitors are constructed by screen printing alternative layers of internal metallic elec- trodes onto ceramic dielectric materials and firing into a concrete monolithic body, then completed by application of metal end terminations which are fired to assure permanent bonding with the individual internal electrodes. Multilayer ceramic capacitors have various features such as large capacitance values in small sizes and excellent high fre- quency characteristics. Moreover, chip capacitors can be used on surface mount assembly equipment. Our fully integrated manufacturing and total quality control systems ensure unprecedented high standards of quality and reliability. Chip Capacitor Selection Selection of the most suitable capacitor for any application is based on the following: Dielectric Type The choice of dielectric is largely determined by the temperature stability required. COG (NPO) Capacitance change with temperature is 0-30ppm/C which is less than -0.3%C from -55C to +125C. Typicai capaci- tance change with life is less than -0.1% for NPOs, one-fifth that shown by most other dielectrics. NPO formulations show no aging characteristics. X7R Its temperature variation of capacitance is within +15% from -55C to +125C. This capacitance change in non-linear. 25U Despite their capacitance instability, Z5U formulations are very popular because of their small size, low ESL, low ESR and excellent frequency response. These features are particularly important for decoupling application where only a minimum Capacitance value is required. Y5V Y5V formulations are for general purpose use in a limited temperature range. They have a wide temperature characteristic of +22% - 82% capacitance change over the operating temperature range of -30C to +85C. Y5Vs high dielectric constant aliows the manufacture of very high capacitance values (up to 22MF) in small physical sizes. Capacitance Value & Tolerance Determined by circuit requirements. Note that chip prices decrease with lower capacitance value and looser tolerance. Voltage Determined by circuit requirements. Units are designed to exceed the withstanding voltage specification, i.e., the user need not incorporate an additional safety margin. Capacitor Size Select the smallest unit permitted by the circuit constraints that provides the required capacitance and voltage rating. Smaller units are generally less expensive : 0805 is the most economical size. Capacitor Termination Termination choice is largely determined by the chip attachment method. Silver-palladium is adequate for most applications involving soldering or solder reflow. Nickel barrier is standard and recommended for units exposed to repeated solder cycles, to minimize leaching of the ter- mination. [1Cal-Chip GMC Series Multilayer Ceramic Chip Capacitors Construction Solder(SN/PB) plated outer layer; typical thickness 0.003mm to 0.005mm 90% solder, 10% lead. Nickel! Barrier Layer (50 Micro-inches Electroplated Nickel min.) Electrodes Example Size Code Dielectric Capacitance (pF) Capacitance Voltage Termination Packaging Designates \ Tolerance Code EIA Marked | (EIA Code) _ Parts 0805 to 2225) +0 4 +0. L 1% 42% 3% t5% +10% +20% -20%~+80% Embossed Taping *NoTE Cal-Chip is phasing out marked capacitors as it is not cost effective. Our engineers also believe it weakens the durability of the component over its life due to the laser etching marking technique used.Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - COG/X7R/Y5V GMC Series 0402/0603 GMC04 GMC10 Type 0402 0603 Length (L,) mm 1.040.05 1.6+0.2 inches 0.04+0.002 0.063+0.008 Width (W mm 0.540.05 0.8+0.2 inches 0.02x0.002 0.031+0.008 j 0.540.1 0.840.2 Thickness (H) inch 0.02+0.004 0.031 +0.008 Termination Band Min Max Min Max (Lo & Lg) mm 0.1 0.35 0.1 0.4 inches 0.004 0.014 0.004 0.015 6.3 06 Band Gap (L4) mm (Min) inches 0.012 0.015 Dielectric COG X7R Y5V COG X7R Y5V Rated Voltage d.c. 25 | 50 [| 16 | 25 | 50 | 25 | 50 25 | 50 | 100 [10 [16 | 25]}50[ 16] 25 | 50 Cap. Range Code Minimum and Maximum capacitance values available 0.5pF Op5 1.0: v $pO :- 1.2 tp2 15 4p5. : 1.8 tps a 22 ape Ee 27 2p7 A i 33 i 3.9 39 Lo Ly _ Ly 47 497 5.6 5p6 68 6p8 a2 8p2 40 460 12 120 ms 18 450 18 180 22 28a a 270 33 880. 39 390 A7 A7O 56 560 68 630 82 820 100 107 120 121 450 18t 180 181 200 224 270 271 830 a0} 390 3901 a70 474 560 561 680 681 820 821 4.00F 02 1.2 122 4.6 182 1.8 182 22 re 27 272 3.3 342: 39 392 4:7 qe 5.6 562 68 6ae: B.2 822 40 103 12 123 45 183 18 183 a2 aga: 27 273 33 38a: 39 393 a7 473 56 563 68 683 82 823 . 100 104 150 154 220 24 = 270 274 a0 394 390 394 470 474 560 564 680 6B4 820 824 1k is [3 |Cal-Chip . GMC SerIEs Multilayer Ceramic Chip Capacitors - 50/63, 100, 200V - Size & Capacitance Table - Ultra Stable Dielectric CCE Part Number GMC 21 GMC29 GMC31 GMC32 GMC43 GMC45 GMC55 COG GMC57 Type 0805 0907 1206 1210 1812 1825 2220 2225 Dimensions cy co cy O 0 C1 L | U] mm inches Length (L,) 2.040.3 0.08+0.012 2.340.3 0.090.012 3.240.3 0.12520.012 3.240.3 0.125+0.012 4,540.35 0.180.014 4,520.35 0.180.014 5.720.4 0.2250.016 5.740.4 0.22540.016 Width (W) mm inches 1.2520.2 0.050.008 1.820.3 0.07140.012 1.6+0.2 0.063+0.008 2.540.3 0.10+0.012 3.240.3 0.125+0.012 6.320.4 0.2520.016 5.020.4 0.197+0.016 6.340.4 0.25+0.016 mm inches Thickness (H) 1.3 0.051 1.3 0.051 1.6 0.063 1.8 0.07 1.8 0.07 1.8 0.07 1.8 0.07 1.8 0.07 Termination Band (Ly & Lg} mm inches Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Band Gap (L4) (Min) mm inches 05 0.019 0.5 0.019 14 0.055 1.4 0.055 22 0.087 2.2 0.087 2.9 0.144 2.9 0.114 Rated Voltage d.c. 50, Pe 100 | 200 50 Pe 100 200 50 al 100 | 200 50 al 100 | 200 50. al 100 | 200 50 50 A 100 | 200 63 100 | 200 50 3} 100 | 200 Cap. Range Code Minimum and Maximum capacitance values available 0.5pF 10 1.2 18 1.8 22 1. Capacitance values to the E24 range also available, + a fd 2 _ L4 el, . 2. Higher capacitance values may be available with a corresponding increase in thickness. 3. Sizes 1005 and 1808 are available as a special requirement. 4. Chips to a specified thickness can be supplied as a special requirement.Cal-Chip | GMC Series "Multilayer Ceramic Chip Capacitors - 50/63, 100, 2000 - Size & Capacitance Table - Stable Dielectric CCE Part Number GMC 21 GMC29 GMC31 GMC32 GMC43 GMC45 GMC55 X7R GMC57 Type 0805 0907 1206 1210 1812 1825 2220 2225 Dimensions o ao 1 oO CI Oi LI LI Length (L,) mm inches 2.040.3 0.080.012 2.340.3 0.090.012 3.240.3 0.12540.012 3.240.3 0.12540,012 4,540.35 0.18+0.014 4.5+0.35 0.180.014 5.7+0.4 0.225+0.016 5,740.4 0.22540.016 Width (W) mm inches 1.2540.2 0.050.008 1.840.3 0.07140.012 1.60.2 0.063+0.008 2.540.3 0.10+0.012 3.220.3 0.12520.012 6.340.4 0.250.016 5.020.4 0.197+0.016 6.3+0.4 0.2520.016 Thickness (H) mm inches 1.3 0.051 1.3 0.051 1.6 0.063 18 0.07 1.8 0.07 1.8 0.07 1.8 0.07 1.8 0.07 (Lz & Lg) Termination Band mm inches Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Min Max 0.25 0.75 0.01 0.03 Band Gap (L4) (Min) mm inches 0.5 0.019 0.5 0.019 1.4 0.055 14 2.2 0.055 0.087 2.2 0.087 29 0.114 2.9 0.114 Rated Voltage d.c. 50 | 100 200 50 3 100 200 52 | 100 | 200 50 100 | 200 [52)] 100 | 200 50 ga 100 | 200 50 5 100 | 200 50 | 100 | 200 Cap. Range Cade Minimum and Maximum capacitance values available 100pF WEO ee 150 Teo! 220 Notes: 2. Sizes 1005 and 1808 are available as a special requirement. 3. Chips to a specified thickness can be supplied as a special requirement. 1. Higher capacitance values may be available with a corresponding increase in thickness.Cal-Chip (eros, ow GMC Series Multilayer Ceramic Chip Capacitors - 50/63, 100, 200V - Size & Capacitance Table - General Purpose Dielectric Z5U CCE Part Number GMC 21 GMC29 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57 Type 0805 0907 1206 1210 1812 1825 2220 2225 Dimensions a m a ao | i | Ll [ | Length (L) _ mm 2,020.3 2.320.3 3.20.3 3.20.3 4,520.35 4,540.35 5,720.4 5.70.4 inches | 0,0820.012 | 0.0920.012 | 0.12540.012 | 0.12540.012 | 0.1820.014 | 0.1840.014 | 0.22520.016 | 0.22520.016 Width (W) mm | 1,250.2 1.80.3 1,640.2 2.50.9 3.240.9 6.30.4 5.00.4 6.320.4 inches | 0.05+0.008 | 0.07140.012 | 0.063+0.008 | 0.10#0.012 | 0.12520.012 | 0.2520.016 | 0.19720.016 | 0.2520.016 Thickness (H) == mm 1.3 1.3 1.6 18 1.8 1.8 1.8 1.8 inches 0.051 0,051 0.063 0.07 0.07 0.07 0.07 0.07 Termination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max (Ly & Lg) mm] 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 inches | 9.01 0.03 | 0.01 0.03 | 0.01 0.03 | 0.01 0.03 | 0.01 0.03 | 0.01 0.03 | 0.01 003 | 0.01 0.03 Band Gap (Ly) = mm 0.5 0.5 1.4 1.4 22 2.2 29 29 (Min) inches 0.019 0.019 0.055 0.055 0.087 0.087 0.174 0.114 Rated Voltage d.c. 2-64 100 | 200 |2<,] 100 | 200 [524] 100 | 200 | 825] 100 | 200 182.1 s00 | 200 [5227] 100 | 200 1821 100 | 200 [<7 100 | 200 Cap. Range Code Minimum and Maximum capacitance values available 1.OnF 102 ARB de 188 22 208 33 392 47 472 68 BBR! 10 103 18 153 22 223 3a 38g 39 393 a 474 56 563 68 689: 100 104 1602: 154 220 224 330 } 334 470 474 BBO 684 1.0uF 405 5) BBE 2.2 225 38 0836 47 475 5.6 a 6.8 685 Notes: 1. Capacitance values to the E12 range also available. 2. Higher capacitance values may be available with a corresponding increase in thickness. 3. Sizes 1005 and 1808 are available as a special requirement. 4. Chips to a specified thickness can be supplied as a special requirement._Cal-Chip - . Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - Ultra Stable Dielectric GMC SERIES COG Dielectric GMC 21 GMC31 GMC32 GMC43 GMC55 GMC57 Type 0805 1206 1210 1812 2220 2205 Dimensions a ca a 1 L] [ ] Length (L,) mm 2.00.3 3,240.3 3.240.3 4.540.358 5.740.4 5720.4 inches 0.08+0.012 0.125+0.012 0.12520.012 0.18+0.014 0.22520.016 0,22520.016 Width (W) _ mm 1.2540.2 1.620.2 2.540.3 3.220.3 5,040.4 6,320.4 inches 0.0520.008 0,063+0.008 0.10+0.012 0.125+0.012 0.197+0.016 0.25+0.016 Thickness (H) mm 1.3 1.6 18 1.8 18 18 inches 0.051 0.063 0.07 0.07 0.07 0.07 Termination Band Min Max Min Max Min Max Min Max Min Max Min Max (Lz & Lg) mm 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 inches 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 Band Gap (Ly) = mm 0.5 1.4 14 2.2 2.9 2.9 (Min) inches 0.019 0.055 0.055 0.087 0.114 0.114 Rated Voltage d.c. 16 | 25 16 | 25 16 25 16 25 Cap. Range Code inimum and Maximum capacitance values availabl 0.5pF Ops $0 : pO: Cees 1.2 1p2 FS 165 eR 1.8 1ps 22 ap2 2.7 2p7 a3 apg 3.9 3p9 Oe Re? 4p7 5.6 5p6 68 aps 8.2 8p2 40 400 12 120 16. +80 Be 18 180 | ae 220 ce 27 270 33 330: 39 390 a7 470 56 60 68 630 a5 820 100 . 101 120 121 150. F $51 180 181 220 221. > 270 271 330 : 33+ 390 391 BIO et 47 560 561 -. 680 681 820 821 10nF. 192 a 12 122 = AS 452 1.8 182 22 222... 2.7 272 33 332. Bes 3.9 392 47 MP2 5.6 562 68 882 8.2 822 40 1038 12 123 15 +58 18 183 22 223 27 273 a3 333 39 393 a? 473 56 _ 563 68 683 82 823 #00 = 94.Cal-Chip E Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - Stable Dielectric GMC SERIES 10,16 & 25V X7R Dielectric GMC 21 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57 Type 0805 1208 1210 1812 1825 2220 2295 Dimensions a a Cl] CI U1 [] [ | Length (L,) mm 2.040.3 3.20.3 3.240.3 4.5+0.35 4.5+0.35 5.70.4 5.70.4 inches | 0.080.012 0.1250.012 0.1250.012 0.1840.014 0.180.014 0.225+0.016 0.22520.016 Width (W) mm 1.250.2 1.640.2 2.540.3 3.220.3 6.3+0.4 5.0+0.4 6.340.4 inches | 9.050.008 0,06320.008 0.1020.012 0.125+0.012 0.2540.016 0.197+0.016 0.250.016 Thickness (H) mm 13 16 18 18 18 1.8 1.8 inches 0.051 0.063 0.07 0.07 0.07 0.07 0.07 Termination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max (Lz & Lg) mm} 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 inches | 9.91 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 Band Gap (L4) = mm 0.5 1.4 14 2.2 2.2 2.9 2.9 (Min) inches 0.019 0.055 0.055 0.087 0.087 0.114 0.114 Rated Voltage d.c. 1o| 16] 25 | of ie[ 25] t6 | 2 | t6 | 2 | 16 | 2 | te | 2 | te | 25 Cap. Range Cade Minimum and Maximum capacitance values available 100pF 101 ASO: | is eee et) te 150 151 ; +. EB SB 8 ts RA Sg Re eS ot eile i | te : 2 cae BPE 330 331 Le Le Lg BBO: aot | 470 471 6 860! $61 680 681 : 820 G24 1,0nF 102 Be: RE 15 182 4B: 482: 2.2 222 QF - 2 2FR. 3.3 332 3.9 382 4,7 472 5.6 S62 > 6.8 682 82 B22 10 103 {2 FOS. 15 153 +8 eS 22 223 27 27d: 33 393 3 303: 47 473 58 583. 68 683 Ba: B23- 100 104 120 124 450 154 180 BA 220 224 270 L ats 330 334 470 474 680 684 Ba: eae 1.0UF 105 "2 125. 1.5 155 1B 4165 22 225 27 275. 3.3 335 a8 BOB SE 47 475 56 $68: 68 685 8.2 B25. 10 106 18 ABB. 22 226_Cal-Chip GMC SERIES Multilayer Ceramic Chip Capacitors - Size & Capacitance Table - General Purpose Dielectric y p Cap p p 10,16 & 25V ZS5U/YS5V Dielectric GNC 21 GMC31 GMC32 GMC43 GMC45 GMC55 GMC57 Type 0805 1206 1210 1812 1825 2220 2295 Dimensions m a oO 1 C1 LJ { | Length (L,) mm 2.040.3 3,240.3 3.20.3 4,540.35 4540.35 5,740.4 5,740.4 inches | 0.080.012 0.125+0.012 0.125+0.012 0.1840.014 0.1840.014 0.22540.016 0.22540.016 Width (W) mm) 1,2530.2 1.60.2 2.50.3 3,240.3 6.320.4 5,020.4 6.320.4 inches | _0.05+0.008 0.06310.008 0.100.012 0.125+0.012 0.25+0.016 0.19740.016 0.25+0.016 Thickness (H) == mm 1.3 16 18 1.8 1.8 1.8 18 inches 0.051 0.063 0.07 0.07 0.07 0.07 0.07 Termination Band Min Max Min Max Min Max Min Max Min Max Min Max Min Max {Ly & Lg) mmt 0.25 075 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 0.25 0.75 inches | 9.91 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 0.01 0.03 Band Gap (L4) = mm 0.5 1.4 1.4 2.2 22 29 29 {Min) inches 0.019 0.055 0.055 0.087 0.087 0.114 0.114 Rated Voltage d.c. 16 | 2 | 10] 16] 25] 16 | 2 16 | 25 16 | 25 16 | 2 | 16 | 26 Cap. Range Code Minimum and Maximum capacitance values available 1.0nF 102 2.2 222 ae ae 4.7 472 68 SABBR Ss. 10 103 15 BBs 22 223 33 GEO 47 473 65 BBB 100 104 AOS Be 220 224 $30 Poe: 470 474 680. Git 1.0uF 105 FG 498. 2.2 225 3.3 S38 47 475 63 B85 : 10 106 46 Be 22 226 27 BIT: 33 336 3g RBOBLL: 47 476cae GMC SERIES Cal-Chip Multilayer Ceramic Chip Capacitors COG Dielectric Ultra stable class | dielectric: linear temperature coefficient, low loss, negligible change of electrical properties with time, voltage and frequency. -55C 0+30ppmC | 0+30ppm/C | 0.1% Max, |* 25C, Vocw:: | 2.5 X Vocw 0% per * C<1000pF to 0.02% Typical | >100GQF or decade hour f=1MHz +125C 10000F, V=1.0Vrms whichever is less +0.2Vrms 125C, Vocw: T=25C >10GQOF or rane 100QF SANZ : ; V=1.0VVrms whichever is less +0.2Vrms T=25C TEMPERATURE COEFFICIENT VOLTAGE COEFFICIENT IR(QF) INSULATION RESISTANCE VS TEMP CAPACITANCE VS FREQUENCY %AC &j %aCc 10K %4C 02 02 0.4 01 Qt 0.0 0.0 1K 0.0 0.4 ot ~0.2 02 1K -5 -15 25 65 85 125 50 00 160 10? 103 40 10 10 Temperature, *C Bias Voltage(VDC) Temperature, C Frequency, Hz X7R Dielectric Stable class II dielectric (EIA X7R) -55C 15% X7R 2.5% Max, |* 25C, Vocw:: | 2.5 X Vocw <2% per 1KHz, to Not Applicable} 1.8% Typical | >100GQFor decade hour | 1.0Vrms +125C | 10000F, +0.2Vrms | whichever is less 25C 125C, Vocw: | | >10GQF or | 10022F | whichever is less TEMPERATURE COEFFICIENT VOLTAGE COEFFICIENT IR(Q F) INSULATION RESISTANCE VS, TEMP noc AGING RATE rs jC pp %AC 25 50 75 100 125 0.1 1.0 10 107. 10> 10% 10 Time After Last Curie Point(Hours) - -18 25 65 85 125 Temperature C Bias Voltage( VDC} Temperature CCal-Chip ~ Multilayer Ceramic Chip Capacitors Z5U (Y5V) Dielectric GMC SEeErIEs High capacitance per unit volume: general purpose product -30C 422% 3.0% Max, |10GQor100QF | 25 xX Vocw 3.0% per ~4KHz, to ~82% 2.0% Typical | whichever is decade hour 0.5 Vrms +85C less, 25C 25C, Vocw TEMPERATURE COEFFICIENT DC VOLTAGE COEFFICIENT AGING RATE AC VOLTAGE COEFFICIENT %aAC coer aie rere me) " or 9 Q 20 40 60 -90 -30 25 40 55 70 85 0 25 50 0.1 1.0 10 107 10% 10* 10 Temperature * C Bias Voltage (VDC) Time after last Curie Point (hours) Test Voltage (Vms) Packaging (Taping) Standard Reel Unit:mm (Reel Type-Size) op odes pg ey R : @178 250 013.0 | 921.0 2.0 14.9 0.8 1.0 1 +2.0 min. +0.5 +0,8 +0.5 +1.5 +0.2 , E | 10000 units per reel OPTIONAL Unit:mm : : = Lo a = 2250 | #50 | 013.0] 0210] 20 | 100] 08 40 +2.0 min. +0.5 +0.8 +0.5 +15 +0.2 , a ~aflet Carrier Tape (Standard) Ww Top Cover Tape 165-180 * To peel off the cover tape by the method shown in the Carrier Tape eT right figure apply a peel-off force of 20 gf - 60 gf (card board); 35 of - 75 gf (plastic tape). > Cover Tape tension direction __ . * The cover tape should not touch the top or bottom of the Tape unreeling i direction chip. Bottom Cover Tape Ifthe cover tape has been peeled off it may be difficult to remove the chip due to punch-hole clearance, dirt, and debris. Make sure therefore that no paper waste will Empty Chip Mounting = Empty Leader adhere to and block the absorption nozzle. section section section section eo, ee we 09 O a) OO Te * If the cover tape has been peeled off from the top, stick it oo oo@a \ @o 606O0 fo oe E | Start back on with a suitable adhesive. |<$> fe] > 50 pitch 30 pitch 200mm * Follow the illustration for the start and end of the winding (200mm) (120mm) . ST operation. Unreeling direction 11Cal-Chip Multilayer Ceramic Chip Capacitors GMC SErIeEs Cardboard carrier tape for 0402, 0603 type and 0805/1206 type Unit: mm 0402 | 0.720.2 | 1.320.2 2.0+0.05 10000 0603 | 1.1+0.2 | 1.920.2 Angular 4000 0805 |1.6520.2| 2.420.2 | 8.020.3 |3.520.05/1.7520.1| 4,040.1 |2.020.05 | 4.0%0.1 |o1 5th 1.1 max| 1.4 max! Punch Hole | 4000 to 5000* 4206 | 2.020.2 | 3.620.2 4000 to 5000" *Dependent on chip thickness Sprocket hole Component window punch hole / gD. f f. / a tt ay Y ee it | Po Unreeling direction : * Embossed plastic carrier tape for 0805/1206 type and 1210 type P. P, Components mounted . 4 Unit: mm 0805 | 1.4520.2| 2.320.2 Angular 2000 to 5000* 1206 | 2.0x0.2 | 3.620.2 | 8.0+0.3 |3.520.05 |1.7520.1 | 4.020.1 | 2.0+0.05) 4.00.1 01.5401 0.6 max |2.5max| Embossed | 2000 to 5000* 1210 | 2.920.2 | 3.620.2 Hole 2000 to 4000* Dependent on chip thickness tr Sprocket hole Component compartment hole oo SF Bee Unreeling direction pai po e Embossed plastic carrier tape for 1812, 1825, 2220 and 2225 type Components mounted 1812 | 3.640.2 . Angular toe 1825. | 6.80.3 | 4.90.2 | 12.020.3 | 5.520.05 | 1.75+0.1 2,020.05 | 4.00.1 Embossed 4906 2220 | 5.50.3 | 6.20.3 0.6 max. |6.5 max. Hole +906 2225 | 6.80.3 | 6.20.3 1000 Unit: mm Dependent on chip thickness tr Sprocket hole Component Compartment hole Too a | Z / | CPE EH oT 1 J y ) chy wale b a a1? WD q eI YW \ te P, P, Po | Unreeling direction Components mountedCal-Chip Multilayer Ceramic Chip Capacitors - All Dielectrics Tape and Reel Packing Quantities Chip Size 178 mm (7) Reel 330 mm (13) Reel 0402 10,000 N/A 0603 4,000 16,000 0805 4,000 12,000 0907 3,000 12,000 1206 4,000 15,000 1210 2,000 , 4,000 8,000 1812 1,000 4,000 1825 1,000 4,000 2220 1,000 4,000 2225 1,000 4,000 The tape and reel packing quantities apply to voltages up to 200V rating only. The 0402 and 0603 size chips have similar width and thickness dimensions. GMC SeriesCal-Chip ial Multilayer Ceramic Chip Capacitors * Bulk case packaging can reduce the stock space and transportation costs. BULK CASE * The bulk feeding system can increase the productivity. * It can eliminate the components loss. GMC SERrIEs Structure and Dimension HU Th B T Dimension 410+0.7 Dimension | 31 5+0.2, 0: 49+0.35 Quantity Quantity 15,000Cal-Chip | Multilayer Ceramic Chip Capacitors RELIABILITY AND TEST CONDITIONS GMC SERIES Capacitance Within tolerance shown * Class (I) by part number code C<1000pF:1MHz+10%, 0.5 to 5Vrms Dissipation Factor * Class (I) C21000pF:1KHz+10%, (tand or Q) C<30pF:Q2400+20xC 1.0+0.2Vrms C230pF:Q21000 Class (Il) * Class (Il) B:DF<2.5% 1KHz+10%, 1.0+0.2Vrms F:DF<5.0% Insulation C<10,000pF: IR>100GQ Apply rated voltage for 60 Resistance(IR) C>10,000pF: IR2500/C seconds at room temperature and normal humidity. (70% RH max) Dielectric There shall be no evidence | Apply 3x rated voltage (Class |) Withstanding of damage or flash over or 2.5 x rated voltage (Class II) to Voltage during the test both terminations for 5 seconds. Charge and discharge current are less than 50mA. Termination No mechanical damage Fillet Solder Adherence ' Alumina 500g Board Care shall be taken to avoid thermal shock. 500g of steady pull is applied in direction of arrow for 1 minute. ; After soldering capacitor on the trength No mechanical damage Bend Streng g glass-epoxy PWB, 2 mm of vend- ing shall be applied for 10 seconds as shown by drawing. UL + Load i 90mm *Soldered| Life Test * Class (I) Applied 2 x rated voltage at (High Temperature No more than +3% or 0.3pF | Maximum operating temperature Loading Test) Ac] Whichever is less for 1000 hours. The surge current * Class (II) shall not exceed 50mA after above B:+10% max testing condition, test samples F:+30% max shail be kept in room temperature ~ Class () for 24 hours (Class |) or C<10pF:Q>200+10xC and then shall be measured Q 10<C<30pF:Q2275+5/2xC or| G230pF:Q2350 DE| Class (I) B:DF<5.0% F:DF<7.5% TOOOME) or 50OF, min IR | whichever is lessCal-Chip Multilayer Ceramic Chip Capacitors RELIABHLITY AND TEST CONDITIONS GMC Series * Class (1) Moisture Test No more than 45% or +0.5pF . ; AC] whichever is larger The capacitors shall be subjected * Class (II) to 40C, 90-95%RH for 500 hours. ern After above testing condition, sampies 7 Clase ) shall be kept in room temperature for C<10pF:Q>200+10xC 24 hours (Class !) or 48 hours (Ciass Il), Q| 10<C<30pF:Q2275+5/2xC and then shall be measured. or] C230pF:Q2350 DF] * Class (II) B:DF<5.0% F:DF<7.5% IR | 1000MQ or S0QF, whichever is less ; * Class (I) Moisture No more than 7.5% Resistance or +0.75pF Test AG . Claes th, is larger Apply rated voltage at 40C, B+10% 90-95%RH for 500 hours. F:+30% The surge current shall not exceed * Class (I) 50mA. After testing with above condition, C<30pF:Q>100+100/3xC samples shall be kept in room tempera- Q 230pF:Q220 or| C280PF:Q2200 ture for 24 hours (Class |) or 48 hours DF cass Oo (Class ||), and then shall be measured. F:DF<7.5% IR 500MQ or 25QF, min whichever is less * Class {I . Temperature No m AS ) than 42.5% Perform 5 cycles as follow: Cycle or +0.25pF 1. Room temperature. Dweil for 15 minutes. whi ch ever is larger 2. Minimum operating temperature, dwell for AC * Class (II) 30 minutes. B:+5% 3. Room temperature, dwell for 30 minutes. e. 120% 4. Maximum operating temperature, dwell for =_ 30 minutes. 2 To satisfy the specified After above testing condition, samples shall pF| initial value. be kept in room temperature for 24 hours To salishy th Tied (Class 1) or 48 hours (Class If), and then shall IR| _O Sausly the spectie be measured. initial value. wee Termination area shall be at The capacitors are completely Solderability least 95% covered with a new immersed during 4+0.5 seconds solder coating. There shail be no | in the molten solder with a crack and ceramic exposure of temperature of 230+5C terminated surface by melting. *Solder: Sn 63. Class (I) | Resistance to No more than +2.5% Immerse into molten solder at Solder Heat Test or +0.25pF 27045C for 340.5 seconds. AC| whichever is larger Preheat before immersion. Class (Il) 1. 80~100C for 2 minutes. B:+5% 2. 150~180C for 2 minutes. F:+20% 3. 270+5C for 340.5 seconds. Q|_ To satisfy the specified The capacitance measurement or] initial value. shall be made after sample DF To Sansty tie Specmied keeping at room temperature for IR] initial vatue. 24 hours.Cal-Chip mm GMC SERIES Multilayer Ceramic Chip Capacitors APPLICATION MANUAL For SURFACE MOUNTING 1. Temperature / Humidity Control Since dew condensation may occur by the differences in temperature when the products are take out of storage, it is important to maintain a temperature- controlled environment. . Design of Solder Land Pattern When designing printed circuit boards, the shape and size of the solder lands must allow for the proper amount of solder on the capacitor. The amount of solder at the end terminations has a direct effect on the probability that the chip will crack. The greater amount of solder, the Jarger amount of stress on the chip, and the more likely that it will break. Use the following illustrations as guidelines for proper solder land design. Recommendation of solder land shape and size. ___ Solder Resist. ~ T Solder Resist iy IP eee solder! rand 2/3 Wib<w 2 2/3T<acT . Adhesives MLCCs generally require the use of an adhesive to adhere the chips to the circuit board prior to wave soldering. 3-1. Requirements for Adhesives - They must have enough adhesion so that the chips will not fail off or move during the handling of the circuit board. - They must maintain their adhesive strength when exposed to soldering temperatures. - They should not spread or run when applied to the circuit board. - They should have a long pot life. - They should harden quickly. - They should not corrode the circuit board or chip material. - They should be a good insulator. - They should be non-toxic, and not produce harmful gases, nor be harmful when touched. 3-2. Application Method It is important to use the proper amount of adhesive. Too little will cause poor adhesion to the circuit board, and too much may strain the conductor pattern, thereby causing defective soldering. The foliowing illustrations show the proper quantity of adhesive. Solder Resist (Unit: mm) Land E ponBin betes P vw A = a 0.2 min 0.2 min Py st | b 70~100um 70~100pm am 7 + LLDIITALI LIL LL TTA ELT IT TTP c >0 >0 =e ar 3-3. Adhesive Hardening Characteristics To prevent oxidation of the terminations, the adhesive must harden at 160C or less, within 2 minutes or less. | 17Multilayer Ceramic cthp Capacitors GMC Series 4. Mounting 4-1. Mounting Head Pressure Excessive pressure will cause chip capacitors to crack. The pressure between nozzle and chip capacitor will be 300g maximum during mounting. 4-2.Bending Stress Bending of printed circuit board by mounting head when double-sided circuit boards are used, chip capacitors first are mounted and soldered onto one side of the board. When the capacitors are mounted onto the other side, it is important to support the board as shown in the illustration. If the circuit board is not supported, it may bend, causing the already installed capacitors to crack. | nozzle | force 7 hotbdihubabrikakhabat tA tn ht tLitdaidbitidd thi tkitetidtididt hid d. oo support pin 5. Flux Although highly activated flux gives better solderability, substances which increase activity may also degrade the insulation of the chip capacitors. To avoid such degradation, it is recommended that a mildly activated rosin flux (less than 0.2% chlorine) be used. 6. Soldering Since a multilayer chip ceramic capacitor comes into direct contact with melted solder during soldering, it is exposed to potentially damaging mechanical stress caused by the sudden temperature change. The capacitor may also be subject to silver migration, and to contamination by the flux. Because of these factors, soldering technique is critical. 6-1. Soldering Methods Method Classification Mass 1R/Convection reflow * VPS (Vapor phase) Reflow Soldering Selective * Hot air/gas reflow Laser Flow Soldering Dual Wave 6-2. Soldering Profile To avoid the crack problem by sudden temperature change, follow the temperature profile in the adjacent graph.Cal-Chip Lo Nabe ti ~ Multilayer Ceramic Chip Capacitors 300 250 200 150 100 50 preheating soldering cooling GMC Series preheating Dipping cooling " over 60 sec 1~20sec over 60 sec Reflow Soldering 6-3. Manual Soldering Manual Soldering can pose a great risk of creating thermal cracks in chip capacitors. The hot soldering iron tip comes into direct contact with the end terminations, and operator's carelessness may cause the tip of the soldering iron to come into direct contact with the ceramic body of the capacitor. Therefore the soldering iron must be handled carefully, and close attention must be paid to the selection of the soldering iron tip and to temperature control of the tip. 6-4. Amount of Solder 300 250 200 150 100 50 eee t over 60 sec 2~3 sec over 60 sec Flow Soldering Too much solder Cracks tend to occur due to large siress Amount of solder is adequate Liam Sr Maximum amount of solder LW Minimum amount of solder Not enough solder wart bere Lda Weak holding force may cause bad connections or detaching of the capacitor 6-5. Cooling Natural cooling using air is recommended. if the chips are dipped into solvent for cleaning, the temperature difference (AT) must be less than 100C. 6-6. Cleaning If rosin flux is used, cleaning usually is unnecessary. When strongly activated flux is used, chlorine in the flux may dissolve into some types of cleaning fluids, thereby affecting the chip capacitors. This means that the cleaning fluid must be carefully selected, and should always be new. 7. Notes for Separating Multiple, Shared PC Boards A multi-PC board is separated into many individual circuit boards after soldering has been completed. If the board is bent or distorted at the time of separation, cracks may occur in the chip capacitors. Carefully choose a separation method that minimizes the bending of the circuit board. 79@ Cal-Chip ec Multilayer Ceramic =Chip Capacitors GMC SEeErIEs APPLICATION INFORMATION ON SOLDER PAD DESIGN FOR SURFACE MOUNT CHIP CAPACITOR Recommended Pad Dimensions 0.021 0.022 0.035 0.030 0.040 0.050 0.040 0.070 0.040 0.065 0.040 0.100 0.050 0.120 0.050 0.250 0.050 0.250 0.050 0.250 0.060 0.400 *These sizes are recommended for use with IR and vapor phase soldering only. a T > (TOTAL LENGTR) (WIDTH) +-<j# W P- L _qq_S pr L ej (LENGTH) (SEPARATION) (LENGTH) NOTICE: Specifications are subject to change without notice. Contact your nearest Cal-Chip Sales Office for the latest specifications. All statements, information and data given herein are believed to be accurate and reliable, but are presented without guarantee, warranty, or responsibility of any kind, expressed or implied. Statements or suggestions concerning possible use of our products are made without representation or warranty that any such use is free of patent infringement and are not recommendations to infringe any patent. The user should not assume that all safety measures are indicated or that other measures may not be required. Specifications are typical and may not apply to all applications.Cal-Chip ~ Multilayer Ceramic Chip Capacitors GMC SErIEs Crip MARKING IDENTIFICATION SYSTEM Marking Proposed EIA Standard: Two Position Marking:* Alpha: ist position significant figures of capacitance in pF Numerical: 2nd position decimal multiplier of capacitance NOTE: 0402, 0603, 0907 available unmarked only. CAPACITANCE 10 | 100 | 1000] 10,000 | 100,000 11 | 110 | 1100] 11,000 | 110,000 F ; 12 | 120 | 1200} 12,000 | 120,000; [amem 4.0 13 | 130 | 1300] 13,000 | 130,000 mee, 4.5 15 | 150 | 1500] 15,000 | 150,000 1 5.0 16 | 160 | 1600 | 16,000 | 160,000 1 6.0 18 | 180 | 1800] 18,000 | 180,000] 1 7.0 20 | 200 | 2000 | 20,000 | 200,000 8.0 22 | 220 | 2200 | 22,000 | 220,000 ; 9.0 24 | 240 | 2400 | 24,000 _| 240,000 eee x1.0 | x10 | x100 | x1000] x10,000 | x100,000 27 | 270 | 2700} 27,000 | 270,000 30 300 | 3000 | 30,000 | 300,000 33 | 330 | 3300] 33,000 | 330,000 36 | 360 | 3600 | 36,000 | 360,000 39 | 390 | 3900 | 39,000 | 390,000 43 | 430 | 4300) 43,000 | 430,000 47 | 470 | 4700} 47,000 | 470,000 51 | 510 | 5100} 51,000 | 510,000 56 | 560 | 5600 | 56,000 | 560,000 > > 62 | 620 | 6200 | 62,000 | 620,000 68 | 680 | 6800 | 68,000 | 680,000 75 | 750 | 7500 | 75,000 | 750,000 ee 82 | 820 | 8200| 82,000 | 820,000 91 910 | 9100 | 91,000 | 910,000 TWO POSITION MARKING (1000 pF)