©2001 National Semiconductor Corporation
www.national.com
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/
CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers
December 2001
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/
CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/
CR16M9S5/CR16MUS5/CR16MUS9/
Family of CompactRISC 16-Bit Microcontrollers
1.0 General Description
The family of CompactRISC™ microcontrollers are gener-
al-purpose 16-bit microcontrollers based on a Reduced In-
struction Set Computer (RISC) architecture. The device
operates as a complete microcomputer with all system tim-
ing, interrupt logic, flash program memory or ROM memo-
ry, RAM, EEPROM data memory, and I/O ports included
on-chip. It is ideally suited to a wide range of embedded
controller applications because of its high performance,
on-chip integrated features and low power consumption,
resulting in decreased system cost.
The family of CompactRISC 16-bit microcontrollers offer
the high performance of a RISC architecture while retain-
ing the advantages of a traditional Complex Instruction Set
Computer (CISC): compact code, on-chip memory and I/O,
and reduced cost. The CPU uses a three-stage instruction
pipeline that allows execution of up to one instruction per
clock cycle, or up to 20 million instructions per second (MI-
PS) at a clock rate of 20 MHz.
CR16B
Core
Core Bus
Peripheral Bus
Clock Generator
Slow Osc
Processing
Unit
I/O µWire/SPI A/D
Fast Osc
2 kbyte Interrupt
Control
(ICU)
Peripheral
Bus
Controller
Power-on-Reset
RAM
48k Flash
Program
Memory
Two Analog
Comparators Real-Time
Timer
WATCHDOG
Power-Save
Management
Two
MFTs
Two
USARTs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
640 Bytes
EEPROM
Data
Memory
boot
MIWU
ROM
Please note that not all family members contain same peripheral modules and features.
Block Diagram
Obsolete
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Table of Contents
1.0 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 CR16B CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.4 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.6 Multi-Input Wake-up. . . . . . . . . . . . . . . . . . . . . . . . .6
3.7 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . .6
3.8 Power Management. . . . . . . . . . . . . . . . . . . . . . . . .6
3.9 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . .6
3.10 Real-Time TIMER and Watchdog . . . . . . . . . . . . . .6
3.11 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.12 MICROWIRE/SPI. . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.13 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.14 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . .7
3.15 Development Support . . . . . . . . . . . . . . . . . . . . . . .7
3.16 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 ENV0 and ENV1 Pins . . . . . . . . . . . . . . . . . . . . . .12
4.2 Module Configuration (MCFG) Register . . . . . . . .12
4.3 Module Status (MSTAT) Register . . . . . . . . . . . . .12
5.0 Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . .14
6.0 CPU and Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 General-Purpose Registers. . . . . . . . . . . . . . . . . .15
6.2 Dedicated Address Registers . . . . . . . . . . . . . . . .15
6.3 Processor Status Register. . . . . . . . . . . . . . . . . . .15
6.4 Configuration Register. . . . . . . . . . . . . . . . . . . . . .16
6.5 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . .16
6.6 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6.7 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7.0 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.2 BIU Control Registers . . . . . . . . . . . . . . . . . . . . . .18
7.3 Wait and Hold States Used . . . . . . . . . . . . . . . . . .19
8.0 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Flash Program Memory. . . . . . . . . . . . . . . . . . . . .21
8.2 RAM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8.3 EEPROM Data Memory. . . . . . . . . . . . . . . . . . . . .24
8.4 ISP Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9.0 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . .27
9.2 Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . .28
9.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . .29
9.4 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . .29
9.5 Interrupt Programming Procedures . . . . . . . . . . . .31
10.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.2 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . .33
10.3 Idle Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.4 Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.5 Switching Between Power Modes . . . . . . . . . . . . .33
11.0 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .36
11.1 External Crystal Network . . . . . . . . . . . . . . . . . . . .36
11.2 Main System Clock. . . . . . . . . . . . . . . . . . . . . . . . .37
11.3 Slow System Clock. . . . . . . . . . . . . . . . . . . . . . . . .37
11.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .38
11.5 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
11.6 Dual Clock and Reset Registers . . . . . . . . . . . . . .38
11.7 Slow Clock Prescaler Register (PRSSC). . . . . . . .38
12.0 Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
12.1 Wake-Up Edge Detection Register (WKEDG). . . .39
12.2 Wake-Up Enable Register (WKENA). . . . . . . . . . .39
12.3 Wake-Up Source Select Register (WKCTRL) . . . .40
12.4 Wake-Up Pending Register (WKPND) . . . . . . . . . .40
12.5 Wake-Up Pending Clear Register (WKPCL) . . . . .40
12.6 Programming Procedures . . . . . . . . . . . . . . . . . . .40
13.0 Real-Time Timer and WATCHDOG. . . . . . . . . . . . . . . . .41
13.1 TWM Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . .41
13.2 Timer T0 Operation . . . . . . . . . . . . . . . . . . . . . . . .41
13.3 WATCHDOG Operation . . . . . . . . . . . . . . . . . . . . .42
13.4 TWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13.5 WATCHDOG Programming Procedure . . . . . . . . .43
14.0 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
14.1 Timer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . .45
14.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . .47
14.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .50
14.4 Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . .50
14.5 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .51
15.0 MICROWIRE/SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
15.1 MICROWIRE Operation . . . . . . . . . . . . . . . . . . . . .54
15.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
15.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
15.4 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . .57
15.5 MICROWIRE Interface Registers. . . . . . . . . . . . . .58
16.0 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
16.1 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . .61
16.2 USART Operation . . . . . . . . . . . . . . . . . . . . . . . . .61
16.3 USART Registers. . . . . . . . . . . . . . . . . . . . . . . . . .65
16.4 Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . .67
17.0 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
17.1 Analog Comparator Control/Status Register
(CMPCTRL)68
17.2 Analog Comparator Usage. . . . . . . . . . . . . . . . . . .68
18.0 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
18.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . .69
18.2 A/D Converter Registers . . . . . . . . . . . . . . . . . . . .70
18.3 A/D Converter Programming . . . . . . . . . . . . . . . . .72
19.0 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
20.0 Register Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
20.1 Register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
21.0 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . .81
Comparator AC and DC Characteristics . . . . . . . . . . . .83
Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
22.0 Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
22.1 8-bit MICROWIRE/SPI (MWSPI) . . . . . . . . . . . . . .95
22.2 Timing and watchdog module . . . . . . . . . . . . . . . .95
23.0 Physical Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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1.0 General Description (Continued)
In the following text, device is alsays refered to the family of
CompactRISC 16-bit microcontrollers. For the exact feature
set, check individual datasheets.
The device is available in a variety of package sizes and
types. All devices have 48 kbytes of reprogrammable flash
program memory, 1.5 kbytes of ISP memory, 2 kbytes of stat-
ic RAM, and 640 bytes of non-volatile EEPROM data memo-
ry. The 80-pin device has two USARTs, two 16-bit multi-
function timers, one SPI/MICROWIRE-PLUS™ serial inter-
face, an 8-channel A/D converter, two analog comparators,
WATCHDOG™ protection mechanism, and up to 48 general-
purpose I/O pins. The 44-pin devices offer the same basic
features as the 80-pin device, but with fewer I/O ports and
peripheral modules due to the smaller number of available
pins.
All devices operate with a high-frequency crystal as the main
clock source. Some packages allow the device to operate
with either the main clock source or with a slow (32.768 KHz)
oscillator in Power Save mode. The device supports several
Power Save modes which are combined with multi-source in-
terrupt and wake-up capabilities.
Powerful cross-development tools are available from Nation-
al Semiconductor and third party suppliers to support the de-
velopment and debugging of application software for the
device. These tools let you program the application software
in C and are designed to take full advantage of the Compac-
tRISC architecture.
2.0 Features
•CPU Features
—Fully static core, capable of operating at any rate from
0 to 20 MHz (4 MHz minimum in active mode)
—50 ns instruction cycle time with a 20 MHz external
clock frequency
—Multi-source vectored interrupts (internal, external,
and on-chip peripheral)
—On-chip power-on reset
•On-Chip Memory
—48 kbytes of flash program memory or ROM memory
(100K cycle)
—1.5 kbytes of ISP memory (100K cycle)
—2 kbytes of static RAM data memory
—640 bytes of non-volatile EEPROM data memory,
word-programmable (100K cycle)
•On-Chip Peripherals
—Up to two Universal Synchronous/Asynchronous Re-
ceiver/Transmitter (USART) devices
—Programmable Idle Timer and real-time clock (T0)
—Up to two dual 16-bit multi-function timers (MFT1 and
MFT2)
—SPI/MICROWIRE-PLUS serial interface
—8-channel, 8-bit Analog-to-Digital (A/D) converter with
external voltage reference, programmable sample-
and-hold delay, and programmable conversion fre-
quency
—Up to two analog comparators
—Integrated WATCHDOG logic
•I/O Features
—Up to 48 general-purpose I/O pins (shared with on-chip
peripheral I/O pins)
—Programmable I/O pin characteristics: TRI-STATE out-
put, push-pull output, weak pull-up input, high-imped-
ance input
—Software-configurable Schmitt triggers on inputs
•Power Supply
—4.5V to 5.5V single-supply operation
•Temperature Range
—0°C to +70°C
—–40°C to +85°C
—–40°C to +125°C
•Development Support
—Real-time emulation and full program debug capabili-
ties available
—CompactRISC tools provide C programming and de-
bugging support
Obsolete
www.national.com 4
CR16 CompactRISC microcontroller Family Selection Guide
Programmable devices
ROM devices
Note: All devices contains Clock and Reset, MICROWIRE/
API, Multi-Input Wake-Up (MIWU), Power Management
(PMM), and the Real-Time Timer and Watchdog (TWM) mod-
ules.
44-Pin PLCC versus 80-Pin PQFP
For 44PLCC packages, MICROWIRE/SPI slave mode, the
first 4 MIWU channels and the Vref pin are not available. 80-
pin PQFP packages provide the MICROWIRE/SPI master
and slave modes, 8 MIWU channels, Vref pin, and two US-
ARTs and two MFTs.
NSID Speed
(MHz)
Flash/
ROM
(kByte)
EEPROM
Data
Memory
(Bytes)
SRAM
(kBytes) USART Timer I/Os Temp.
Range Peripherals Package
Type
CR16MHS9VJEx 20 48 640 2 2 2 48 E, I ADC,
Comparators 80PQFP
CR16MFS944Vx 20 48 640 2 2 1 33 E, I ADC 44PLCC
CR16MES944Vx 20 48 640 2 1 2 33 E, I ADC 44PLCC
CR16MNS944Vx 20 48 None 2 1 2 33 C, I None 44PLCC
CR16MUS944Vx 8 48 None 2 1 2 33 CNone 44PLCC
NSID Speed
(MHz)
Flash/
ROM
(kByte)
EEPROM
Data
Memory
(Bytes)
SRAM
(kBytes) USART Timer I/Os Temp.
Range Peripherals Package
Type
CR16MHS5VJExy 20 48 640 2 2 2 48 E, I ADC,
Comparators 80PQFP
CR16MFS544Vxy 20 48 640 2 2 1 33 E, I ADC 44PLCC
CR16MES544Vxy 20 48 640 2 1 2 33 E, I ADC 44PLCC
CR16MPS544Vxy 20 48 None 2 1 2 33 C, I ADC 44PLCC
CR16MNS544Vxy 20 48 None 2 1 2 33 C, I None 44PLCC
CR16MUS544Vxy 8 48 None 2 1 2 33 CNone 44PLCC
Note:
•Suffix x in the NSID is defined below:
Temperature Ranges:
E = Extended
I = Industrial
C = Commercial
•Suffix y in the NSID defines the ROM code.
-40°C to +125°C is represented when x is 7
-40°C to +85°C is represented when x is 8
0°C to +70°C is represented when x is 9
Obsolete
5www.national.com
3.0 Device Overview
The family of CompactRISC 16-bit microcontrollers are com-
plete microcomputers with all system timing, interrupt logic,
program memory, data memory, and I/O ports included on-
chip, making it well-suited to a wide range of embedded con-
troller applications.
3.1 CR16B CPU CORE
The device uses the CR16B CPU core module. This is the
same core used in other CompactRISC family members.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the device
differs in the following ways:
•The CPU core uses on-chip rather than external memory.
This eliminates the need for large and complex bus inter-
face units.
•Most instructions are 16 bits, so all basic instructions are
just two bytes long. (Additional bytes are sometimes re-
quired for immediate values, so instructions can be two or
four bytes long.)
•Non-aligned word access is allowed. Each instruction can
operate on 8-bit or 16-bit.
•The device is designed to operate with a clock rate in the
10 to 25 MHz range rather than 100 MHz or more. Most
embedded systems face EMI and noise constraints that
limit clock speed to these lower ranges. A lower clock
speed means a simpler, less costly silicon implementa-
tion.
•The instruction pipeline uses three stages. A smaller pipe-
line eliminates the need for costly branch prediction
mechanisms and bypass registers, while maintaining ad-
equate performance for typical embedded controller ap-
plications.
3.2 MEMORY
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The device implementation of
this architecture uses only the lowest 64 kbytes of address
space. Four types of on-chip memory occupy specific inter-
vals within this address space: 48 kbytes of flash program
memory, 1.5 kbytes of ISP memory, 2 kbytes of static RAM,
and 640 bytes of EEPROM data memory.
The 48 kbytes of flash program memory are used to store the
application program. It has security features to prevent unin-
tentional programming and to prevent unauthorized access
to the program code. This memory can be programmed ei-
ther with the device plugged into an EPROM programmer
unit (external programming) or with the device installed in the
application system (in-system programming).
The 2 kbytes of static RAM are used for temporary storage of
data and for the program stack and interrupt stack. Read and
write operations can be byte-wide or word-wide, depending
on the instruction executed by the CPU. Each memory ac-
cess requires one clock cycle; no wait cycles or hold cycles
are required.
The 640 bytes of EEPROM data memory are used for non-
volatile storage of data, such as configuration settings en-
tered by the end-user. The CPU reads or writes this memory
by using ordinary byte-wide or word-wide memory access
commands. After the CPU performs a write to this memory,
the on-chip hardware completes the EEPROM programming
in the background. A register status bit indicates the status of
the EEPROM programming operation.
There is a factory programmed boot memory used to store
In-System-Programming (ISP) code. (this code allows pro-
gramming of the program memory via one of the USART in-
terfaces in the final application.)
For the flash program memory, the device internally gener-
ates the necessary voltages for programming. No additional
power supply is required.
3.3 INPUT/OUTPUT PORTS
Each device has 48 software-configurable I/O pins, orga-
nized into six 8-pin ports called Port B, Port C, Port F, Port G,
Port L, and Port I. Each pin can be configured to operate as
a general-purpose input or general-purpose output. In addi-
tion, many I/O pins can be configured to operate as a desig-
nated input or output for an on-chip peripheral module such
as the USART, timer, A/D converter, or MICROWIRE/SPI in-
terface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input. In-
put pins can be software-configured to use Schmitt triggers
for noise resistance.
Each 44-pin device has a subset of the pins available in the
80-pin device. This results in the loss of some features that
are available in the larger-package device:
•One of the two USARTs or one of the two multi-function
timers (depending on package selection)
•Synchronous mode in the remaining USART(s)
•Slave mode operation for the MICROWIRE/SPI interface
•Separate external VREF for the A/D converter
•Comparators
•Four of the eight Multi-Input Wakeup pins
•NMI interrupt input pin
3.4 BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing EEPROM memory. Upon start-up of the device,
these registers must be programmed with appropriate values
so that the minimum allowable number states is used. This
number varies with the clock frequency and the type of on-
chip device being accessed.
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3.5 INTERRUPTS
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. An interrupt is an event that temporarily stops the
normal flow of program execution and causes a separate in-
terrupt service routine to be executed. After the interrupt is
serviced, CPU execution continues with the next instruction
in the program following the point of interruption.
Interrupts from the timers, USARTs, MICROWIRE/SPI inter-
face, multi-input wake-up, and A/D converter are all
maskable interrupts; they can be enabled or disabled by the
software. There are 16 of these maskable interrupts, orga-
nized into 16 predetermined levels of priority.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI in-
put pin. This interrupt is not available in the 44-pin packages.
3.6 MULTI-INPUT WAKE-UP
The Multi-Input Wake-up (MIWU) module can be used for ei-
ther of two purposes: to provide inputs for waking up (exiting)
from the HALT, IDLE, or Power Save mode; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. This eight-channel module generates one
combined interrupt to the CPU based on the signals received
on its eight input channels. Channels can be individually en-
abled or disabled, and programmed to respond to positive or
negative edges.
3.7 DUAL CLOCK AND RESET
The Dual Clock and Reset (CLK2RES) module generates a
high-speed main system clock from an external crystal net-
work. It also provides the main system reset signal and a
power-on reset function.
In the 80-pin package, the module also generates a slow sys-
tem clock (32.768 KHz) from another external crystal net-
work. The slow clock is used for operating the device in
power-save mode. For the 44-pin devices and for devices not
using a secondary crystal network, the slow clock can be
generated by dividing the high-speed main clock by a pres-
caler factor.
3.8 POWER MANAGEMENT
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode (and
therefore the power consumption) according to the current
level of activity.
The device can operate in any of four power modes:
•Active: The device operates at full speed using the high-
frequency clock. All device functions are fully operational.
•Power Save: The device operates at reduced speed using
the slow clock. The CPU and some modules can continue
to operate at this low speed.
•IDLE: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the slow clock.
•HALT: The device is inactive but still retains its internal
state (RAM and register contents).
3.9 MULTI-FUNCTION TIMER
The Multi-Function Timer (MFT16) module contains two inde-
pendent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counter registers. Each timer/
counter unit can be configured to operate in any of the follow-
ing modes:
•Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter
•Dual Input Capture mode, which measures the elapsed
time between occurrences of external events, and which
also provides a general-purpose timer/counter
•Dual Independent Timer mode, which generates system
timing signals or counts occurrences of external events
•Single Input Capture and Single Timer mode, which pro-
vides one external event counter and one system timer
3.10 REAL-TIME TIMER AND WATCHDOG
The Timing and Watchdog Module (TWM) generates the
clocks and interrupts used for timing periodic functions in the
system. It also provides Watchdog protection against soft-
ware errors. The module operates on the slow (32.768 KHz)
clock.
The real-time timer generates a periodic interrupt to the CPU
at a software-programmed interval. This can be used for real-
time functions such as a time-of-day clock.
The Watchdog is designed to detect program execution er-
rors such as an infinite loop or a “runaway” program. Once
Watchdog operation is initiated, the application program
must periodically write a specific value to a Watchdog regis-
ter, within specific time intervals. If the software fails to do so,
a Watchdog error is triggered, which resets the device.
3.11 USART
The USART is a Universal Synchronous/Asynchronous Re-
ceiver-Transmitter, a device used for serial communications.
It supports a wide range of programmable baud rates and
data formats, and handles parity generation and several er-
ror detection schemes. The baud rate is generated on-chip,
under software control.
The synchronous mode of operation is not available in the
44-pin devices.
3.12 MICROWIRE/SPI
The MICROWIRE/SPI (MWSPI) interface module supports
asynchronous serial communications with other devices that
conform to MICROWIRE or Serial Peripheral Interface (SPI)
specifications.
The MICROWIRE interface allows several devices to com-
municate over a single system consisting of three wires: se-
rial in, serial out, and shift clock. At any given time, one
device on the MICROWIRE interface operates as the master,
while all other devices operate as slaves. An 80-pin device
supports the full set of slave select and Ready lines for multi-
slave implementation, while a 44-pin device has only the ba-
sic Data-in/Data-out/Clock lines, limiting its implementation
to master mode.
Obsolete
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3.13 A/D CONVERTER
The A/D Converter (ADC) module is an 8-channel multi-
plexed-input analog-to-digital converter. The A/D Converter
receives an analog voltage signal on an input pin and con-
verts the analog signal into an 8-bit digital value using suc-
cessive approximation. The CPU can then read the result
from a memory-mapped register. The module supports four
automated operating modes, providing single-channel or
scanned 4-channel operation in single or continuous mode.
The 80-pin device has a separate pin, Vref, for the A/D refer-
ence voltage. The 44-pin devices use the AVCC (analog
VCC) power supply pin as the reference voltage.
3.14 ANALOG COMPARATORS
The Dual Analog Comparator (ACMP2) module contains two
independent analog comparators with all necessary control
logic. Each comparator unit compares the analog input volt-
ages applied to two input pins and determines which voltage
is higher. The CPU uses a memory-mapped register to con-
trol the comparator and to obtain the comparison results. The
comparison result can also be applied to comparator output
pins.
3.15 DEVELOPMENT SUPPORT
A powerful cross-development tool set is available from Na-
tional Semiconductor and third parties to support the devel-
opment and debugging of application software for the device.
The tool set lets you program the application software in C
and is designed to take full advantage of the CompactRISC
architecture.
There are In-System Emulation (ISE) devices available for
the device from iSYSTEM™, as well as lower-cost evaluation
boards. See your National Semiconductor sales representa-
tive for current information on availability of various features
of emulation equipment and evaluation boards.
Obsolete
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Table 1Package Pin Assignments
Pin Name Alternate Function(s) 44-pin PLCC
Package
Pin Number
80-pin PQFP
Package
Pin Number Type
GND 44 13 PWR
Vcc 1 14 PWR
GND N/A 15 PWR
ENV0-44/SLCLKa2N/A I/O
PC0 3 17 I/O
PC1 4 18 I/O
PC2 5 19 I/O
PC3 6 20 I/O
PC4 7 21 I/O
PC5 8 22 I/O
PC6 9 23 I/O
PC7 10 24 I/O
ENV0-80/SLCLKaN/A 26 I/O
CLKOUT2b11 27 I/O
ENV1/CLKa11 28 I/O
PG7 CKX1 N/A 29 I/O
PG6 TDX1 12 30 I/O
PG5 RDX1 13 31 I/O
PG4 MRDY N/A 32 I/O
PG3 MCS N/A 33 I/O
PG2 MSK 14 34 I/O
PG1 MDODI 15 35 I/O
PG0 MDIDO 16 36 I/O
PF7 N/A 38 I/O
PF6 CKX2 N/A 39 I/O
PF5 T2B 17 40 I/O
PF4 T2A 18 41 I/O
PF3cTDX2 19 or N/A * 42 I/O
PF2cRDX2 20 or N/A * 43 I/O
PF1cT1B N/A or 19 * 44 I/O
PF0cT1A N/A or 20 * 45 I/O
NMI N/A 46 I
X1CKO 21 48 O
X1CKI 22 49 I
GND N/A 50 PWR
Vcc 23 51 PWR
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GND 24 52 PWR
X2CKO N/A 53 O
X2CKI N/A 54 I
PI0 ACH0e,f 25 57 I/O
PI1 ACH1e,f 26 58 I/O
PI2 ACH2e,f 27 59 I/O
PI3 ACH3e,f 28 60 I/O
PI4 ACH4e,f, MIWU4 29 61 I/O
PI5 ACH5e,f, MIWU5 30 62 I/O
PI6 ACH6e,f, MIWU6 31 63 I/O
PI7 ACH7e,f, MIWU7 32 64 I/O
Vref N/A 66 PWR
AVcc 33f67 PWR
AGND 34f68 PWR
GND N/A 69 PWR
Vcc N/A 70 PWR
GND N/A 71 PWR
RESETd35 76 I
PB0 36 77 I/O
PB1 37 78 I/O
PB2 38 79 I/O
PB3 39 80 I/O
PB4 40 1I/O
PB5 41 2I/O
PB6 42 3I/O
PB7 43 4I/O
PL0 COMP1NeN/A 73 I/O
PL1 COMP1PeN/A 74 I/O
PL2 COMP1O N/A 5I/O
PL3 N/A 6I/O
PL4 COMP2Ne, MIWU0 N/A 8I/O
PL5 COMP2Pe, MIWU1 N/A 9I/O
Table 1Package Pin Assignments
Pin Name Alternate Function(s) 44-pin PLCC
Package
Pin Number
80-pin PQFP
Package
Pin Number Type
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PL6 COMP2O, MIWU2 N/A 11 I/O
PL7 MIWU3 N/A 12 I/O
Notes:
a.The ENV0 and ENV1 pins each have a weak pullup to keep the input from floating.
b.The CLKOUT2 function is shared with the ENV1/CLK pin in the 44-pin device.
c. In the 44-pin CR16MES, CR16MNS, CR16MPS, and CR16MUS packages, PF1 and PF0 are available; PF3 and PF2 are
not available.
In the 44-pin CR16MFS, CR16MOS, CR16MQS, and CR16MVS packages, PF3 and PF2 are available; PF1 and PF0 are
not available.
d.The RESET input has a weak pulldown.
e. These functions are always enabled due to the direct low-impedance path to these pins.
f. These functions may not be available on some 44-pin devices.
Table 1Package Pin Assignments
Pin Name Alternate Function(s) 44-pin PLCC
Package
Pin Number
80-pin PQFP
Package
Pin Number Type
Obsolete
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3.16 PIN DESCRIPTION
Some pins have alternate functions which may be enabled.
These pins can be individually configured as general pur-
pose pins, even when the module they belong to is enabled.
The following is a brief description of all CR16MHR6 pins.
Table 2Input Pins
Signal Type Active Pin (* for a
shared pin) Function
X1CKI OSC High Main oscillator clock input.
X2CKI OSC High 32kHz oscillator clock input.
RESET CMOS Low Chip general reset pin. Schmitt trigger input, asynchronous.
ISE CMOS Low Interrupt input for development system.
T1B CMOS Prog. *Timer 1 input B. Shares pin with I/O port pin PF1.
T2B CMOS Prog. *Timer 2 input B. Shares pin with I/O port pin PF5.
RDX1 CMOS High *USART 1 receive data input. Shares pin with I/O port pin PG5.
RDX2 CMOS High *USART 2 receive data input. Shares pin with I/O port pin PF4.
ACH0 Analog *A2D converter channel 0. Shares pin with I/O port pin PI0
ACH1 Analog *A2D converter channel 1. Shares pin with I/O port pin PI1
ACH2 Analog *A2D converter channel 2. Shares pin with I/O port pin PI2
ACH3 Analog *A2D converter channel 3. Shares pin with I/O port pin PI3
ACH4 Analog *A2D converter channel 4. Shares pin with I/O port pin PI4
ACH5 Analog *A2D converter channel 5. Shares pin with I/O port pin PI5
ACH6 Analog *A2D converter channel 6. Shares pin with I/O port pin PI6
ACH7 Analog *A2D converter channel 7. Shares pin with I/O port pin PI7
MCS CMOS Low *SPI/MICROWIRE slave select. Shares pin with I/O port pin PG3.
NMI CMOS Low External non-maskable interrupt.
ENV0-44 CMOS Low *Strap pin on 44-pin package to select operating environment.
ENV0-80 CMOS Low *Strap pin on 80-pin package to select operating environment.
ENV1 CMOS Low *Strap pin to select operating environment.
ENV2 CMOS Low Strap pin to select operating environment.
Table 3Output Pins
Signal Type Active Pin (* for a
shared pin) Function
X1CKO OSC High Main oscillator clock output.
X2CKO OSC High 32 kHz oscillator clock output.
CLK CMOS High External reference clock for development environment.
TDX1 CMOS High *USART 1 transmit data output. Shares pin with I/O port pin PG6.
TDX2 CMOS High *USART 2 transmit data output. Shares pin with I/O port pin PF5.
MRDY CMOS Low *SPI/MICROWIRE slave ready output. Shares pin with I/O port pin PG4
CLKOUT2 OSC High System clock divided-by-2 output (shared with the ENV1 pin in the 44-pin
device)
Obsolete
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Table 4Input/Output Pins
Signal Type Active Pin (* for a
shared pin) Function
PF[0:7] CMOS High *Generic I/O port. Shared with T1A, T1B, T2A, T2B, RDX2, TDX2, CKX2.
PG[0:7] CMOS High *Generic I/O port. Shared with MDIDO, MDODI, MSK, MCS, MRDY, RDX1,
TDX1, CKX1.
PB[0:7] CMOS High *Generic I/O port.
PC[0:7] CMOS High *Generic I/O port.
PL[0:7] CMOS High *Generic I/O port. Shared with six comparator pins and four MIWU pins.
PI[0:7] CMOS High *Generic I/O port. Shared with ADC input channels 0-7 and four MIWU pins.
T1A CMOS Prog *Timer 1 input A. Shared with I/O port pin PF0.
T2A CMOS Prog *Timer 2 input A. Shared with I/O port pin PF4.
MDIDO CMOS High *Master In/Slave Out port: SPI/Microwire. Shared with I/O pin PG0.
MDODI CMOS High *Master Out/Slave In port: SPI/Microwire. Shared with I/O pin PG1.
MSK CMOS High *SPI/Microwire clock. Shared with I/O pin PG2.
CKX1 CMOS High *USART 1 clock signal. Shared with I/O pin PG7.
CKK2 CMOS High *USART 2 clock signal. Shared with I/O pin PF6.
Table 5Power Supply
Signal Function
Vcc Main digital power supply.
Vref Voltage reference supply for analog to digital converter.
AVcc Analog power supply for analog/digital converter.
AGND Analog reference ground supply.
GND Main digital reference ground.
Obsolete
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4.0 System Configuration
The CR16MHS9 has two input pins, ENV0 and ENV1, which
are used to specify the operating environment of the device
upon reset. There are also two system configuration regis-
ters, called the Module Configuration (MCFG) register and
the Module Status (MSTAT) register.
4.1 ENV0 AND ENV1 PINS
Upon reset, the operating mode of the device is determined
by the state of the ENV0 and ENV1 input pins, as indicated
in Table6.
In the case where the ENV1 and ENV0 pins are both high,
the reset algorithm looks at the FLCTRL2.EMPTY bit to de-
termine whether the program memory is empty, and sets the
operating mode accordingly.
The ENV0 and ENV1 pins have on-chip pull-up devices that
are enabled during reset while the pins are being sampled.
Therefore, if they are left unconnected, the inputs are consid-
ered high and the normal operating mode (IRE-Mode) is se-
lected and the CPU starts to execute code at address 0. To
enter any other operating mode, the external hardware must
drive the appropriate input low.
In the case where the ISP-Mode is selected, the chip starts
executing the ISP code residing in the on-chip boot ROM ar-
ea.
The Test Modes are reserved for factory testing and for ex-
ternal programming of the flash program memory; they
should not be invoked otherwise.
4.2 MODULE CONFIGURATION (MCFG)
REGISTER
The MCFG register is a byte-wide, read/write register that
sets the general programmable features of the device.
Upon reset, the non-reserved bits of this register are cleared
to zero. The start-up software must write a specific value to
this register in order to configure the CLK output pin function.
When the software writes to this register, it must write a zero
to each reserved bit for the device to operate properly. The
register should be written in active mode only, not in power
save, HALT, or IDLE mode. However, the register contents
are preserved during all power modes.
The MCFG register format is shown below.
CLKOE CPU Clock Output Enable. When this bit is
cleared (0), the CLK pin remains in the high-im-
pedance state. When this bit is set (1) in normal
operating mode, the CLK pin operates as a
CPU clock output.
SLCLKOE Slow Clock Output Enable. When cleared (0),
the SLCLK pin of the 44-pin package (ENV0-44
pin) remains in the high-impedance state.
When set (1), this pin produces the slow clock
as an output.
FEEDM Fast EEPROM Data Memory Access. This bit
is set (1) for zero-wait-state access to the EE-
PROM data memory, or cleared (0) for one-
wait-state access to the data ROM. For infor-
mation on the required number of wait states,
see Table8.
SLCOE2 Slow Clock Output Enable. When cleared (0),
the SLCLK pin of the 80-pin package (ENV0-80
pin) remains in the high-impedance state.
When set (1), this pin produces the slow clock
as an output.
CLK2OE CPU Clock Divide-by-2 Output Enable. When
this bit is cleared (0), the CLKOUT2 pin re-
mains in the high-impedance state. When this
bit is set (1) and the CLKOE bit is cleared, the
CLKOUT2 pin operates as clock output, with a
frequency of one-half that of the CPU clock.
4.3 MODULE STATUS (MSTAT) REGISTER
The MSTAT register is a byte-wide, read-only register that in-
dicates the general status of the device.
The MCFG register format is shown below.
OENV(1:0) Operating Environment. These two bits contain
the values applied to the ENV1 and ENV0 pins
upon reset. These bit values are controlled by
the external hardware upon reset and are held
constant in the register until the next reset.
PGMBUSY Flash Programming Busy. This bit is automati-
cally set to 1 when either the program memory
or the data memory is busy being programmed.
It is cleared to 0 when neither of the two flash
memories are busy being programmed. When
this bit is set, the software should not attempt
to access either of these two memories.
Table 6Operating Environment Selection
ENV1 ENV0 Operating Environment
0 0 Test Mode
0 1 Test Mode
1 0 In-System Programming mode
1 1 Internal ROM enabled Mode (IRE), if
program memory is not empty; or ISP-
Mode, if program memory is empty
7 6 5 4 3 2 1 0
Reserved CLK2OE SLCOE2 FEEDM SLCLKOE CLKOE Reserved
743 2 1 0
Reserved PGMBUSY Reserved OENV1 OENV0
Obsolete
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5.0 Input/Output Ports
Each device has up to 48 software-configurable I/O pins, or-
ganized into six ports of up to eight pins per port. The exact
number of port pins varies with the package type. The ports
are named Port B, Port C, Port F, Port G, Port L, and Port I.
Each pin can be configured to operate as a general-purpose
input or general-purpose output. In addition, many I/O pins
can be configured to operate as a designated input or output
for an on-chip peripheral module such as the USART. This is
called the pin's “alternate function.” The alternate functions of
all I/O pins are shown in the pinout diagrams in Table1.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input. Dif-
ferent pins within the same port can be individually config-
ured to operate in different modes.
Figure1 is a diagram showing the functional features of an I/
O port pin. The register bits, multiplexers, and buffers allow
the port pin to be configured into the various operating
modes.The output buffer is a TRI-STATE buffer with weak
pull-up capability. The weak pull-up, if used, prevents the port
pin from going to an undefined state when it operates as an
input.
The input buffer is disabled when it is not needed to prevent
leakage current. When enabled, it buffers the input signal
and sends the pin's logic level to the appropriate on-chip
module where it is latched. A Schmitt trigger, when enabled,
minimizes the effects of electrical noise.
The electrical characteristics and drive capabilities of the in-
put and output buffers are described in Section21.0.
For some pins, a direct low-impedance path is provided be-
tween the pin and an internal analog function. These are the
input pins to the A/D converter and the analog comparators
5.1 PORT REGISTERS
Each port has an associated set of memory-mapped regis-
ters used for controlling the port and for holding the port data.
In general, there are six such registers:
•PxALT: Port alternate function register
•PxDIR: Port direction register
•PxDIN: Port data input register
•PxDOUT: Port data output register
•PxWKPU: Port weak pull-up register
•PxSCHEN: Port Schmitt trigger enable register
In the descriptions of the ports and port registers, the lower-
case letter “x” represents the port designation, either B, C, F,
G, L, or I. For example, “PxDIR register” means any one of
the port direction registers: PBDIR, PCDIR, PFDIR, and so
on.
All of the port registers are byte-wide read/write registers, ex-
cept for the port data input registers, which are read-only reg-
isters. Each register bit controls the function of the
corresponding port pin. For example, PFDIR.2 (bit 2 of the
PFDIR register) controls the operation of port pin PF2.
Figure 1.I/O Pin Functional Diagram
PIN
Direction
Data Out
Register {
Direction
Register {
Weak pull-up
Register {
Data Input
MUX1
MUX2
Weak pull-up
Data Out
Alt Device Data Output
Alt
Alt
Alt Device Direction
Data In Read Strobe
Alt
MUX2
Alt 1
Analog Input
Alt. Function
{
Alternate Func.
Register
Alternate Data Input
*
* Schmitt trigger is used at input when enabled or when the pin’s alternate function is selected.
Schmitt Enable
Obsolete
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5.1.1 Port Alternate Function Register
Each port that supports an alternate function (any port other
than Port B or Port C) has an alternate function register (Px-
ALT). This register determines whether the port pins are used
for general-purpose I/O or for the predetermined alternate
function. Each port pin can be controlled independently.
A bit cleared to 0 in the alternate function register causes the
corresponding pin to be used for general-purpose I/O. In this
configuration, the output buffer is controlled by the direction
register and the data output register. The input buffer is rout-
ed to the data input register. The input buffer is blocked ex-
cept when the buffer is actually being read.
A bit set to 1 in the alternate function register causes the cor-
responding pin to be used for its predetermined peripheral I/
O function. The output buffer data and TRI-STATE configura-
tion are controlled by signals coming from the on-chip periph-
eral device. The input buffer is enabled continuously in this
case. To minimize power consumption, the input signal
should be held within 0.2 volts of the VCC or GND voltage.
A reset operation clears the port alternate function registers
to 0, which programs the pins to operate as general-purpose
I/O ports. This register must be enabled before the corre-
sponding alternate function is enabled.
5.1.2 Port Direction Register
The port direction register (PxDIR) determines whether each
port pin is used for input or for output. A bit cleared to 0 caus-
es the pin to operate as an input, which puts the output buffer
in the high-impedance state. A bit set to 1 causes the pin to
operate as an output, which enables the output buffer.
A reset operation clears the port direction registers to 0,
which programs the pins to operate as inputs.
5.1.3 Port Data Input Register
The data input register (PxDIN) is a read-only register that re-
turns the current state of each port pin. The CPU can read
this register at any time even when the pin is configured as
an output.
5.1.4 Port Data Output Register
The data output register (PxDOUT) holds the data to be driv-
en onto each port pin configured to operate as a general-pur-
pose output. In this configuration, writing to the register
changes the output value. Reading the register returns the
last value written to the register.
A reset operation leaves the register contents unchanged.
Upon power-up, the registers contain unknown values.
5.1.5 Port Weak Pull-Up Register
The weak pull-up register (PxWKPU) determines whether
each port pin uses a weak pull-up on the output buffer. A bit
set to 1 causes the weak pull-up to be used, while a bit
cleared to 0 causes the weak pull-up not to be used.
The pull-up device, if enabled by the register bit, operates in
the general-purpose I/O mode whenever the port output buff-
er is in the TRI-STATE mode. In the alternate function mode,
the pull-ups are always disabled.
A reset operation clears the port weak pull-up registers to 0,
which disables all pull-ups.
5.1.6 Port Schmitt Input Enable Register
PxSCHEN registers are byte-wide read/write registers. They
enable the Schmitt trigger characteristics on Px input buffers
when these pins are used as general purpose I/O ports.
When cleared (0) with the pins used as general purpose I/O
ports, each bit in PxSCHEN enables the corresponding input
buffer only when the port is read, and therefore the input buff-
er may not exhibit any Schmitt trigger behavior. When set (1),
the input buffer is enabled, and will exhibit Schmitt trigger be-
havior. PxSCHEN registers are cleared upon reset.
5.2 OPEN-DRAIN OPERATION
A port pin can be configured to operate as an inverting open-
drain output buffer. To do this, the CPU should clear the bit in
the data output register (PxDOUT) and then use the port di-
rection register (PxDIR) to set the value of the port pin. With
the direction register bit set to 1 (direction=out), the value
zero is forced on the pin. With the direction register bit
cleared to 0 (direction=in), the pin is placed in the TRI-STATE
mode. If desired, the internal weak pull-up can be enabled to
pull the signal high when the output buffer is in the TRI-
STATE mode.
Obsolete
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6.0 CPU and Core Registers
The device uses the same CR16B CPU core as other Com-
pactRISC family members. The core's Reduced Instruction
Set Computer (RISC) architecture allows a processing rate of
up to one instruction per clock cycle.
The CPU core uses the following set of internal registers:
•General-purpose registers (R0-R13, RA, and SP)
•Dedicated address registers (PC, ISP, and INTBASE)
•Processor Status Register (PSR)
•Configuration Register (CFG)
All of these registers are 16 bits wide except for the three ad-
dress registers, which are 21 bits wide.
Some register bits are designated as “reserved.” The CPU
must write a zero to each of these bit locations when it writes
to the register. Read operations from reserved bit locations
return undefined values.
6.1 GENERAL-PURPOSE REGISTERS
There are 16 general-purpose registers, designated R0
through R13, RA, and SP. Registers R0 through R13 can be
used for any purpose such as holding variables, addresses,
or index values. The RA register is usually used to store the
return address upon entry into a subroutine. The SP register
is usually used as the pointer to the program run-time stack.
If a general-purpose register is used for a byte-wide opera-
tion, only the low-order byte is referenced or modified. The
high-order byte is not used or affected by a byte-wide opera-
tion.
6.2 DEDICATED ADDRESS REGISTERS
There are three dedicated address registers: the Program
Counter (PC), the Interrupt Stack Pointer (ISP), and the Inter-
rupt Base Register (INTBASE). Each of these registers is 21
bits wide.
6.2.1 Program Counter
The PC register contains the address of the first byte of the
instruction currently being executed. It is automatically incre-
mented or changed by the appropriate amount each time an
instruction is executed.
The five most significant and the least significant bit of this
register are always zero. The least significant bit of the PC is
always zero, thus instruction must always be aligned to even
addresses in the range of 0000 to FFFE hex.
Upon reset, the PC register is initialized to zero and program
execution starts at that address. When a reset signal is re-
ceived, bits 1 through 16 of the PC register (prior to initializa-
tion) are stored in register R0. This allows the software to
determine the point in the program at which the reset oc-
curred.
6.2.2 Interrupt Stack Pointer
The ISP register points to the lowest address of the last item
stored on the interrupt stack. This stack is used by the hard-
ware when an interrupt or trap service procedure is invoked.
The five most significant bits and the least significant bit of
this register are always zero. The last item stored on the in-
terrupt stack must be at an even address in the range of
E000-E7FF hex, which is the range of the RAM memory in
which the stack resides.
6.2.3 Interrupt Base Register
The INTBASE register holds the address of the Dispatch Ta-
ble for interrupts and traps. The five most significant bits and
the least significant bit of this register are always zero.
6.3 PROCESSOR STATUS REGISTER
The Processor Status Register (PSR) holds status informa-
tion and selects the operating modes for the CPU core. The
format of the register is shown below.
C bit The Carry (C) bit indicates whether a carry or
borrow has occurred after addition or subtrac-
tion. It is set to 1 if a carry or borrow has oc-
curred, or cleared to 0 otherwise.
T bit The Trace (T) bit, when set, causes a Trace
(TRC) trap to be executed after every instruc-
tion. This bit is automatically cleared to 0 when
a trap or interrupt occurs.
L bit The Low (L) bit is set by comparison opera-
tions. In a comparison of unsigned integers, the
bit is set to 1 if the second operand (Rdest) is
less than the first operand (Rsrc). Otherwise, it
is cleared to 0.
F bit The Flag (F) bit is a general condition flag that
is set by various instructions. It may be used to
signal exception conditions or to distinguish the
results of an instruction. For example, integer
arithmetic instructions use this bit to indicate an
overflow condition after an addition or subtrac-
tion operation.
Z bit The Zero (Z) bit is set by comparison opera-
tions. In a comparison of integers, the bit is set
to 1 if the two operands are equal. Otherwise,
it is cleared to 0.
N bit The Negative (N) bit is set by comparison oper-
ations. In a comparison of signed integers, the
bit is set to 1 if the second operand (Rdest) is
less than the first operand (Rsrc). Otherwise, it
is cleared to 0.
E bit The Local Maskable Interrupt Enable (E) bit is
used to enable or disable maskable interrupts.
If this bit and the Global Maskable Interrupt En-
able (I) bit are both set to 1, all maskable inter-
rupts are accepted. Otherwise, only non-
maskable interrupts are accepted. The E bit is
set to 1 by the Enable Interrupts (EI) instruction
and cleared to 0 by the Disable Interrupts (DI)
instruction.
P bit The Trace Trap Pending (P) bit is used together
with the Trace (T) bit to prevent a Trace (TRC)
trap from occurring more than once for any in-
struction. The P bit may be cleared to 0 (no
TRC trap pending) or set to 1 (TRC trap pend-
ing).
15 14 13 12 11 10 9876543210
Reserved IPE0NZ F 00LTC
Obsolete
17 www.national.com
I bit The Global Maskable Interrupt Enable (I) bit is
used to enable or disable maskable interrupts.
If this bit and the Local Maskable Interrupt En-
able (E) bit are both set to 1, all maskable inter-
rupts are accepted. Otherwise, only the non-
maskable interrupts are accepted. This bit is
automatically cleared to 0 when an interrupt oc-
curs and automatically set to 1 upon comple-
tion of an interrupt service routine.
Upon reset, all non-reserved bits of the register are cleared
to 0 except for the E bit (bit 9), which is set to 1. When a de-
vice reset occurs, the PSR contents prior to the reset are
stored into register R1, allowing the initialization software to
determine the state of the device prior to the reset operation.
6.4 CONFIGURATION REGISTER
The Configuration (CFG) register is a 16-bit core register that
determines the size of the INTBASE register. For the device,
the CFG register should always be left in its default state
(cleared to zero), resulting in a 16-bit INTBASE register.
6.5 ADDRESSING MODES
Each instruction operates on one or more operands. An op-
erand can be a register or a memory location.
Most instructions use one, two, or three device registers as
operands. The instruction opcode specifies the registers to
be operated on. Some instructions may use an immediate
value (a value provided in the instruction itself) instead of a
register.
Memory locations are accessed only by the Load and Store
commands. The memory location to use for a particular in-
struction can be specified as an absolute, relative, or far-rel-
ative address.
The instruction set supports the following addressing modes:
For additional information on the instruction set and instruc-
tion encoding, see the CompactRISC CR16B Programmer's
Reference manual.
6.6 STACKS
A stack is a one-dimensional data buffer in which values are
entered and removed one at a time. The last value entered is
the first one removed. A register called the stack pointer con-
tains the current address of the last item entered on the
stack. In the device, when an item is entered or “pushed”
onto the stack, the stack expands downward in memory (the
stack pointer is decremented). When an item is removed or
“popped” from the stack, the stack shrinks upward in memory
(the stack pointer is incremented).
The device uses two type of stacks: the program stack and
the interrupt stack.
The program stack is used by the software to save and re-
store register values upon entry into and exit from a subrou-
tine. The software can also use the program stack to store
local and temporary variables. The stack pointer for this
stack is the SP register.
The interrupt stack is used to save and restore the program
state when an exception occurs (an interrupt or software
trap). The on-chip hardware automatically pushes the pro-
gram state information onto the stack before the exception
service procedure is executed. Upon exit from the exception
service procedure, the hardware pops this information from
the stack and restores the program state. The stack pointer
for this stack is the ISP, or Interrupt Stack Pointer.
6.7 INSTRUCTION SET
Table7 is a summary list of all instructions in the device in-
struction set. For each instruction, the table shows the mne-
monic with a brief description of the operation performed.
In the Mnemonic column, the lower-case letter “i” is used to
indicate the type of integer that the instruction operates on,
either “B” for byte or “W” for word. For example, the notation
ADDi for the “add” instruction means that there are two forms
of this instruction, ADDB and ADDW, which operate on bytes
and words, respectively.
Similarly, the lower-case string “cond” is used to indicate the
type of condition tested by the instruction. For example, the
notation Jcond represents a class of conditional jump instruc-
Register Mode The operand is a general-purpose regis-
ter: R0 through R13, RA, or SP. For exam-
ple:
ADDB R1, R2
Immediate
Mode A constant operand value is specified with-
in the instruction. In a branch instruction,
the immediate operand is a displacement
from the program counter (PC). In the as-
sembly language syntax, a dollar sign indi-
cates an immediate value. For example:
MULW $4, R4
Relative Mode The operand is located in memory. Its ad-
dress is obtained by adding the contents of
a general purpose register to the constant
value encoded into the displacement field
of the instruction. For example:
LOADW 12(R5), R6
Far-Relative
Mode The operand is located in memory. Its ad-
dress is obtained by concatenating a pair
of adjacent general-purpose registers to
form a 21-bit value, and adding this value
to the constant value encoded into the dis-
placement field of the instruction. The de-
vice implementation only uses the first 64K
of the address space, so the relative mode
is sufficient to access the entire usable ad-
dress space; the far-relative mode is not
used.
Absolute Mode The operand is located in memory. Its ad-
dress is specified within the instruction.
For example:
LOADB 4000, R6
Obsolete
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tions: JEQ for Jump on Equal, JNE for Jump on Not Equal,
and so on.
For detailed information on all instructions, see the
CompactRISC CR16B Programmer's Reference manual.
Table 7Device Instruction Set Summary
Mnemonic Description
ADDi Add Integer
ADDUi Add Unsigned Integer
ADDCi Add Integer with Carry
ANDi Bitwise Logical AND
ASHUi Arithmetic Shift Unsigned
Bcond Conditional Branch
Bcond0i Compare Register to 0 and Branch
Bcond1i Compare Register to 1and Branch
BAL Branch and Link
BR Unconditional Branch
CBITi Clear Bit in Integer
CMPi Compare Integer
DI Disable Maskable Interrupts
EI Enable Maskable Interrupts
EIWAIT Enable Interrupts and Wait for Interrupt
EXCP Exception
Jcond Conditional Jump
JAL Jump and Link
JUMP Jump
LOADi Load Integer
LOADM Load Multiple Registers
LPR Load Processor Register
LSHi Logical Shift Integer
MOVi Move Integer
MOVXB Move with Sign-Extension
MOVZB Move with Zero-Extension
MULi Multiply Integer
MULSi Multiply Signed
MULUW Multiply Unsigned
NOP No Operation
ORi Bitwise Logical OR
POPrt Pop Registers from Stack
PUSH Push Registers on Stack
RETX Return from Exception
Scond Save Condition as Boolean
MULi Multiply Integer
SBITi Set Bit in Integer
STORi Store Integer
STORM Store Registers to Memory
SUBi Subtract Integer
SUBCi Subtract Integer with Carry
TBIT Test Bit
WAIT Wait for Interrupt
XORi Bitwise Logical Exclusive OR
Table 7Device Instruction Set Summary
Mnemonic Description
Obsolete
19 www.national.com
7.0 Bus Interface Unit
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules and the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for the requested access.
7.1 BUS CYCLES
There are four types of data transfer bus cycles:
•Normal read
•Fast read
•Early write
•Late write
Note: For write operations, this device utilizes the Late write
operation.
The type of data cycle used in a particular transaction de-
pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write or
normal/fast read).
For read operations, a basic normal read takes two clock cy-
cles, whereas a fast read bus cycle takes one clock cycle.
Upon reset of the device, normal read bus cycles are en-
abled by default.
For write operations, a basic late write bus cycle takes two
clock cycles, whereas a basic early write bus cycle takes
three clock cycles. Upon reset of the device, early write bus
cycles are enabled by default. However, late write bus cycles
are needed for ordinary write operations, so this configura-
tion should be changed by the application software (see
Section7.2.1).
In certain cases, one or more additional clock cycles are add-
ed to a bus access cycle. There are two types of additional
clock cycles for ordinary memory accesses, called internal
wait cycles (TIW) and hold (Thold) cycles.
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request. A hold cycle is inserted at the end of a bus cycle.
This holds the data on the data bus for an extended number
of clock cycles.
7.2 BIU CONTROL REGISTERS
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access-
ing memory. Upon start-up of the device, these registers
should be programmed with appropriate values so that the
minimum allowable number of cycles is used. This number
varies with the clock frequency used.
There are two applicable BIU registers: the BIU Configura-
tion (BCFG) register and the Static Zone 0 Configuration
(SZCFG0) register. These registers control the bus cycle
configuration used for accessing the flash program memory.
Note: A system configuration register called the Module
Configuration (MCFG) register controls the number of wait
cycles used for accessing the EEPROM data memory. This
register is described in Section4.2.
7.2.1 BIU Configuration (BCFG) Register
The BIU Configuration (BCFG) Register is a byte-wide, read/
write register that selects either early write or late write bus
cycles. The register address is F900 hex. Upon reset, the
register is initialized to 07 hex. The register format is shown
below.
EWR Early Write. This bit is cleared to 0 for late write
operation (two clock cycles to write) or set to 1
for early write operation.
Note 1: This bit (bit 1 or bit 2) controls the configuration of the
224-pin device used in emulation equipment. The CPU
should set this bit to 1 when it writes to the register.
Upon reset, the BCFG register is initialized to 07 hex, which
selects early write operation. However, late write operation is
required for normal device operation, so the software should
change the register value to 06 hex.
7.2.2 I/O Zone Configuration (IOCFG) Register
The I/O Zone Configuration (IOCFG) register is a word-wide,
read/write register that sets the timing and bus characteris-
tics of I/O Zone memory accesses. In the device implemen-
tation, the registers associated to Port B and Port C reside in
the I/O memory array. (These ports are used as a 16-bit data
port, if the device operates in development mode.)
The IOCFG register address is F902 hex. Upon reset, the
register is initialized to 069F hex. The register format is
shown below.
WAIT Memory Wait cycles
This field specifies the number of TIW (internal
wait state) clock cycles added for each memory
access, ranging from 000 binary for no addi-
tional TIW wait cycles to 111 binary for seven
additional TIW wait cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
HOLD Memory Hold cycles
This field specifies the number of Thold clock
cycles used for each memory access, ranging
from 00 binary for no Thold cycles to 11 binary
for three Thold clock cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
BW Bus Width
BW defines the external bus width for the I/O
zone. Bus width is initialized during reset to its
default value, which is 16 bits. If this bit is
cleared to 0 the external bus is 8 bits wide. To
set to external bus width to 16 bits, this bit has
to be set to 1. For the 80 pin package the Bus
width has to be set to 1. When using the device
in 224 pin package in emulator equipment the
7 6 5 4 3 2 1 0
Reserved Note 1 Note 1 EWR
15 14 13 12 11 10 9 8
Reserved 1IPST Reserved
7 6 5 4 3 2 1 0
BW Reserved HOLD WAIT
Obsolete
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bus width may have to be set to 8 bits depend-
ing on the requirements of the external hard-
ware.
IPST Post Idle
An idle cycle follows the current bus cycle,
when the next bus cycle is in a different zone.
For the 80-pin package where all zones are on-
chip, this bit can be cleared to 0; as this addi-
tional idle-cycle is not required.
7.2.3 Static Zone 0 Configuration (SZCFG0) Register
The Static Zone 0 Configuration (SZCFG0) register is a
word-wide, read/write register that sets the timing and bus
characteristics of Zone 0 memory accesses. In the
CR16MHS9 implementation of the CompactRISC architec-
ture, Zone 0 is occupied by the flash EEPROM program
memory.
The SZCFG0 register address is F904 hex. Upon reset, the
register is initialized to 069F hex. The register format is
shown below.
WAIT Memory Wait cycles
This field specifies the number of TIW (internal
wait state) clock cycles added for each memory
access, ranging from 000 binary for no addi-
tional TIW wait cycles to 111 binary for seven
additional TIW wait cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
HOLD Memory Hold cycles
This field specifies the number of Thold clock
cycles used for each memory access, ranging
from 00 binary for no Thold cycles to 11 binary
for three Thold clock cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
BW BW defines the external bus width for the zone.
Bus width is initialized during reset to its default
value, which is 16 bits. If this bit is cleared to 0
the external bus is 8 bits wide. To set to exter-
nal bus width to 16 bits, this bit has to be set to
1. For the 80 pin package the Bus width has to
be set to 1.
IPST Post Idle
An idle cycle follows the current bus cycle,
when the next bus cycle is in a different zone.
For the 80-pin package where all zones are on-
chip, this bit can be cleared to 0 as this addi-
tional idle-cycle is not required.
IPRE Preliminary Idle
An idle cycle is inserted prior to the current bus
cycle, when this bus cycle is in a new zone. For
the 80-pin package where all zones are on-
chip, this bit can be cleared to 0 as this addi-
tional idle-cycle is not required.
FRE Fast Read Enable
This bit enables (1) or disables (0) fast read bus
cycles. A fast read operation takes one clock
cycle. A normal read operation takes at least
two clock cycles.
Note 1: These bits (bit 5 and 6) control the configuration to
the 224-pin device used in emulation equipment. The CPU
should clear these bits to 0 when it writes to the register.
7.3 WAIT AND HOLD STATES USED
The number of wait cycles and hold cycles inserted into a bus
cycle depends on whether it is a read or write operation, the
type of memory or I/O being accessed, and the control regis-
ter settings.
7.3.1 Flash Program Memory
When the CPU accesses the flash program memory (ad-
dress 0000-BFFF hex), the number of added wait and hold
cycles depends on type of accesses and the BIU register set-
tings.
For a read operation in fast read mode (SZCFG0.FRE=1), no
wait cycles or hold cycles are used.
For a read operation in normal read mode (SZCFG0.FRE=0),
the number of inserted wait cycles is one plus the value writ-
ten to the SZCFG0.WAIT field. The number in this field can
range from zero to seven, so the total number of wait cycles
can range from one to eight. The number of inserted hold cy-
cles is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is one. No hold cycles are
used.
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0. WAIT field plus one (in the late write mode) or two
(in the early write mode). The number of inserted hold cycles
is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
Writing to the flash program memory is a ROM programming
operation that requires some additional steps, as explained
in Section8.3.2.
7.3.2 RAM Memory
When the CPU accesses RAM memory (address E000-
E7FF hex), no wait cycles or hold cycles are used.
7.3.3 EEPROM Data Memory
There is either no wait state or one wait state used when the
CPU accesses the EEPROM data memory (address F000-
F27F hex). The number of required wait states (zero or one)
depends on the CPU clock frequency and operating mode,
and is controlled by programming of the FEEDM bit in the
MCFG register, as explained in Section8.3. No hold cycles
are used.
7.3.4 Core Register and Peripheral Accesses
When the CPU accesses core registers and on-chip periph-
erals in the range of F000-FFFF, one wait cycle is used. No
hold cycles are used.
For the FB00-FBFF (Ports B and C) the IOCFG register de-
termines the timing.
15 14 13 12 11 10 9 8
Reserved FRE IPRE IPST Reserved
7 6 5 4 3 2 1 0
BW Note 1 HOLD WAIT
Obsolete
21 www.national.com
7.3.5 Wait/Hold Summary Table
Table8 is a summary showing the number of wait cycles and
hold cycles used for various address ranges.
7.3.6 Recommended Register Settings
Table9 shows the recommended register settings for various
clock rates. Different clock rates require different register set-
tings because the flash program memories have specific set-
up and hold requirements that can be met only by using
enough wait cycles and hold cycles.
Table 8Access Timing Table
Address
Range (hex) Memory or
I/O Type Wait Cycles Added Hold Cycles Added
0000-BFFF Flash Program
Memory For read operation: 0 if SZCFG0.FRE=1, or
1+SZCFG0.WAIT if SZCFG0.FRE=0; For
write operation: 1+BCFG.EWR if
SZCFG0.FRE=1, or
1+BCFG.EWR+SZCFG0.WAIT if
SZCFG0.FRE=0
0 if SZCFG0.FRE=1, or SZCFG0.HOLD if
SZCFG0.FRE=0
E000-E7FF Static RAM Memory 0 0
F000-F27F EEPROM Data
Memory For read operation: 0 if MCFG.FEEDM=1,
or 1 if MCFG.FEEDM=0 0
F900-FFFF
F800-F9FF
FC00-FFFF
Core Registers And
On-Chip Peripherals 1 0
FB00-FBFF Ports B and C For read operation: 1+IOCFG.WAIT
For write: 1+BCFG.EWR+IOCFG.WAIT IOCFG.HOLD
Table 9Recommended Register Settings
Clock Rate SZCFG0 IOCFG
< 12.5 MHz,
0 wait state 0E80 hex 0288 hex
12.5 to 16 MHz, 0
wait state 0E80 hex 0288 hex
12.5 to 16 MHz, 1
wait state 0680 hex 0288 hex
> 16 MHz,
1 wait state 0680 hex 0288 hex
Obsolete
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8.0 Memory
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes, addressed by 21 bits. The de-
vice implementation of this architecture uses only the lowest
64 kbytes of address space, addressed by 16 bits. Each
memory location contains a byte consisting of eight bits.
Four types of on-chip memory occupy specific intervals with-
in the address space: 48 kbytes of flash program memory,
1.5 kbytes of ISP memory, 2 kbytes of static RAM, and 640
bytes of EEPROM data memory. All of these memories are
16 bits wide, but their contents can be accessed either as
bytes (eight bits wide) or words (16 bits wide).
The CPU core uses the Load and Store instructions to ac-
cess memory. These instructions can operate on bytes or
words. For a byte access, the CPU operates on a single byte
occupying a specified memory address. For a word access,
the CPU operates on two consecutive bytes. In that case, the
specified address refers to the least significant byte of the
data value; the most significant byte is located at the next
higher address. Thus, the ordering of bytes in memory is
from least to most significant byte. For more efficient data ac-
cess operations, 16-bit variables should be stored starting at
word boundaries (at even address).
8.1 FLASH PROGRAM MEMORY
The flash program memory is used to store the application
program. The 48 kbytes of this memory reside in the address
range of 0000-BFFF hex. A normal CPU write operation to
this memory has no effect.
The program memory has the following features:
•48 kbytes arranged as 24K by 16 bits
•Page size of 64 words, divided into two rows of 32 words
•30 µs programming pulse per word
•Page mode erase with a 1 ms pulse
•Programming high voltage and timing generated on-chip
•Boot-ROM controlled in-system programming capability
•User-coded programming capability
•Security features to limit read/write access
8.1.1 Reading
Program memory read accesses can operate without wait cy-
cles with a CPU clock rate of up to 12.5 MHz in the normal
mode. At higher clock rates, memory read accesses can op-
erate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by the BIU Configuration (BCFG) register
and the Static Zone 0 Configuration (SZCFG0) register.
These registers are described in Section7.2.1 and 7.2.3.
8.1.2 Conventional Programming Modes
The flash program memory can be programmed either with
device plugged into an EPROM programmer unit (external
programming) or with the device installed in the application
system (in-system programming). The device internally gen-
erates the necessary voltages for programming. No addition-
al power supply is required.
Programming the memory requires placing the device in a
special programming mode. Programming commands is-
sued while the device is in its normal operating mode are ig-
nored.
To enter one of the programming modes, the device must be
reset with the ENV1 and ENV0 pins configured to select the
desired mode: Test Mode for external programming or In-
System Programming mode for in-system programming.
Once the device enters the programming mode, the pro-
gramming software performs the task of downloading the
program code through a serial port and writing the code to
the EEPROM memory. The software used for programming
the EEPROM resides outside of the device for external pro-
gramming or in the on-chip boot ROM for conventional in-
system programming.
8.1.3 User-Coded Programming Routines
Instead of using an EPROM programmer unit or the conven-
tional in-system programming mode, you can write your own
processor code to program and erase the flash program
memory. Writing your own code is more flexible than using
the other programming methods. Like the conventional in-
system programming mode, you can program the device
while it is installed in the system, but no PC is required to
download the program data. It is not necessary to reset the
device or use the ENV0/ENV1 pins to configure the device.
If you write your own flash EEPROM programming code, the
code must reside in the 2 kbytes of RAM memory, in the ad-
dress range of E000-E7FF. This is because the entire flash
program memory becomes unavailable when you program or
erase any part of that memory.
Also, for programming the flash program memory, you need
to design a protocol for the device to obtain the programming
data. For example, you can use the on-chip USART to obtain
the programming data from an external device through a se-
rial interface.
The flash program memory is divided into 384 pages, each
page containing 64 words (each 16 bits wide). Each page is
further divided into two rows of 32 words. Erasure is carried
out one page at a time, whereas programming is carried out
one row (or one partial row) at a time.
Once an erase or programming operation is started, the
PGMBUSY bit in the MSTAT register is automatically set, and
then cleared when the operation is complete. All high-voltage
pulses and timing needed for programming and erasing are
provided internally. The program memory cannot be access-
ed while the PGMBUSY bit is set.
8.1.4 Flash EEPROM Programming and Verify
The flash EEPROM program memory programming and
erase can be performed using different methods. It can be
done through user code that is stored in system RAM, or
through In-System-Programming mode, but should not be
programmed through the flash EEPROM program memory it-
self as no instruction or data can be fetched from it while it is
being programmed. All program and erase operations must
be preceded immediately by writing the proper key to the pro-
gram memory key register PGMKEY.
The flash EEPROM program memory is divided into 384 pag-
es, each page containing 64 words (each 16 bits wide). Each
page is further divided into two adjacent rows. A page erase
will erase one page. Programming is done by writing to all
the words within a row, one word following another sequen-
Obsolete
23 www.national.com
tially within one single high voltage pulse. This is supported
through a double-buffered write-data buffer scheme. Byte
programming is not supported. Programming should be
done on erased rows.
A page erase requires the following code sequence (assum-
ing that this sequence will not be interrupted to do another
flash erase or programming):
1. Check for MSTAT.PGMBUSY not set.
2. Set FLCSR.ERASE = 1.
3. If interrupt was enabled, disable interrupt.
4. Write proper key value to PGMKEY.
5. Write to any valid location within the page to be erased.
6. If interrupt was disabled in step 3, re-enable interrupt.
7. Set FLCSR.ERASE = 0.
When programming, the data to be written into the flash EE-
PROM program memory is first written into a double-buffered
write-data buffer. When a piece of data is written to the page
while the flash EEPROM program memory is idle, the write
cycle will start. Due to the double-buffered nature of the
write-data buffer, a second word can be written to the flash
EEPROM program memory. This will then set FLCSR.PML-
FULL flag indicating the buffer is now full. When the first
write is done, the memory address would be incremented,
and the second word would be written to that address while
keeping the high voltage pulse active; the FLCSR.PMLFULL
flag is cleared. Another word can then be written to the buff-
er, and this programming will repeat until there are no more
words to be programmed. This allows pipelined writes to dif-
ferent words on the same row within the same high voltage
pulse. If the programming sequence exceeds a row, the
flash programming interface will automatically initiate a pro-
gramming pulse for the next row. The FLCSR.PMLFULL bit
is also cleared. when programming of the last word of the
current row is completed, e.g. programming of the entire row
is completed and MSTAT.PGMBUSY is cleared. This means,
the separation of the program memory into rows is transpar-
ent to the user, as the transition is handled by the flash pro-
gram memory interface. Figure2 shows a flowchart for a
programming sequence.
Erase Procedure
Erasing a page requires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Disable any enabled interrupts.
3. Set the FLCSR.ERASE bit to 1.
4. Write the proper key value to the PGMKEY register.
5. Write to any valid location in the page to be erased.
6. Clear the FLCSR.ERASE bit to 0.
7. Re-enable any interrupts disabled in Step 2.
Erased bits read back as 1.
start
MSTAT.PGMBUSY
=1?
disable interrupt
if necessary
write PGMKEY
re-enable interrupt
if necessary
write memory
last word?
done
Yes
No
Yes
Yes FLCSR.PMLFULL
=0?
No
No
Figure 2.Programming Sequence for
the Program Memory
Obsolete
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Programming Procedure
Programming is done by writing to all the words within a row,
one word following another sequentially, within a single high-
voltage pulse for the entire row. It is not possible to program
single bytes. Programming should be done only on erased
rows.
Programming a row requires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Disable any enabled interrupts.
3. Write the proper key value to the PGMKEY register.
4. Write the desired word to the lowest address of the row.
5. Wait until the FLCSR.PMLFULL bit is cleared to 0.
6. Write the proper key value to the PGMKEY register.
7. Write the desired word to the next address of the row.
8. Repeat Steps 5, 6, and 7 until the whole row is written.
9. Re-enable any interrupts disabled in Step 2.
The programmed values can be verified by normal read op-
erations from the applicable memory locations.
Each time you write a word to the flash program memory us-
ing the procedure just described, the data word is stored in a
two-level write-data buffer. The first word written while the
program memory is idle starts the write cycle. Due to double-
buffering of the write path, a second word can be written to
the program memory while the first word is still being pro-
grammed. Writing the second word sets the FLCSR.PML-
FULL flag, thus indicating that the write-data buffer is full.
When programming of the first word is done, the memory ad-
dress is incremented, programming of the second word
starts, and the PLCSR.PMFULL flag is cleared. The next
word can then be written to the write-data buffer. This pro-
cess is repeated until there are no more words in the buffer
or the entire row has been programmed. All of this happens
within the same high-voltage programming pulse.
If a reset occurs in the middle of an erase or programming
operation, the operation is terminated. The reset is extended
until the flash memory returns to the idle state.
8.1.5 Erase and Programming Timing
The internal hardware of the device handles the timing of
erase and programming operations. To drive the timing con-
trol circuits, the device divides the system clock by a pro-
grammable prescaler factor. You should select a prescaler
value to produce a program/erase clock of 200 kHz (or as
close as possible to 200 kHz without exceeding 200 kHz).
For the timing control circuit to operate correctly, you must
program the prescaler value in advance and leave it un-
changed while a program or erase operation is in progress.
A similar (but separate) prescaler factor is applied to the EE-
PROM data memory. See Section8.1.7 and Section8.3.4 for
details.
8.1.6 Flash Program Memory Control and Status
Register (FLCSR)
The Flash Program Memory Control and Status (FLCSR)
register is a byte-wide, read/write register that contains sev-
eral status and control bits related to the program memory.
Upon reset, this register is cleared to zero when the flash
memory on the chip is in the idle state.
The register format is shown below.
ERASE Erase Flash Program Memory Page. When set
(1), a write to the program memory erases the
whole page containing the addressed memory
location. When cleared (0), a write to the pro-
gram memory either has no effect on program-
ming the memory word (if properly set up for
programming). This bit should be changed only
when the flash memory is not busy being pro-
grammed or erased.
PMBUSY Program Memory Busy. This bit is automatical-
ly set to 1 when the flash program memory is
busy being programmed, and cleared to 0 at all
other times. (The MSTAT.PGMBUSY is also set
to 1 whenever the PMBUSY bit is set to 1.)
PMLFULL Program Memory Write-Latch Buffer Full.
When set (1), the double-buffered data register
for program memory write operations is full.
When cleared (0), the double-buffered data
register is not full.
IENPROG Interrupt Enable for Program Memory Write.
When set (1), the flash program memory write
mechanism generates an interrupt whenever
the PMLFULL bit changes from 1 to 0. This is a
signal to the CPU to write the next word for pro-
gramming. When IENPROG is cleared, no
such interrupt is generated.
8.1.7 Program Memory Timing Prescaler Register
(FLPSLR)
The FLPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the flash program mem-
ory programming clock. Before you program or erase the pro-
gram memory for the first time, you should program the
FLPSLR register with the proper prescaler value, an 8-bit val-
ue called FTDIV. The device divides the system clock by (FT-
DIV+1) to produce the program memory programming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. For example, if the system clock frequency is 12.5
MHz, use the value 3E hex (62 decimal) for FTDIV, because
12.5 MHz / (62+1) = 198.4 kHz. Do not modify this register
while a flash program or erase operation is in progress.
Upon reset, this register is programmed by default with the
value 33 hex (51 decimal), which is an appropriate setting for
a 10.4 MHz system clock.
8.1.8 Program Memory Write Key Register (PGMKEY)
The PGMKEY register is a byte-wide, write-only register that
must be written with a key value (A3 hex) immediately prior
to each write to the flash program memory. Otherwise, the
write operation to the program memory will fail. This feature
is intended to prevent unintentional programming of the pro-
gram memory.
Reading this register always returns FF hex.
7 6 5 4 3 2 1 0
Reserved IENPROG PMLFULL PMBUSY ERASE Reserved
Obsolete
25 www.national.com
8.2 RAM MEMORY
The static RAM memory is used for temporary storage of
data and for the program and interrupt stacks. The 2 kbytes
of this memory reside in the address range of E000-E7FF
hex. Each memory access requires one clock cycle, for a
byte or word access. For non-aligned word access, each
memory access requires multiple clock cycles. No wait cy-
cles or hold cycles are required.
8.3 EEPROM DATA MEMORY
The EEPROM data memory is used for non-volatile storage
of data. The 640 bytes of this memory reside in the address
range of F000-F27F hex. The CPU reads or writes this mem-
ory by using ordinary byte-wide or word-wide memory ac-
cess commands.
8.3.1 Reading
EEPROM data memory read accesses can operate without
wait cycles with a CPU clock rate of up to 12.5 MHz in the
normal mode. At higher clock rates, read accesses can oper-
ate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by a bit in the Module Configuration regis-
ter (MCFG.FEEDM). This register is described in
Section4.2.
8.3.2 Programming
Before you begin programming the EEPROM data memory,
you should set the value in the EEPROM Data Memory Pres-
caler register. This register sets the prescaler used to gener-
ate the data memory programming clock from the system
clock, as described in Section8.3.4.
After the CPU performs a write to the EEPROM data memo-
ry, the on-chip hardware completes the EEPROM program-
ming in the background. When programming begins, the on-
chip hardware sets the DMCSR.DMBUSY bit to 1, and also
sets the MSTAT.PGMBUSY bit to 1. When programming is
completed, it resets these status bits back to 0. Once the
software writes to the EEPROM data memory, it should not
attempt to access the EEPROM data memory again until pro-
gramming is completed and the status bit is reset to 0.
The device hardware internally generates the voltages and
timing signals necessary for programming. No additional
power supply is required, nor any software required except to
check the status bit for completion of programming. The min-
imum time required to erase and reprogram a byte or word is
1.16 ms. The programmed values can be verified by using
normal memory read operations.
If a reset occurs during a programming or erase operation,
the operation is terminated. The reset is extended until the
flash memory returns to the idle state.
The EEPROM data memory does not have permanent read-
protection or write-protection features like those available for
the EEPROM program memory. However, the Data Memory
Write Key Register provides a way to “lock” the data written
to the data memory.
8.3.3 Data Memory Control and Status Register
(DMCSR)
The DMCSR register is a byte-wide, read/write register used
with the EEPROM data memory. There are two status/control
bits, as shown in the register format below.
ERASE Erase ISP Flash Program Memory Page.
When set (1) a valid write to the ISP flash EE-
PROM program memory will erase the entire
ISP flash EEPROM program memory page
pointed to by the write address rather than per-
forming a write to the addressed memory loca-
tion. This bit should be cleared to 0 and remain
cleared after the write operation.
DMBUSY Data Memory Busy. This bit is automatically set
to 1 when the EEPROM data memory is busy
being programmed, and cleared to 0 at all other
times. (The MSTAT.PGMBUSY is also set to 1
whenever the DMBUSY bit is set to 1.)
Upon reset, the DMCSR register is cleared to zero when the
flash memory on the chip is in the idle state.
8.3.4 Data Memory Prescaler Register (DMPSLR)
The DMPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the EEPROM data
memory programming clock. Before you write to the data
memory for the first time, you should program the DMPSLR
register with the proper prescaler value, an 8-bit value called
FTDIV. The device divides the system clock by (FTDIV+1) to
produce the data memory programming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. Upon reset, this register is programmed by default
with the value 33 hex (51 decimal), which is an appropriate
setting for a 10.4 MHz system clock.
8.3.5 Data Memory Write Key Register (DMKEY)
The DMKEY register is a byte-wide, read/write register that
provides a way to “lock” the data contained in the EEPROM
data memory. Upon reset, the register is automatically set to
C9 hex, which is the key value. Writing to the EEPROM data
memory is allowed as long as the DMKEY register contains
this value. When the register contains any value other than
C9 hex, writing the EEPROM data memory is disallowed.
To “lock” the current data stored in the data memory, write an-
other value (such as 00 hex) to the DMKEY register. To “un-
lock” the data memory, write the value C9 hex to the DMKEY
register.
Note: Operation of this register is different from the
PGMKEY register used with the program memory. It is not
necessary to write the key value to DMKEY every time you
write to the data memory.
8.4 ISP MEMORY
The In-System Program memory is part of the flash memory
array that contains the flash EEPROM data memory. It is not
possible to access the ISP memory while programming the
7 6 5 4 3 2 1 0
Reserved DMBUSY ERASE Reserved
Obsolete
www.national.com 26
flash EEPROM data memory or access the flash EEPROM
data memory while programming the ISP memory. The 1.5
kbytes of ISP memory resides in the address range of DA00-
DFF7 and is used for storing a boot ROM. The ROM contains
the code that performs in-system programming, and is pro-
grammed at the factory. In ISP mode, code execution starts
at address DA00.
The ISP program memory and flash EEPROM data memory
share the same memory array, which makes it impossible to
access one type of memory while the other is being pro-
grammed.
The ISP memory has the following features:
—1.5 kbytes ISP flash EEPROM program memory
—Page size of 4 words, divided into two rows of 2 words
each
—Odd and even bytes within a page can be erased sep-
arately
—The lowest 384 rows are the ISP memory, the others
are data memory; A1 selects the columns and A[11:2]
select the rows
—30µs programming pulse width per word
—Page mode erase with 1ms pulse
—All erased memory bits read 1
—Fast read access time
—Requires valid key for program and erase to proceed
—Provide memory protection and security features for
flash EEPROM program memory
—Security features may limit accesses to ISP memory
—Disable memory when address is out of range to pre-
vent accessing data memory
—Provide busy status during programming and erase
—Read/write accesses disabled during programming/
erase
—Programming high voltage and timing generated on-
chip
—Support flash memory test mode with PADX for securi-
ty overrides
8.4.1 Reading
The ISP flash EEPROM program memory read accesses can
operate without wait cycles with a CPU clock rate of up to
20MHz in the normal mode. At higher clock rates, read ac-
cesses can operate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by BIU Configuration (BCFG) register and
the Static Zone 0 Configuration (SZOFG0) register. These
registers are described in Section7.2.1 and 7.2.3.
8.4.2 User-Coded Programming Routines
All program and erase operations must be preceded by writ-
ing the proper key to the program memory key register ISP-
KEY. The programming code can reside in the in-system
RAM, but cannot reside in the ISP flash EEPROM program
memory or flash EEPROM data memory as accesses within
these ranges are not permitted while ISP flash EEPROM pro-
gram memory is being programmed.
The ISP flash memory is divided into 192 pages, each page
containing 4 words (each 16 bits wide). Each page is further
divided into two rows. Erase is carried out one page at a time,
whereas programming is carried out one row (or one partial
row) at a time.
Once an erase or programming operation is started, the PG-
MBUSY bit in the MSTAT register is automatically set, and
then cleared when the operation is complete. All high-voltage
pulses and timing needed for programming and erasing are
provided internally. The program memory cannot be access-
ed while the PGMBUSY bit is set.
Erase Procedure
Erasing a page requires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Set the DMCSR.ERASE bit to 1.
3. Locally disable interrupts.
4. Write proper key value to the ISPKEY register.
5. Write to any valid page to be erased.
6. Re-enable interrupts disabled in Step 3.
7. Set the DMCSR.ERASE bit to 0.
8.4.3 Programming Procedure
Programming is done by writing one byte or word at a time
and should be done on already erased memory.
Programming the ISP flash EEPROM program memory re-
quires the following code sequence:
1. Verify that the MSTAT.PGMBUSY bit is cleared.
2. Locally disable interrupts.
3. Write proper key value to the ISPKEY register.
4. Write a byte or word to the addressed location.
5. Re-enable interrupts disabled in Step 2.
Programmed values can be verified through normal read op-
erations.
If a reset occurs in the middle of an erase or programming
operation, the operation is terminated. The rest is extended
until the flash EEPROM memory returns to the idle state.
8.4.4 Erase and Programming Timing
The program and erase timing are controlled by the flash EE-
PROM data memory logic.
8.4.5 Protection Features
The last byte of the ISP memory are reserved for special
functions and provide memory protection and security for the
flash EEPROM program memory. Read and write protection
is provided.
8.4.6 Program Memory Security Features
The program memory has security features to prevent unau-
thorized access to the program code and unintentional pro-
gramming. These features are invoked by programming a
non-volatile control register, the Flash EEPROM Security
(FLSEC) register. This register contains a read-access con-
trol bit and a write-access control bit.
Both control bits are initially set to 1. Programming the read-
access bit to 0 prevents outside access to the program code;
any attempt to access the code from outside returns all ze-
ros. Programming the write-access bit to 0 prevents any fur-
ther programming of the flash program memory, thus
protecting the program code from overwriting.
Programming either bit to 0 (or both bits to 0) also prevents
any further changes to the FLSEC register itself. Thus, invok-
ing read protection and/or write protection is permanent.
Obsolete
27 www.national.com
The Flash Memory Security (FLSEC) register format is
shown below.
FROMRD When this bit is set to 1, the flash program
memory can be read from outside the device.
When this bit is cleared to 0, the flash program
memory cannot be read from outside the de-
vice, and the FLSEC register itself is write-pro-
tected.
FROMWR When this bit is set to 1, the flash program
memory can be erased and overwritten by sub-
sequent programming operations. When this
bit is cleared to 0, the program memory and the
FLSEC register itself are both write-protected.
7 6 5 4 3 2 1 0
Reserved FROMWR Reserved FROMRD
Obsolete
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9.0 Interrupts
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. Interrupts from the timers, USARTs, MICROW-
IRE/SPI interface, Multi-Input Wake-Up, and A/D converter
are all maskable interrupts. The highest-priority interrupt is
the Non-Maskable Interrupt (NMI), which is triggered by a
falling edge received on the NMI input pin. The NMI pin is not
available on the 44-pin packages.
9.1 INTERRUPT OPERATION
An exception is an event that temporarily stops the normal
flow of program execution and causes execution of a sepa-
rate service routine. Upon completion of the service routine,
execution of the interrupted program continues from the point
at which it was stopped.
There are two kinds of exceptions, called traps and inter-
rupts. A trap is the result of some action or condition in the
program itself, such as execution of an Exception (EXCP) in-
struction. An interrupt is a CPU-external event, such as a sig-
nal received on a Multi-Input Wake-Up input or a request
from an on-chip peripheral module for service.
The operation of traps is beyond the scope of this data sheet.
For information on traps, and for additional detailed informa-
tion on interrupts not provided in this data sheet, please refer
to the CompactRISC CR16B Programmer's Reference Man-
ual.
9.1.1 Interrupt Operation Summary
When an interrupt occurs, the on-chip hardware performs the
following steps:
1. Decrements the Interrupt Stack Point (ISP) by four.
2. Saves the contents of the Program Counter (PC) and
Processor Status Register (PSR) on the interrupt stack.
3. Clears the I, P, and T bits in the Processor Status Reg-
ister (PSR). These are the Global Maskable Interrupt
Enable bit, Trace Trap Pending bit, and Trace bit, re-
spectively.
4. Reads the interrupt vector from the Interrupt Vector Reg-
ister (IVCT).
5. Combines the interrupt vector with the value in the Inter-
rupt Base (INTBASE) register to obtain an address in the
Interrupt Dispatch Table, and loads the dispatch table
entry into the Program Counter (PC).
From this point onward, the CPU executes the interrupt ser-
vice routine. The service routine ends with a Return from Ex-
ception (RETX) instruction. This returns the CPU to the
interrupted program. The CPU restores the contents of the
PC and PSR registers from the stack and increments the In-
terrupt Stack Pointer by four.
9.1.2 Service Routine Addresses
When an interrupt or trap occurs, the CPU executes a service
routine. There are different service routines for different inter-
rupts and traps. Each service routine may reside anywhere
in program memory. The starting addresses of the service
routines are contained in a table called the Dispatch Table.
Entries in the table are organized in the order shown in
Table10.
Each entry in the Dispatch Table consists of two bytes that
provide bits 1 through 16 of the starting address of the corre-
sponding service routine. The full 21-bit address of a service
routine is reconstructed by adding a leading 0 and a trailing
0 to the 16-bit table entry. Because the program memory of
the device only occupies the range of 0000-BFFF hex, en-
tries in the table are restricted to this range.
The INTBASE register is a pointer to the Dispatch Table.
Upon reset, the initialization software must write the starting
address of the Dispatch Table to the INTBASE register, a 21-
bit register with the five most significant bits and the least sig-
nificant bit always equal to 0. It is typically kept in the flash
EEPROM program memory. The Dispatch Table is 32 words
long.
Table 10Dispatch Table Entries
0: Reserved
1: NMI
2: Reserved
3: Reserved
4: Reserved
5: SVC (Supervisor Call Trap)
6: DVC (Divided by Zero Trap)
7: FLG (Flag Trap)
8: BPT (Breakpoint Trap)
9: TRC (Trace Trap)
10: UND (Undefined Instruction Trap)
11: Reserved
12: Reserved
13: Reserved
14: Reserved
15: Reserved
16: INT0 (Reserved)
17: INT1 (A/D Converter)
18: INT2 (Multi-Input Wake-Up)
19: INT3 (Reserved)
20: INT4 (USART2 Tx)
21: INT5 (USART1 Tx)
22: INT6 (MICROWIRE/SPI Rx/Tx)
23: INT7 (Reserved)
24: INT8 (USART2 Rx)
25: INT9 (USART1 Rx)
26: INT10 (Timer 2 Input B)
27: INT11 (Timer 2 Input A)
28: INT12 (Timer 1 Input B)
29: INT13 (Timer 1 Input A)
30: INT14 (Timer 0)
31: INT15 (Reserved)
Obsolete
29 www.national.com
Each interrupt or trap source has an associated vector num-
ber ranging from 0 to 31, as indicated in Table10. When an
interrupt occurs, the hardware multiplies the vector by 2,
adds the result to the contents of the INTBASE register, and
uses the resulting address to obtain the service routine start-
ing address from the corresponding entry in the Dispatch Ta-
ble. This address is placed in the Program Counter so that
the CPU begins executing the interrupt service routine.
Figure3 summarizes the method used by the device to gen-
erate the starting address of a service routine.
9.1.3 Stack Usage
When an interrupt occurs, the CPU automatically preserves
the contents of the Program Counter (PC) and Processor
Status Register (PSR) by pushing them on the interrupt stack
and decrementing the Interrupt Stack Pointer by four. The
service routine ends with a Return from Exception (RETX) in-
struction, which returns control to the interrupted program by
restoring the PC and PSR values and incrementing the Inter-
rupt Stack Pointer (ISP) by four.
Prior to using any interrupts, the Interrupt Stack Pointer (ISP)
must be initialized so that it points to a space in RAM where
the interrupt stack will be kept. The stack grows downward in
memory (toward address zero) when an interrupt occurs and
items are pushed onto the stack. The stack shrinks upward
in memory when an interrupt service routine ends and items
are popped from the stack.
Many routines need to use the general-purpose registers R0
through R13. To preserve the existing register contents, a
routine can save register contents on the program stack
upon start of the routine and restore the register contents pri-
or to completion of the routine. The software can also use the
program stack to transfer data parameters from one routine
to another when the parameters are too large to easily fit into
the scratch registers (large structures, large arrays, or a set
of more than four parameters in a single routine). A high-level
language typically allocates the local (non-static) variables
on the stack.
The stack pointer for the program stack is the SP register,
which must be initialized prior to any register save/restore
operations or data transfer operations. Using the program
stack, an interrupt routine needs to initially save the contests
of all registers that it uses, and restore those register con-
tents before returning to the interrupted program.
9.2 NON-MASKABLE INTERRUPT
A non-maskable interrupt is triggered by a falling edge on the
NMI input pin, which generates a software trap. The NMI pin
is an asynchronous input with Schmitt trigger characteristics
and an internal synchronization circuit. Therefore, no exter-
nal synchronizing is needed.
Upon reset, the non-maskable interrupt is disabled and
should remain disabled until the software initializes the inter-
rupt table, interrupt base, and interrupt stack pointer. It can
Figure 3.
INTBASE
~
~
~
~
Non-maskable Interrupt
Reserved
Supervisor Call Trap
Divide By Zero Trap
Flag Trap
Breakpoint Trap
Trace Trap
Undefined Instruction Trap
Maskable Interrupts
NMI
Reserved
Reserved
SVC
DVZ
FLG
BPT
TRC
UND
Reserved
Reserved
ISE
INTn
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 to 127
In-System Emulator Interrupt
31 0
Reserved
Reserved
DBG Debug Trap
Obsolete
www.national.com 30
be enabled by setting either of two control bits in the External
NMI Control/Status (EXNMI) register. The two bits are called
the EN (Enable) bit and the ENLCK (Enable and Lock) bit.
The EN bit enables the NMI trap until an NMI trap event or a
reset occurs. An NMI trap automatically resets the EN bit. Us-
ing this bit to enable the NMI trap is intended for applications
where the NMI pin is toggled frequently but nested NMI traps
are not needed. The trap service routine should re-enable the
NMI trap by setting the EN bit before returning to the main
program.
The ENLCK bit enables the NMI trap and locks it in the en-
abled state. In other words, it leaves the NMI trap enabled
even after the trap occurs. It can be cleared only by a reset
operation. After the bit is set, an NMI trap is triggered by each
falling edge on the NMI pin, allowing nested NMI traps.
To use the EN bit, the ENLCK must remain cleared to 0. Oth-
erwise, the EN bit is ignored.
9.3 MASKABLE INTERRUPTS
Maskable interrupts can be enabled or disabled under soft-
ware control. There are 16 maskable interrupt sources (in-
cluding some reserved for future expansion), organized into
levels of priority. If more than one interrupt event occurs at
any given time, the interrupt source with the highest priority
is serviced first. The others must wait until the highest-priority
interrupt is serviced and is no longer pending.
Figure11 lists the maskable interrupt sources of the device
in order of priority, from the highest-priority interrupt (IRQ15)
to the lowest (IRQ0).
To enable a maskable interrupt, the enable bit must be set in
the applicable peripheral module and also in the appropriate
Interrupt and Enable Mask register, IENAM0 or IENAM1. In
addition, both the Global Maskable Interrupt Enable bit (I)
and the Local Maskable Interrupt Enable bit (E) must be set
to 1 in the PSR register. If either one of these bits is 0, then
all maskable interrupts are disabled.
Both the E bit and I bit can be controlled with the Load Pro-
cessor Register (LPR) instruction. In addition, the E bit is
easily changed by executing the Enable Interrupts (EI) or
Disable Interrupts (DI) instruction. Using the EI and DI in-
structions avoids the possibility of an interrupt occurring with-
in a read-modify-write operation on the PSR register.
For more information on the PSR bits, see Section6.3.
9.4 INTERRUPT REGISTERS
The Interrupt Control Unit uses the following interrupt control
and status registers:
•Non-Maskable Interrupt Status Register (NMISTAT)
•External NMI Control/Status Register (EXNMI)
•Interrupt Enable and Mask Register 0 (IENAM0)
•Interrupt Enable and Mask Register 1 (IENAM1)
•Interrupt Vector Register (IVCT)
•Interrupt Status Register 0 (ISTAT0)
•Interrupt Status Register 1 (ISTAT1)
The following CPU core registers are also used in processing
interrupts:
•Interrupt Stack Pointer (ISP)
•Interrupt Base Register (INTBASE)
•Processor Status Register (PSR)
Table 11Maskable Interrupt Priority List
Interrupt Request Source
IRQ15 Reserved (highest priority)
IRQ14 Timer 0
IRQ13 Timer 1 Input A
IRQ12 Timer 1 Input B
IRQ11 Timer 2 Input A
IRQ10 Timer 2 Input B
IRQ9 USART1 Rx
IRQ8 USART2 Rx
IRQ7 Reserved
IRQ6 MICROWIRE/SPI Rx/Tx
IRQ5 USART1 Tx
IRQ4 USART2 Tx
IRQ3 Reserved
IRQ2 Multi-Input Wake-Up
IRQ1 A/D Converter
IRQ0 Reserved (lowest priority)
Obsolete
31 www.national.com
9.4.1 Non-Maskable Interrupt Status Register
(NMISTAT)
The NMISTAT register is a byte-wide, read-only register that
holds the current pending status of the Non-Maskable Inter-
rupt (NMI). This register is cleared upon reset. It is also
cleared each time it is read. The register format is shown be-
low.
EXT External Non-Maskable Interrupt Request.
When set to 1 by the hardware, it indicates an
external Non-Maskable Interrupt request has
occurred. See the description of the EXNMI
register below for more information.
9.4.2 External NMI Control/Status Register (EXNMI)
The EXNMI register is a byte-wide, read/write register that
shows the current state of the NMI pin and also allows the
NMI trap to be enabled by setting either the EN bit or the EN-
LCK bit. Both of these bits are cleared upon reset. When the
software writes to this register, it must write 0 to all reserved
bit positions for the device to function properly. The register
format is shown below.
EN Enable NMI Trap. When set to 1, NMI traps are
enabled and falling edge on the NMI pin gener-
ates a NMI trap. Each occurrence of an NMI
trap automatically clears the EN bit. The trap
service routine should set the EN bit to 1 before
returning control to the interrupted program.
When EN is cleared to 0, NMI traps are dis-
abled unless they are enabled with the ENLCK
bit. When the ENLCK bit is set to 1, the EN bit
is ignored.
PIN NMI Pin. This bit shows the current state of the
NMI input pin (without logical inversion). A 1 in-
dicates a high level and a 0 indicates a low lev-
el on the pin. This is a read-only bit. In a write
operation, the value written to this bit position is
ignored.
ENLCK Enable and Lock NMI Trap. When set to 1, NMI
traps are enabled and locked in the enabled
state. Each falling edge on the NMI pin gener-
ates a NMI trap, even if a previous NMI trap
has occurred and is still being processed.
When ENLCK is cleared to 0, NMI traps are
disabled unless they are enabled with the EN
bit.
9.4.3 Interrupt Vector Register (IVCT)
The IVCT register is a byte-wide, read-only register that con-
tains the encoded value of the enabled and pending
maskable interrupt with the highest priority. The on-chip
hardware automatically updates this field whenever there is
a change in the highest-priority enabled and pending
maskable interrupt. The CPU reads this register during an in-
terrupt acknowledge core bus cycle to determine where to
begin executing the interrupt service routine. The register
contents are guaranteed to be valid at that time. The register
is not guaranteed to contain valid data during a hardware up-
date operation. The register format is shown below.
INTVECT Interrupt Vector. This 5-bit field contains the en-
coded value of the enabled and pending
maskable interrupt with the highest priority. For
example, if interrupts IRQ1 and IRQ6 are both
enabled and pending, the higher-priority inter-
rupt is IRQ6. As a result, the 5-bit interrupt vec-
tor is 10110.
9.4.4 Interrupt Enable and Mask Register 0 (IENAM0)
The IENAM0 register is a byte-wide, read/write register that
enables or disables the individual interrupts IRQ0 through
IRQ7. The register format is shown below.
A bit set to 1 enables the corresponding interrupt. A bit
cleared to 0 disables the corresponding interrupt. Upon re-
set, this register is initialized to FF hex.
9.4.5 Interrupt Enable and Mask Register 1 (IENAM1)
The IENAM0 register is a byte-wide, read/write register that
enables or disables the individual interrupts IRQ8 through
IRQ15. The register format is shown below.
A bit set to 1 enables the corresponding interrupt. A bit
cleared to 0 disables the corresponding interrupt. Upon re-
set, this register is initialized to FF hex.
9.4.6 Interrupt Status Register 0 (ISTAT0)
The ISTAT0 register is a byte-wide, read-only register that in-
dicates which maskable interrupt inputs to the ICU (IRQ0
through IRQ7) are currently active. The register format is
shown below.
IST(0-7) Interrupt Status bits. Each bit indicates the cur-
rent status of an interrupt input to the ICU, cor-
responding to interrupts IRQ0 through IRQ7. A
bit set to 1 indicates an active interrupt input,
even when the interrupt is masked out by the
IENAM0 register. A bit cleared to 0 indicates an
inactive interrupt input.
7 6 5 4 3 2 1 0
Reserved EXT
7 6 5 4 3 2 1 0
Reserved ENLCK PIN EN
76543210
0 0 0 INTVECT
76543210
IENA(7:0)
76543210
IENA(15:8)
76543210
IST7 IST6 IST5 IST4 IST3 IST2 IST1 IST0
Obsolete
www.national.com 32
9.4.7 Interrupt Status Register 1 (ISTAT1)
The ISTAT1 register is a byte-wide, read-only register that in-
dicates which maskable interrupt inputs to the ICU (IRQ8
through IRQ15) are currently active. The register format is
shown below.
IST(8-15) Interrupt Status bits. Each bit indicates the cur-
rent status of an interrupt input to the ICU, cor-
responding to interrupts IRQ8 through IRQ15.
A bit set to 1 indicates an active interrupt input,
even when the interrupt is masked out by the
IENAM0 register. A bit cleared to 0 indicates an
inactive interrupt input.
9.4.8 Core Registers (PSR, INTBASE, and ISP)
Some of the CPU core registers are used for controlling inter-
rupts: the Processor Status Register (PSR), the Interrupt
Base Register (INTBASE), and the Interrupt Stack Pointer
(ISP) register.
PSR Register
The Processor Status Register (PSR) is a 16-bit register that
holds status information and selects the operating modes for
the CPU core. Bit 9 and Bit 11 are the Local Maskable Inter-
rupt Enable (E) bit and the Global Maskable Interrupt Enable
(I) bit, respectively, as shown in Figure4. These bits are used
to enable or disable maskable interrupts.
Both the E bit and I bit can be controlled with the Load Pro-
cessor Register (LPR) instruction. The E bit can also be con-
trolled by the Enable Interrupts (EI) and Disable Interrupts
(DI) instructions. If the E and I bits are both set to 1, all
maskable interrupts are accepted. Otherwise, only the non-
maskable interrupt is accepted.
Upon reset, the E bit is set to 1 and the I bit is cleared to 0.
The processor uses the I bit to block maskable interrupts
while executing an interrupt handler. When an interrupt oc-
curs, the processor saves the existing I bit (as part of the
PSR) on the interrupt stack and then clears the current I bit
to prevent further interrupts. When RETX is executed, the
former I bit it restored (with the rest of the PSR), again en-
abling masked interrupts.
The E bit is intended to be used in a localized manner, allow-
ing a process to operate without interruption for a short peri-
od while it accesses and modifies system variables and
semaphores. The E bit can be set to 1 by executing the En-
able Interrupt (EI) or cleared to 0 by executing the Disable In-
terrupts (DI) instruction. Using these two instructions avoids
the possibility of an interrupt occurring within a read-modify-
write operation on the PSR register.
INTBASE Register
The Interrupt Base Register (INTBASE) is a 21-bit register
that holds the address of the Dispatch Table for interrupts
and traps. The five most significant bits and the least signifi-
cant bit of this register are always zero. The Dispatch Table
is 32 words long, and limited to the flash program memory
space. Thus, the Dispatch Table must start at an even ad-
dress in the range of 0004 to BFC0 hex.
ISP Register
The Interrupt Stack Pointer (ISP) is a 21-bit register that
points to the lowest address of the last item stored on the in-
terrupt stack. The on-chip hardware modifies the stack con-
tents and stack pointer when an interrupt or trap event occurs
and upon completion of an interrupt or trap service routine.
The five most significant bits and the least significant bit of
this register are always zero. Because the stack must reside
in RAM and the device RAM occupies the address range of
E000-E7FF hex, the interrupt stack is restricted to this range.
9.5 INTERRUPT PROGRAMMING
PROCEDURES
The following subsections provide information on initializing
the device for interrupts, clearing interrupts, and nesting in-
terrupts.
9.5.1 Initialization
Upon reset, all interrupts are disabled. To program the device
for interrupt operation and to enable interrupts, use the fol-
lowing procedure in the application software:
1. Set the interrupt stack pointer (ISP).
2. Load the INTBASE register so that it points to the base
of the interrupt Dispatch Table in ROM.
3. Perform any required preparation steps for the interrupt
service routines.
4. Initialize the peripheral devices that can generate inter-
rupts and set their respective interrupt enable bits.
5. Use the Load Processor Register (LPR) instruction to
set I bit in the PSR register.
6. When the device is ready to execute interrupts, set the
E bit in the PSR register by executing the Enable Inter-
rupts (EI) instruction.
Once maskable interrupts are enabled by setting the E and I
bits, you can disable and re-enable all maskable interrupts by
using the Enable Interrupts (EI) and Disable Interrupts (DI)
instructions, which set and clear the E bit.
9.5.2 Clearing Interrupts
Clearing an interrupt request before it is serviced may cause
a spurious interrupt because the CPU may detect an interrupt
not reflected in the Interrupt Vector (IVCT) register. To ensure
reliable operation, clear interrupt requests only while inter-
rupts are disabled.
Changing the polarity of an interrupt input (for example, in the
Multi-Input Wake-Up module) can cause a spurious interrupt,
and therefore should be done only while interrupts are dis-
abled.
For the same reason, clearing an enable bit in a peripheral
module should be carried out only while the interrupt is dis-
abled.
9.5.3 Nesting Interrupts
Interrupts may be nested, or in other words, an interrupt ser-
vice routine can itself be interrupted by a different interrupt
source. There is no hardware limitation on the number of in-
76543210
IST15 IST14 IST13 IST12 IST11 IST10 IST9 IST8
15 14 13 12 11 109876543210
Reserved IP E 0NZF00LTC
Figure 4.Processor Status Register (PSR) Format
Obsolete
33 www.national.com
terrupt nesting levels. However, the interrupt stack must not
be allowed to overflow its allocated memory space.
Unless specifically enabled by the software, nested inter-
rupts will not occur. When the CPU acknowledges an inter-
rupt, the I bit in the PSR register is automatically cleared to 0
for the duration of the service routine, disabling any further
maskable interrupts.
To allow nested interrupts, an interrupt service routine should
first set or clear the respective interrupt enable bits to specify
which peripherals will be allowed to interrupt the current ser-
vice routine. The present interrupt routine should be disabled
(or interrupt pending bit cleared). The service routine should
then set the PSR.I bit to 1, thus enabling maskable interrupts.
This bit can be controlled with the Store Processor Register
(SPR) and Load Processor Register (LPR) instructions.
Note: Clearing the pending bit of the current interrupt should
not be immediately followed by enabling further interrupts by
setting the I bit in the PSR register. Wait states must be in-
serted into the software after clearing the interrupt pending
bit and before another interrupt. Placing a NOP instruction
will perform this instruction. This is because the instruction
which resets the pending bit may not yet be finished when the
interrupts are already enabled again by setting the I bit in the
PSR register. To avoid this situation the user has to make
sure that prior to enabling the interrupt an additional instruc-
tion is inserted. This could look like the example below:
A CBITi or SBITi instruction may be used to clear the interrupt
pending bit. In such cases, a spurious interrupt may occur.
SBITi $0, T1ICRL # clear pending bit
NOP # NOP instruction
MOVW $0x0a00, r0 # enable further interrupts
LPR r0, psr
Obsolete
www.national.com 34
10.0 Power Management
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode (and
therefore the power consumption) according to the current
level of device activity.
The device can operate in any of four power modes:
•Active
•Power Save
•Idle
•Halt
Table12 summarizes the main properties of the four operat-
ing modes: the state of the high-frequency oscillator (on or
off), the type of clock used by most modules, and the clock
used by the Timing and Watchdog Module (TWM).
The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the de-
vice power supply pins. In the Halt mode, however, the inter-
nal SLCLK does not toggle, and as a result, the TWM timer
and Watchdog Module do not operate. For the Power Save
and Idle modes, the high-frequency oscillator can be turned
on or off under software control, as long as the low-frequency
oscillator exists in the applicable device package.
10.1 ACTIVE MODE
In the Active mode, all device modules are fully operational.
This is the operating mode upon reset. Most device modules
use the clock generated by the high-frequency clock oscilla-
tor. The clock rate is determined by the external crystal net-
work.
Power consumption in the Active mode can be reduced by
selectively disabling inactive modules and/or by executing
the WAIT instruction. When WAIT is executed, the core stops
executing new instructions and waits for an interrupt.
10.2 POWER SAVE MODE
In the Power Save mode, all device modules operate off the
low-frequency clock. If the low-frequency clock is generated
from an external crystal network, the high-frequency clock
oscillator can be turned off to further reduce power consump-
tion.
All on-chip modules continue to operate in the Power Save
mode, with the SLCLK acting as their system clock. If this
mode is entered by using the WAIT command, the CPU is in-
active and waits for an interrupt to wake up. Otherwise, CPU
continues to function normally at the lower frequency of the
slow clock.
The low frequency of the clock in Power Save mode limits the
operation of modules such as the USARTs, MICROWIRE in-
terface, A/D Converter, and timers because they are driven
by the slow clock rather than the normal high-speed clock. In
order to work properly in Power Save mode, modules that
perform real-time operations (such as a USART baud rate
generator) must be reprogrammed to use the slower clock.
To reduce power consumption as much as possible, the pro-
gram should execute a WAIT instruction during periods of
CPU inactivity.
10.3 IDLE MODE
In the Idle mode, the clock is stopped for most of the device.
Only the Power Management Module and Timing and Watch-
dog Module continue to operate. Both of these modules use
the slow clock in this mode.
10.4 HALT MODE
In the Halt mode, all device clocks are disabled and the high-
frequency oscillator is shut off. In this mode, the device con-
sumes the least possible power while maintaining the device
memory and register contents. The low-frequency oscillator
continues to operate in this mode, but with very low power
consumption due to its power-optimized design.
10.5 SWITCHING BETWEEN POWER MODES
Switching from a higher to a lower power consumption mode
is accomplished by writing an appropriate value to the Power
Management Control/Status Register (PMCSR). Switching
from a lower power consumption mode to the Active mode is
usually triggered by a hardware interrupt. Figure5 shows the
four power consumption modes and the events that trigger a
transition from one mode to another.
Some of the power-up transitions are based on the occur-
rence of a wake-up event. An event of this type can be either
a maskable interrupt or a non-maskable interrupt (NMI). All of
the maskable hardware wake-up events are gathered and
processed by the Multi-Input Wake-Up Module, which is ac-
tive in all modes. Once a wake-up event is detected, it is
latched until an interrupt acknowledge cycle occurs or a reset
is applied.
A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execution
Table 12Power Mode Operating Summary
Mode High-Frequency
Oscillator Clock Used TWM Clock
Active On Main Clock Slow Clock
Power Save On or Off Slow Clock Slow Clock
Idle On or Off None Slow Clock
Halt Off None None
Figure 5.Power Modes and Transitions
Active
Power Save
Idle
Halt
IDLE =1
and WAIT
PSM =1
HW event
or PSM =0
HALT =1
HW event
and WAIT
Reset
HW event
Obsolete
35 www.national.com
of the program. It is the interrupt service routine associated
with the wake-up source (MIWU or NMI) that causes actual
program execution to resume.
10.5.1 Power Management Control/Status Register
(PMCSR)
The Power Management Control/Status Register (PMCSR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator in the Power Save
and Idle modes. The two most significant bits, OLFC and
OHFC, are read-only status bits controlled by the hardware.
Upon reset, the non-reserved bits of this register are cleared.
The format of the register is shown below.
PSM Power Save Mode. When this bit is 0, the de-
vice operates in the Active mode. Writing a 1 to
this bit position puts the device into the Power
Save mode, either immediately or upon execu-
tion of the next WAIT instruction, depending on
the WBPSM bit.
The PSM bit can be set and cleared by the soft-
ware. It is also cleared by the hardware when a
hardware wake-up event is detected.
DHF Disable High-Frequency Oscillator. This bit en-
ables (0) or disables (1) the high-frequency os-
cillator in the Power Save or Idle mode. (The
high-frequency oscillator is always enabled in
Active mode and always disabled in Halt mode,
regardless of this bit settings.) The DHF bit is
cleared automatically when a hardware wake-
up event is detected.
IDLE Idle Mode. When this bit is set, the device en-
ters the Idle mode upon execution of a WAIT in-
struction. In order to enter the Idle mode from
the Active mode, the WBPSM bit must be set
before the WAIT instruction is executed.
The IDLE bit can be set and cleared by the soft-
ware. When a hardware wake-up event is de-
tected, this bit is cleared automatically and the
device returns to the Active mode.
HALT Halt Mode. When this bit is set, the device en-
ters the Halt mode upon execution of a WAIT
instruction. In order to enter the Halt mode from
the Active mode, the WBPSM bit must be set
before the WAIT instruction is executed.
The Halt bit can be set and cleared by the soft-
ware. When a hardware wake-up event is de-
tected, this bit is cleared automatically and the
device returns to the Active mode.
WBPSM Wait Before Entering Power Save Mode. When
the CPU writes a 1 to the PSM bit, the WBPSM
determines when the transition from Active to
Power Save mode is done. If the WBPSM bit is
0, the switch to Power Save mode is initiated
immediately; the PSM bit in the register is set
to 1 upon completion of the switch to Power
Save mode. If the WBPSM bit is 1, the device
continues to operate in Active mode until the
next WAIT instruction, and then enters the
Power Save mode. In this case, the PSM bit is
set to 1 immediately, even if a WAIT instruction
has not yet been executed.
In the Active mode, the WBPSM bit must be set
in order to enter the Idle or Halt mode.
OHFC Oscillating High-Frequency Clock. This read-
only bit indicates the status of the high-frequen-
cy clock. If this bit is 1, the high-frequency clock
is available and stable. If this bit is 0, the high-
frequency clock is either disabled, not available
to the Power Management Module, or operat-
ing but not yet stable. The device can switch to
the Active mode only when this bit is 1.
OLFC Oscillating Low-Frequency Clock. This read-
only bit indicates the status of the low-frequen-
cy (slow) clock. If this bit is 1, it indicates that
the slow clock is running and stable. The slow
clock can be either the prescaled fast clock (the
default) or the external oscillator (if selected).
The Dual Clock module will not allow a transi-
tion to the slow crystal mode unless the slow
crystal is operating, so this bit should be 1 un-
der normal circumstances.
The OLFC bit is the multiplexed and sampled
output of the “Good Main Clk” and “Good Low
Speed Clk” indicator signals. These values are
determined at reset or power-up, and then se-
lected according to the programmed slow clock
source.
The device can switch from the Active mode to
the Power Save or Idle mode only if the OLFC
bit is 1. (There is no such restriction on switch-
ing to the Halt mode.)
10.5.2 Active to Power Save Mode
A transition from the Active mode to the Power Save mode is
accomplished by writing a 1 to the PMCSR.PSM bit. The
transition to Power Save mode is either initiated immediately
or upon execution of the next WAIT instruction, depending on
the PMCSR.WBPSM bit.
For an immediate transition to Power Save mode (PMC-
SR.WBPSM=0), the CPU continues to operate using the low-
frequency clock. The PMCSR.PSM bit is set to 1 when the
transition to the Power Save mode is completed.
For a transition upon the next WAIT instruction (PMC-
SR.WBPSM=1), the CPU continues to operate in the Active
mode until it executes a WAIT instruction. Upon execution of
the WAIT instruction, the device enters the Power Save
mode and the CPU waits for the next interrupt event. In this
case, the PMCSR.PSM bit is set to 1 when it is written, even
before the WAIT instruction is executed.
10.5.3 Entering the Idle Mode
Entry into the Idle mode is accomplished by writing a 1 to the
PMCSR.IDLE bit and then executing a WAIT instruction.
The Idle mode can be entered only from the Active or Power
Save mode. For entry from the Active mode, the PMC-
SR.WBPSM bit must be set before the WAIT instruction is
executed.
7 6 5 4 3 2 1 0
OLFC OHFC WBPSM Reserved HALT IDLE DHF PSM
Obsolete
www.national.com 36
10.5.4 Disabling the High-Frequency Clock
In systems where the low-frequency crystal is available and
is used to generate the Slow Clock (SLCLK), power con-
sumption can be reduced further in the Power Save or Idle
mode by disabling the high-frequency clock. This is accom-
plished by writing a 1 to the PMCSR.DHF bit before execut-
ing the WAIT instruction that puts the device in the Power
Save or Idle mode. The high-frequency clock is turned off
only after the device enters the Power Save or Idle mode.
The CPU operates on the low-frequency clock in Power Save
mode. It can turn off the high-frequency clock at any time by
writing a 1 to the PMCSR.DHF bit.
The high-frequency oscillator is always enabled in Active
mode and always disabled in Halt mode, regardless of the
PMCSR.DHF bit setting.
Immediately following power-up and entry into the Active
mode, the software must wait for the low-frequency clock to
become stable before it can put the device in the Power Save
mode. It should monitor the PMCSR.OLFC bit for this pur-
pose. Once this bit is set to 1, the slow clock is stable and the
Power Save mode can be entered.
10.5.5 Entering the Halt Mode
Entry into the Halt mode is accomplished by writing a 1 to the
PMCSR.HALT bit and then executing a WAIT instruction.
The Halt mode can be entered only from the Active or Power
Save mode. For entry from the Active mode, the PMC-
SR.WBPSM bit must be set before the WAIT instruction is ex-
ecuted.
10.5.6 Software-Controlled Transition to Active Mode
A transition from the Power Save mode to the Active mode
can be accomplished by either a software command or a
hardware wake-up event. The software method is to write a
0 to the PMCSR.PSM bit. The value of the register bit chang-
es only after the transition to the Active mode is completed.
If the high-frequency oscillator is disabled for Power Save op-
eration, the oscillator must be enabled and allowed to stabi-
lize before the transition to Active mode. To enable the high-
frequency oscillator, the software writes a 0 to the PMC-
SR.DHF bit. Before writing a 0 to the PMCSR.PSM bit, the
software should first monitor the PMCSR.OHFC bit to deter-
mine whether the oscillator has stabilized.
10.5.7 Wake-Up Transition to Active Mode
A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to the Active mode. When a
wake-up event occurs, the on-chip hardware performs the
following steps:
1. Clears the PMCSR.DHF bit, thus enabling the high-fre-
quency clock (if it was disabled).
2. Waits for the PMCSR.OHFC bit to be set, which indi-
cates that the high-frequency clock is operating and is
stable.
3. Switches the device into the Active mode.
10.5.8 Power Mode Switching Protection
The Power Management Module has several mechanisms to
protect the device from malfunctions caused by missing or
unstable clock signals.
The PMCSR.OHFC and PMCSR.OLFC bits indicate the cur-
rent status of the high-frequency and low-frequency clock os-
cillators, respectively. The software can check the
appropriate bit before it changes to an operating mode that
requires the clock. A status bit set to 1 indicates an operating,
stable clock. A status bit cleared to 0 indicates a clock that is
disabled, not available, or not yet stable.
During a power mode transition, if there is a request to switch
to a mode that uses clock with the status bit cleared to 0, the
switch is delayed until that bit is set to 1 by the hardware.
When the system is built without an external crystal network
for the low-frequency clock, the high-frequency clock is divid-
ed by a prescaler factor to produce the low-frequency clock.
In this situation, the high-frequency clock is disabled only in
the Halt mode, and cannot be disabled for the Power Save or
Idle mode, regardless of the software command issued.
Without an external crystal network for the low-frequency
clock, the device comes out of the Halt or Idle mode and en-
ters the Active mode with the high-speed oscillator used as
the clock. The device can still enter the Power Save from the
Active mode by using the high-frequency-clock divider to
generate the slow clock (PMCSR.DHF=0).
Note: For correct operation in the absence of a low-frequen-
cy crystal, the X2CKI pin must be tied low (not left floating) so
the hardware can detect the absence of the crystal.
Obsolete
37 www.national.com
11.0 Dual Clock and Reset
The Dual Clock and Reset module (CLK2RES) generates a
high-speed main system clock from an external crystal net-
work and a slow clock (32.768 kHz or other rate) for operat-
ing the device in Power Save mode. It also provides the main
system reset signal and a power-on reset function.
Figure6 is block diagram of the Dual Clock and Reset mod-
ule.
11.1 EXTERNAL CRYSTAL NETWORK
An external crystal network is required at pins X1CKI and
X1CKO for the main clock. A similar external crystal network
may be used at pins X2CKI and X2CKO for the slow clock in
packages that have these pins. If an external crystal network
is not used for the slow clock, the clock is generated by divid-
ing the fast main clock.
Figure7 shows the required crystal network at X1CKI/
X1CKO and optional crystal network at X2CKI/X2CKO.
Table13 shows the component specifications for the main
crystal network and Table14 shows the component specifi-
cations for the 32.768 kHz crystal network.
Figure 6.Dual Clock and Reset Module Block Diagram
14-Bit Timer
6-Bit Timer
Start-Up-Delay
Start-Up-Delay
Preset
Preset
Power-On-Reset
System
Reset
Stop
Main Osc In
RESET
X1CKI
X1CKO
X2CKI
X2CKO
Main Osc.
32kHz Osc.
Stop Main Osc.
Stop 32kHz Osc.
Main Clk
Good Main
Clk
Low Speed
Clk
Good Low
Speed Clk
Stop Low
Speed Clk
Time-out
Time-out
Mux
8-Bit
Prescaler
Div.
by-2
Figure 7.External Crystal Network
X1CKI / X2CKI
X1CKO / X2CKO
R1
R2
XTAL
C2
C1
Obsolete
www.national.com 38
The crystal oscillator you choose may require external com-
ponents different from the ones specified above. In that case,
consult with National Semiconductor for the component
specifications.
The crystals and other oscillator components should be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO de-
vice input pins to keep the printed trace lengths to an abso-
lute minimum.
Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when combined
with the parasitic capacitance of the trace, socket, and pack-
age (which can vary from 0 to 8 pF). As a guideline, the load
capacitance is:
CL = (C1 * C2)/(C1+C2) + Cparasitic
C2 > C1
C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
“Q” value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.
11.2 MAIN SYSTEM CLOCK
The main system clock is generated by the main oscillator. It
can be stopped by the Power Management Module to reduce
power consumption during periods of reduced activity. When
the main clock is restarted, a 14-bit timer generates a “Good
Main Clk” signal after a start-up delay of 32,768 clock cycles.
This signal is an indicator that the main clock oscillator is sta-
ble.
The “Stop Main Osc” signal from the Power Management
Module stops and starts the main oscillator. When this signal
is asserted, it presets the 14-bit timer to 3FFF hex and stops
the main oscillator. When the signal goes inactive, the main
oscillator starts and the 14-bit timer counts down from its pre-
set value. When the timer reaches zero, it stops counting and
asserts the “Good Main Clk” signal.
11.3 SLOW SYSTEM CLOCK
The slow (32.768 kHz) clock is necessary for operating the
device in Power Save modes and to provide a clock source
for modules such as the Timing and Watchdog Module.
The slow clock operates in a manner similar to the main
clock. The “Stop Slow Osc” signal from the Power Manage-
ment Module stops and starts the slow oscillator. When this
signal is asserted, it presets a 6-bit timer to 3F hex and dis-
ables the slow oscillator. When the signal goes inactive, the
slow oscillator starts and the 6-bit timer counts down from its
preset value. When the timer reaches zero, it stops counting
and asserts the “Good Low Speed Clk” signal, thus indicating
that the slow clock is stable.
For systems that do not require a reduced power consump-
tion mode, the external crystal network may be omitted for
the slow clock. In that case, the slow clock can be created by
dividing the main clock by a prescaler factor. The prescaler
circuit consists of a fixed divide-by-2 counter and a program-
mable 8-bit prescaler register. This allows a choice of clock
divisors ranging from 2 to 512. The resulting slow clock fre-
quency must not exceed 100 KHz.
A software-programmable multiplexer selects either the
prescaled main clock or the 32.768 kHz oscillator as the slow
clock. Upon reset, the prescaled main clock is selected, en-
suring that the slow clock is always present initially. Selection
of the 32.768 kHz oscillator as the slow clock disables the
clock prescaler, which allows the CLK1 oscillator to be turned
Table 13Component Values of the High Frequency Crystal Circuit
Component Parameters Values Values Values Values Tolerance
Oscillator Resonance Frequency
Type
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance
4 MHz
AT-Cut
75 Ω
4 pF
12 pF
12 MHz
AT-Cut
35 Ω
4 pF
15 pF
16 MHz
AT-Cut
35 Ω
4 pF
15 pF
20 MHz
AT-Cut
35 Ω
4 pF
20 pF
N/A
Crystal Resistor R1 1 MΩ1 MΩ1 MΩ1 MΩ5%
Resistor R2 0 Ω0 Ω0 Ω0 Ω5%
Capacitor C1, C2 22 pF 20 pF 20 pF 20 pF 20%
Table 14Component Values of the Low Frequency Crystal Circuit
Component Parameters Values Tolerance
Oscillator Resonance Frequency
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
32.768kHz
Parallel
N-Cut or XY-bar
40 kΩ
2 pF
9-13 pF
N/A
Crystal Resistor R1 10-20 MΩ5%
Resistor R2 4.7 kΩ5%
Capacitor C1, C2 20 pF 20%
Obsolete
39 www.national.com
off during power-save operation, thus reducing power con-
sumption and radiated emissions. This can be done only if
the module detects a toggling low-speed oscillator. If the low-
speed oscillator is not operating, the prescaler remains avail-
able as the slow clock source.
11.4 POWER-ON RESET
The Power-On Reset circuit generates a system reset signal
upon power-up and holds the signal active for a period of
time to allow the crystal oscillator to stabilize. The circuit de-
tects a power turn-on condition, which presets the 14-bit tim-
er to 3FFF hex. Once oscillation starts and the clock
becomes active, the timer starts counting down. When the
count reaches zero, the 14-bit timer stops counting and the
internal reset signal is deactivated (unless the RESET pin is
held low).
The circuit sets a power-on reset flag bit upon detection of a
power-on condition. The CPU can read this flag to determine
whether a reset was caused by a power-up or by the RESET
input.
Note: Power-On Reset circuit cannot be used to detect a
drop in the supply voltage.
11.5 EXTERNAL RESET
An active-low reset input pin called RESET allows the device
to be reset at any time. When the signal goes low, it gener-
ates an internal system reset signal that remains active until
the RESET signal goes high again.
11.6 DUAL CLOCK AND RESET REGISTERS
The Dual Clock and Reset module (CLK2RES) contains two
registers: the Clock and Reset Control register (CRCTRL)
and the Slow Clock Prescaler register (PRSSC).
11.6.1 Clock and Reset Control Register (CRCTRL)
Clock and Reset Control Register (CRCTRL) is a byte-wide
read/write register that contains the power-on reset flag and
selects the type of slow clock. The register format is shown
below.
SCLK Slow Clock Select. When this bit is set to 1, the
32.728 kHz oscillator is used for the slow clock.
When this bit is cleared to 0, the prescaled
main clock is used for the slow clock. Upon re-
set, this bit is cleared to 0.
POR Power-On Reset. This bit is set to 1 by the
hardware when a power-on condition is detect-
ed, allowing the CPU to determine whether a
power-up has occurred. The CPU can clear
this bit to 0 but cannot set it to 1. Any attempt
by the CPU to set this bit is ignored.
11.7 SLOW CLOCK PRESCALER REGISTER
(PRSSC)
The Slow Clock Prescaler (PRSSC) register is a byte-wide
read/write register that holds the clock divisor used to gener-
ate the slow clock from the main clock. The format of the reg-
ister is shown below.
SCDIV Slow Clock Divisor. If the clock divider is en-
abled (CRCTRL.SCLK=0), the main clock is di-
vided by (SCDIV+1)*2 to produce the slow
system clock. Upon reset, PRSSC register is
set to FF hex.
7 6 5 4 3 2 1 0
Reserved POR SCLK
7 6 5 4 3 2 1 0
SCDIV
Obsolete
www.national.com 40
12.0 Multi-Input Wake-Up
The Multi-Input Wake-Up (MIWU) module monitors its eight
input channels for a software-selectable trigger condition.
Upon detection of a trigger condition, the module generates
either a wake-up request or an interrupt request. A wake-up
request can be used by the power management unit to exit
the Halt, Idle, or Power Save mode and return to the active
mode. An interrupt request generates an interrupt to the CPU
(interrupt IRQ2), allowing interrupt processing in response to
external events.
The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the inter-
rupt request associated with the MIWU that gets the CPU to
start executing code by jumping to the proper interrupt rou-
tine. Therefore, setting up the MIWU interrupt handler is es-
sential for any wake-up operation.
Figure8 is a block diagram showing the internal operation of
the Multi-Input Wake-Up module.
The input pins for the Multi-Input Wake-Up channels are
named WUI0 through WUI7. These pins are alternate func-
tions of I/O pins in Port I and Port L. The first Multi-Input
Wake-Up channel is software-selectable between the WUI0
input pin and the T0OUT signal from the Timing and Watch-
dog (TWM) module, which can be used to wake up the de-
vice after a programmed time interval. The WKCTL register
controls this selection. The remaining seven channels al-
ways use input pins WUI1 through WUI7.
Each input can be configured to trigger on rising or falling
edges, as determined by the setting in the WKEDG register.
Each trigger event is latched into the WKPND register. If a
trigger event is enabled by its respective bit in the WNENA
register, an active wake-up/interrupt signal is generated. The
software can determine which channel has generated the ac-
tive signal by reading the WKPND register.
The Multi-Input Wake-Up module is active at all times, includ-
ing the Halt mode. All device clocks are stopped in this mode.
Therefore, detecting an external trigger condition and the
subsequent setting of the pending flag are not synchronous
to the system clock.
12.1 WAKE-UP EDGE DETECTION REGISTER
(WKEDG)
The Wake-Up Edge Detection (WKEDG) register is a byte-
wide read/write register that controls the edge sensitivity of
the Multi-Input Wake-Up pins. Register bits 0 through 7 con-
trol input pins WUI0 through WUI7, respectively. A bit cleared
to 0 configures the corresponding input to trigger on a rising
edge (a low-to-high transition). A bit set to 1 configures the
corresponding input to trigger on a falling edge (a high-to-low
transition).
This register is cleared upon reset, which configures all eight
inputs to be triggered on rising edges.
The register format is shown below.
12.2 WAKE-UP ENABLE REGISTER (WKENA)
The Wake-Up Enable (WKENA) register is a byte-wide read/
write register that enables or disables each of the Multi-Input
Wake-Up channels. Register bits 0 through 7 control chan-
nels WUI0 through WUI7, respectively. A bit cleared to 0 dis-
ables the wake-up/interrupt function and a bit set to 1
enables the function.
This register is cleared upon reset, which disables all eight
wake-up/interrupt channels.
76543210
WKED7 WKED6 WKED5 WKED4 WKED3 WKED2 WKED1 WKED0
Figure 8.Multi-Input Wake-Up Module Block Diagram
Peripheral Bus
7 0
WKENA
WUI0
WUI7
0
7
..........................
WKEDG WKPND
EXINT to ICU and
To Power Mgt
WKCTRL
Wake-up Signal
WUI0
T0OUT
7 0
..........................
Obsolete
41 www.national.com
The register format is shown below.
12.3 WAKE-UP SOURCE SELECT REGISTER
(WKCTRL)
The Wake-Up Source Select (WKCTRL) register is a byte-
wide read/write register that selects the trigger source for the
first of the eight channels. Register bit 0 controls this func-
tion; the seven higher-order bits are reserved. The register
format is shown below.
WKSEL0 Wake-Up Select 0. This bit cleared to 0 selects
the WUI0 pin as the trigger source. This bit set
to 1 selects the T0OUT signal from the Timing
and Watchdog (TWM) module as the trigger
source, which can be used to wake up the de-
vice after a programmed time interval. This bit
is cleared upon reset. All reserved bits must be
written with 0 for this module to function prop-
erly.
12.4 WAKE-UP PENDING REGISTER (WKPND)
The Wake-Up Pending (WKPND) register is a byte-wide
read/write register in which the Multi-Input Wake-Up module
latches any detected trigger conditions. Register bits 0
through 7 serve as latches for channels WUI0 through WUI7,
respectively. A bit cleared to 0 indicates that no trigger con-
dition has occurred. A bit set to 1 indicates that a trigger con-
dition has occurred and is pending on the corresponding
channel. This register is cleared upon reset.
The CPU can only write a 1 to any bit position in this register.
If the CPU attempts to write a 0, it has no effect on that bit.
To clear a bit in this register, the CPU must use the WKPCL
register (described below). This implementation prevents a
potential hardware-software conflict during a read-modify-
write operation on the WKPND register.
The register format is shown below.
12.5 WAKE-UP PENDING CLEAR REGISTER
(WKPCL)
The Wake-Up Pending Clear (WKPCL) register is a byte-
wide write-only register that lets the CPU clear bits in the WK-
PND register. Writing a 1 to a bit position in the WKPCL reg-
ister clears the corresponding bit in the WKPND register.
Writing a 0 leaves the corresponding bit in the WKPND reg-
ister unchanged.
Reading this register location returns unknown data. There-
fore, do not use a read-modify-write sequence to set the in-
dividual bits. In other words, do not attempt to read the
register and do a logical OR with the register value. Instead,
just write the mask directly to the register address.
The register format is shown below.
12.6 PROGRAMMING PROCEDURES
To set up and use the Multi-Input Wake-Up function, use the
following procedure. Performing the steps in the order shown
will prevent false triggering of a wake-up condition. This
same procedure should be used following a reset because
the wake-up inputs are left floating, resulting in unknown data
on the input pins.
1. Clear the WKENA register to disable the wake-up chan-
nels.
2. If the input originates from an I/O port (the usual case),
set the corresponding bit in the port direction register to
configure the I/O pin to operate as an input.
3. Write the WKEDG register to select the desired type of
edge sensitivity (clear to 0 for rising edge, set to 1 for fall-
ing edge).
4. Set all bits in the WKPCL register to clear any pending
bits in the WKPND register.
5. Set the bits in the WKENA register corresponding to the
wake-up channels to be activated.
To change the edge sensitivity of a wake-up channel, use the
following procedure. Performing the steps in the order shown
will prevent false triggering of a wake-up/interrupt condition.
1. Clear the WKENA bit associated with the input to be re-
programmed.
2. Write the new value to the corresponding bit position in
the WKEDG register to reprogram the edge sensitivity of
the input.
3. Set the corresponding bit in the WKPCL register to clear
the pending bit in the WKPND register.
4. Set the same WKENA bit to re-enable the wake-up func-
tion.
76543210
WKEN7 WKEN6 WKEN5 WKEN4 WKEN3 WKEN2 WKEN1 WKEN0
7 6 5 4 3 2 1 0
Reserved WKSEL0
76543210
WKPD7 WKPD6 WKPD5 WKPD4 WKPD3 WKPD2 WKPD1 WKPD0
76543210
WKCL7 WKCL6 WKCL5 WKCL4 WKCL3 WKCL2 WKCL1 WKCL0
Obsolete
www.national.com 42
13.0 Real-Time Timer and WATCHDOG
The Timing and WATCHDOG Module (TWM) generates the
clocks and interrupts used for timing periodic functions in the
system, and also provides Watchdog protection against soft-
ware errors. The module operates off the slow clock either
generated by the external 32kHz oscillator or from the pres-
caled high speed system clock. The maximum operating
clock frequency is 100kHz.
The WATCHDOG is designed to detect program execution
errors. Once WATCHDOG operation is initiated, the software
must periodically write a specific value to a WATCHDOG reg-
ister. If the software fails to do so, a WATCHDOG error is trig-
gered, which resets the device.
The TWM is flexible in allowing selection of a variety of clock
ratios and clock sources for the WATCHDOG circuit. Once
the software configures the TWM, it can lock the configura-
tion for a higher level of protection against erroneous soft-
ware action. Once locked, the TWM can be released only by
a device reset.
13.1 TWM STRUCTURE
Figure9 is a block diagram showing the internal structure of
the Timing and WATCHDOG module. There are two main
sections: the Real-Time Timer (T0) section at the top and the
WATCHDOG section on the bottom.
All counting activities of the module are based on the slow
clock (SLCLK). A prescaler counter divides this clock to
make a slower clock. The prescaler factor is defined by a 3-
bit field in the Timer and WATCHDOG Prescaler register,
which selects either 1, 2, 4, 8, 16, or 32 and the divide-by fac-
tor. Thus, the prescaled clock period can be set to 1, 2, 4, 8,
16, or 32 times the slow clock period. The prescaled clock
signal is called T0IN.
13.2 TIMER T0 OPERATION
Timer T0 is a programmable 16-bit down counter that can be
used as the time base for real-time operations such as a pe-
riodic audible tick. It can also be used to drive the WATCH-
DOG circuit.
The timer starts counting from the value loaded into the
TWMT0 register and counts down on each rising edge of
T0IN. When the timer reaches zero, it is automatically reload-
ed from the TWMT0 register and continues counting down
from that value. Thus, the frequency of the timer is:
fSLCLK / [ (TWMT0+1) * prescaler ]
When an external crystal oscillator is used as the SLCLK
source or when the fast clock is divided accordingly, fSLCLK
is 32.768 kHz.
The value stored in TWMT0 can range from 0001 hex to
FFFF hex.
Figure 9.Timing and WATCHDOG Module Block Diagram
(TWCP)
16-bit Timer (Timer0)
5-bit pre-scaler counter
WATCHDOG Timer
Peripheral Bus
CLKIN1
T0OUT
WATCHDOG ERROR
TWMT0 register
WDCNT
WDSDM
WATCHDOG
Service
Logic
Restart
Underflow
T0CSR Contrl. Reg.
Restart
Underflow
T0LINT
WDERR
(to ICU)
(to Multi-Input-
Wake-up)
slow clock from
dual clock and
reset module
REAL TIME TIMER (T0)
WATCHDOG
T0IN
Obsolete
43 www.national.com
When the counter reaches zero, an internal timer signal
called T0OUT is set to 1 for one T0IN clock cycle. This signal
sets the TC bit in the TWMT0 Control and Status Register
(T0CSR). It also generates an interrupt called RTI (IRQ14) if
the interrupt is enabled by the T0CSR.T0INTE bit.
If the software loads TWMT0 with a new value, the timer uses
that value the next time that it reloads the 16-bit timer register
(in other words, after reaching zero). The software can re-
start the timer at any time (on the very next edge of the T0IN
clock) by setting the Restart (RST) bit in the T0CSR register.
The T0CSR.RST bit is cleared automatically upon restart of
the 16-bit timer.
Note: If the user wishes to switch to power save or idle mode
after setting T0CSR.RST, the user must wait for reset opera-
tion to complete before doing the switch.
13.3 WATCHDOG OPERATION
The WATCHDOG is an 8-bit down counter that operates on
the rising edge of a specified clock source. Upon reset, the
WATCHDOG is disabled; it does not count and no WATCH-
DOG signal is generated. A write to either the WATCHDOG
Count (WDCNT) register or the WATCHDOG Service Data
Match (WDSDM) register starts the counter. The WATCH-
DOG counter counts down from the value programmed in to
the WDCNT register. Once started, only a reset can stop the
WATCHDOG from operating.
The WATCHDOG can be programmed to use either T0OUT
or T0IN as its clock source (the output and input of Timer T0,
respectively). The TWCFG.WDCT0I bit controls this clock
selection.
The software must periodically “service” the WATCHDOG.
There are two ways to service the WATCHDOG, the choice
depending on the programmed value of the WDSDME bit in
the Timer and WATCHDOG Configuration (TWCFG) register.
If TWCFG.WDSDME bit is cleared to 0, the WATCHDOG is
serviced by writing a value to the WDCNT register. The value
written to the register is reloaded into the WATCHDOG
counter. The counter then continues counting down from that
value.
If TWCFG.WDSDME bit is set to 1, the WATCHDOG is ser-
viced by writing the value 5C hex to the WATCHDOG Service
Data Match (WDSDM) register. This reloads the WATCH-
DOG counter with the value previously programmed into the
WDCNT register. The counter then continues counting down
from that value.
A WATCHDOG error signal is generated by any of the follow-
ing events:
—The WATCHDOG serviced too late .
—The WATCHDOG serviced too often.
—The WDSDM register is written with a value other than
5C hex when WDSDM type servicing is enabled
(TWCFG.WDSDME=1).
A WATCHDOG error condition resets the device.
13.3.1 Register Locking
The Timer and WATCHDOG Configuration (TWCFG) regis-
ter is used to set the WATCHDOG configuration. It controls
the WATCHDOG clock source (T0IN or T0OUT), the type of
WATCHDOG servicing (using WDCNT or WDSDM), and the
locking state of the TWCFG, TWCPR, TIMER0, T0CSR, and
WDCNT registers. A register that is locked cannot be read or
written. A write operation is ignored and a read operation re-
turns unpredictable results.
If the TWCFG register is itself locked, it remains locked until
the device is reset. Any other locked registers also remain
locked until the device is reset. This feature prevents a run-
away program from tampering with the programmed
WATCHDOG function.
13.3.2 Power Save Mode Operation
The Timer and WATCHDOG Module is active in both the
Power Save and Idle modes. The clocks and counters con-
tinue to operate normally in these modes. The WDSDM reg-
ister is accessible in the Power Save and Idle modes, but the
other TWM registers are accessible only in the Active mode.
Therefore, WATCHDOG servicing must be carried out using
the WDSDM register in the Power Save or Idle mode.
In the Halt mode, the entire device is frozen, including the
Timer and WATCHDOG Module. Upon return to the Active
mode, operation of the module resumes at the point at which
it was stopped.
Note: After a restart or WATCHDOG service through WD-
CNT, do not enter Power Save mode for a period equivalent
to 5 slow clock cycles.
13.4 TWM REGISTERS
The TWM registers controls the operation of the Timing and
WATCHDOG Module. There are six such registers:
•Timer and WATCHDOG Configuration Register (TWCFG)
•Timer and WATCHDOG Clock Prescaler Register
(TWCP)
•TWM Timer 0 Register (TWMT0)
•TWMT0 Control and Status Register (T0CSR)
•WATCHDOG Count Register (WDCNT)
•WATCHDOG Service Data Match Register (WDSDM)
The WDSDM register is accessible in both Active and Power
Save mode. The other TWM registers are accessible only in
Active mode.
13.4.1 Timer and WATCHDOG Configuration Register
(TWCFG)
The TWCFG register is a byte-wide, read/write register that
selects the WATCHDOG clock input and service method,
and also allows the WATCHDOG registers to be selectively
locked. Once a bit is set, that bit cannot be cleared until the
device resets. Upon reset, the non-reserved bits of the regis-
ter are all cleared to 0. The register format is shown below.
LTWCFG Lock TWCFG Register. When cleared to 0, ac-
cess to the TWCFG register is allowed. When
set to 1, the TWCFG register is locked. A
7 6 5 4 3 2 1 0
Reserve
dWDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
Obsolete
www.national.com 44
locked register cannot be read or written; a
read operation returns unpredictable values
and a write operation is ignored. Locking the
TWCFG register remains in effect until the de-
vice is reset.
LTWCP Lock TWCP Register. When cleared to 0, ac-
cess to the TWCP register is allowed. When
set to 1, the TWCP register is locked.
LTWMT0 Lock TWMT0 Register. When cleared to 0, ac-
cess to the TWMT0 and T0CSR registers are
allowed. When set to 1, the TWMT0 and
T0CSR registers are locked.
LWDCNT Lock LDWCNT Register. When cleared to 0,
access to the LDWCNT register is allowed.
When set to 1, the LDWCNT register is locked.
WDCT0I WATCHDOG Clock from T0IN. When cleared
to 0, the T0OUT signal (the output of Timer T0)
is used as the WATCHDOG clock. When set to
1, the T0IN signal (the prescaled slow clock) is
used as the WATCHDOG clock.
WDSDME WATCHDOG Service Data Match Enable.
When cleared to 0, WATCHDOG servicing is
accomplished by writing a count value to the
WDCNT register; write operations to the
WATCHDOG Service Data Match (WDSDM)
register are ignored. When set to 1, WATCH-
DOG servicing is accomplished by writing the
value 5C hex to the WDSDM register.
13.4.2 Timer and WATCHDOG Clock Prescaler
Register (TWCP)
The TWCP register is a byte-wide, read/write register that de-
fines the prescaler value used for dividing the low frequency
clock to generate the T0IN clock. Upon reset, the non-re-
served bits of the register are cleared to 0. The register for-
mat is shown below.
MDIV Main Clock Divide. This 3-bit field defines the
prescaler factor used for dividing the low speed
device clock to create the T0IN clock. The al-
lowed 3-bit values and the corresponding clock
divisors and clock rates are listed below.
13.4.3 TWM Timer 0 Register (TWMT0)
The TWMT0 register is a word-wide, read/write register that
defines the T0OUT interrupt rate. Upon reset, TWMT0 regis-
ter is initialized to FFFF hex. The register format is shown be-
low.
PRESET Timer T0 Preset. Timer T0 is reloaded with this
value on each underflow. Thus, the frequency
of the Timer T0 interrupt is the frequency of
T0IN divided by (PRESET+1). The allowed val-
ues of PRESET are 0001 hex through FFFF
hex.
13.4.4 TWMT0 Control and Status Register (T0CSR)
The T0CSR register is a byte-wide, read/write register that
controls Timer T0 and shows its current status. Upon reset,
the non-reserved bits of the register are cleared to 0. The
register format is shown below.
RST Restart. When this bit is set to 1, it forces the
timer to reload the value in the TWMT0 register
on the next rising edge of the selected input
clock. The RST bit is reset automatically by the
hardware on the same rising edge of the se-
lected input clock. Writing a 0 to this bit position
has no effect. Upon reset, the non-reserved
bits of the register are cleared to 0.
TC Terminal Count. This bit is set to 1 by the hard-
ware when the Timer T0 count reaches zero
and is cleared to 0 when the software reads the
T0CSR register. It is a read-only bit. Any data
written to this bit position is ignored.
T0INTE Timer T0 Interrupt Enable. When this bit is set
to 1, it enables an interrupt to the CPU each
time the Timer T0 count reaches zero. When
this bit is cleared to 0, Timer T0 interrupts are
disabled.
13.4.5 WATCHDOG Count Register (WDCNT)
The WDCNT register is a byte-wide, write-only register that
holds the value that is loaded into the WATCHDOG counter
each time the WATCHDOG is serviced. The WATCHDOG is
started by the first write to this register. Each successive write
to this register restarts the WATCHDOG count with the writ-
ten value. Upon reset, this register is initialized to 0F hex.
13.4.6 WATCHDOG Service Data Match Register
(WDSDM)
The WSDSM register is a byte-wide, write-only register used
for servicing the WATCHDOG. When this type of servicing is
enabled (TWCFG.WDSDME=1), the WATCHDOG is ser-
viced by writing the value 5C hex to the WSDSM register.
Each such servicing reloads the WATCHDOG counter with
the value previously written to the WDCNT register. Writing
any data other than 5C hex triggers a WATCHDOG error.
Writing to the register more than once in one WATCHDOG
clock cycle also triggers a WATCHDOG error signal. If this
type of servicing is disabled (TWCFG.WDSDME=0), any
write to the WSDSM register is ignored.
76543210
Reserved MDIV
MDIV Clock Divisor TOIN Frequency
(fSCLK=32.768 kHz)
000 1 32.768 kHz
001 2 16.384 kHz
010 4 8.192 kHz
011 84.096 kHz
100 16 2.048 kHz
101 32 1.024 kHz
other Reserved N/A
15 14 13 12 11 10 9876543210
PRESET
76543 2 10
Reserved T0INTE TC RST
Obsolete
45 www.national.com
13.5 WATCHDOG PROGRAMMING
PROCEDURE
The highest level of protection against software errors is
achieved by programming and then locking the WATCHDOG
registers and using the WDSDM register for servicing. This is
the procedure:
1. Write the desired values into the TWM Clock Prescaler
register (TWCP) and the TWM Timer 0 register
(TWMT0) to control the T0IN and T0OUT clock rates.
The frequency of T0IN can be programmed to any of six
frequencies ranging from 1/32*fSLCLK to fSLCLK (1.024
kHz to 32.768 kHz if SLCLK is 32.768 kHz). The fre-
quency of T0OUT is equal to the frequency of T0IN di-
vided by (1+PRESET), where PRESET is the value
written to the TWMT0 register.
2. Configure the WATCHDOG clock to use either T0IN or
T0OUT by setting or clearing the TWCFG.WDCT0I bit.
3. Write the initial value into the WDCNT register. This
starts operation of the WATCHDOG and specifies the
maximum allowed number of WATCHDOG clock cycles
between service operations.
4. Lock the WATCHDOG registers and enable the
WATCHDOG Service Data Match Enable function by
setting bits 0, 1, 2, 3, and 5 in the TWCFG register.
5. Service the WATCHDOG by periodically writing the val-
ue 5C hex to the WDSDM register at an appropriate
rate. Servicing must occur at least once per period pro-
grammed into the WDCNT register, but no more than
once in a single WATCHDOG input clock cycle.
Obsolete
www.national.com 46
14.0 Multi-Function Timer
The Multi-Function Timer (MFT16) module contains two inde-
pendent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counters. Each timer/counter
unit offers a choice of clock sources for operation and can be
configured to operate in any of the following modes:
•Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter
•Dual Input Capture mode, which measures the elapsed
time between occurrences of external events, and which
also provides a general-purpose timer/counter
•Dual Independent Timer mode, which generates system
timing signals or counts occurrences of external events
•Single Input Capture and Single Timer mode, which pro-
vides one external event counter and one system timer
The two timer units, MFT1 and MFT2, are identical in opera-
tion and separately programmable. Each timer unit uses two
I/O pins, called T1A and T1B (for Timer MFT1) or T2A and
T2B (for Timer MFT2). The timer I/O pins are alternate func-
tions of the Port F I/O pins.
In the description of the timers, the lower-case letter “n” rep-
resents the timer number, either 1 or 2. For example, “TnA”
means I/O pin T1A or T2A.
14.1 TIMER STRUCTURE
Figure10 is a block diagram showing the internal structure of
each timer. There are two main functional blocks: a Timer/
Counter and Action block and a Clock Source block. The
Timer/Counter and Action block contains two separate timer/
counter units, called Timer/Counter I and Timer/Counter II (a
total of four timer/counter unit in both MFT1 and MFT2).
14.1.1 Timer/Counter Block
The Timer/Counter block contains the following functional
blocks:
—two 16-bit counters, Timer/Counter I (TnCNT1) and
Timer/Counter II (TnCNT2)
—two 16-bit reload/capture registers, TnCRA and
TnCRB
—control logic necessary to configure the timer to oper-
ate in any of the four operating modes
—interrupt control and I/O control logic
In a power-saving mode that uses the low-frequency (32.768
kHz) clock as the system clock, the synchronization circuit re-
quires that the slow clock operate at no more than one-fourth
the speed of the 32.768 kHz system clock.
14.1.2 Clock Source Block
The Clock Source block generates the signals used to clock
the two timer/counter registers. The internal structure of the
Clock Source block is shown in Figure11.
Counter Clock Source Select
There are two clock source selectors that allow the software
to independently select the clock source for each of the two
16-bit counters from any one of the following sources:
—no clock (which stops the counter)
—prescaled system clock
—external event count based on TnB
—pulse accumulate mode based on TnB
—slow clock (derived from the low-frequency oscillator or
divided from the high-speed oscillator)
Prescaler
The 5-bit clock prescaler allows the software to run the timer
with a prescaled clock signal. The prescaler consists of a 5-
bit read/write prescaler register (TnPRSC) and a 5-bit down
counter. The system clock is divided by the value contained
in the prescaler register plus 1. Thus, the timer clock period
Figure 10.Multi-Function Timer Block Diagram
Reload/Capture
A
Timer/Counter
1
Reload/Capture
Timer/Counter
2
B
Timer/Counter
Clock Source Action
System
Clock
TnB
Toggle/Capture/Interrupt
Mode Select + Control
PWM/Capture/Counter
TnA
External Event
Interrupt A
Interrupt B
Clock Prescaler/Selector
Obsolete
47 www.national.com
can be set to any value from 1 to 32 divisions of the system
clock period. The prescaler register and down counter are
both cleared upon reset.
External Event Clock
The TnB I/O pin can be configured to operate as an external
event input clock for either of the two 16-bit counters. This in-
put can be programmed to detect either rising or falling edg-
es. The minimum pulse width of the external signal is one
system clock cycle. This means that the maximum frequency
at which the counter can run in this mode is one-half of the
system clock frequency. This clock source is not available in
the capture modes (modes 2 and 4) because the TnB pin is
used as one of the two capture inputs.
Pulse Accumulate Mode
The counter can also be configured to count prescaler output
clock pulses when the TnB is high and not count when TnB
is low, as illustrated in Figure12. The resulting count is an in-
dicator of the cumulative time that TnB is high. This is called
the “pulse accumulate” mode. In this mode, an AND gate
generates a clock signal for the counter whenever a prescal-
er clock pulse is generated and TnB input is high. (The polar-
ity of the TnB signal is programmable, so the counter can
count when TnB is low rather than high.) The pulse accumu-
late mode is not available in the capture modes (modes 2 and
4) because the TnB pin is used as one of the two capture in-
puts.
Slow Clock
The slow clock is generated by the Dual Clock and Reset
(CLK2RES) module. The clock source is either the divided
fast clock or the external 32.768 kHz clock crystal (if available
and selected). The slow clock can be used as the clock
source for the two 16-bit counters. Because the slow clock
can be asynchronous to the system clock, a circuit is provid-
ed to synchronize the clock signal to the high-frequency sys-
tem clock before it is used for clocking the counters. The
synchronization circuit requires that the slow clock operate at
no more than one-fourth the speed of the system clock.
Limitations in Low-Power Modes
The Power Save mode uses the low-frequency clock as the
system clock. In this mode, the slow clock cannot be used as
a clock source for the timers because both CLK and SLCLK
are driven then at the same frequency, and the 2:1 system-
clock to input clock ratio needed for the synchronization can-
not be maintained. However, the External Event Clock and
Pulse Accumulate Mode will still work, as long as the external
event pulses are at least the size of the whole slow-clock pe-
riod. Using the prescaled system clock will also work, but at
a much slower rate than the original system clock.
Figure 11.Clock Source Block Diagram
Prescaler Register
TnPRSC
Prescaler Counter
5-bit
System
Clock
Reset
TnB
Pulse
Accumulate
External
Event
No Clock
Prescaled
Clock
Counter I
Clock
Select
Counter II
Clock
Select
Counter I
Clock
Counter II
Clock
Synchr.
Figure 12.Pulse Accumulate Mode Operation
TnB
Prescaler Output
Counter Clock
Obsolete
www.national.com 48
Some Power Save modes stops the system clock (the high-
frequency and/or low-frequency clock) completely. If the sys-
tem clock is stopped, the timer stops counting until the sys-
tem clock resumes operation.
In the Idle or Halt mode, the system clock stops completely,
which stops the operation of the timers. In that case, the tim-
ers stop counting until the system clock resumes operation.
14.2 TIMER OPERATING MODES
Each timer/counter unit can be configured to operate in any
of the following modes:
•Processor-Independent Pulse Width Modulation (PWM)
mode
•Dual Input Capture mode
•Dual Independent Timer mode
•Single Input Capture and Single Timer mode
Upon reset, the timers are disabled. To configure and start
the timers, the software must write a set of values to the reg-
isters that control the timers. The registers are described in
Section14.5.
14.2.1 Mode 1: Processor-Independent PWM
Mode 1 is the Processor-Independent Pulse Width Modula-
tion (PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a separate
general-purpose timer/counter.
Figure13 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 1. Timer/Counter I (TnCNT1)
functions as the time base for the PWM timer. It counts down
at the clock rate selected for the counter. When an underflow
occurs, the timer register is reloaded alternately from the
TnCRA and TnCRB register, and counting proceeds down-
ward from the loaded value.
On the first underflow, the timer is loaded from TnCRA, then
from TnCRB on the next underflow, then from TnCRA again
on the next underflow, and so on. Every time the counter is
stopped and restarted, it always obtains its first reload value
from TnCRA. This is true whether the timer is restarted upon
reset, after entering Mode 1 from another mode, or after stop-
ping and restarting the clock with the Timer/Counter I clock
selector.
The timer can be configured to toggle the TnA output bit upon
each underflow. This generates a clock signal on TnA with
the width and duty cycle determined by the values stored in
the TnCRA and TnCRB registers. This is a “processor-inde-
pendent” PWM clock because once the timer is set up, no
more action is required from the CPU to generate a continu-
ous PWM signal.
The timer can be configured to generate separate interrupts
upon reload from TnCRA and TnCRB. The interrupts can be
enabled or disabled under software control. The CPU can de-
termine the cause of each interrupt by looking at the TnAPND
and TnBPND flags, which are set by the hardware upon each
occurrence of a timer reload.
In Mode 1, Timer/Counter II (TnCNT2) can be used either as
a simple system timer, an external event counter, or a pulse
accumulate counter. The clock counts down using the clock
selected with the Timer/Counter II clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TnDIEN bit.
Figure 13.Mode 1: Processor-Independent PWM Block Diagram
Reload A = Time 1
Timer/Counter I
Reload B = Time 2
Timer I
Clock
Underflow
TnA
TnAIEN
TnAPND
TnCNT1
TnCRA
TnCRB
TnBIEN
TnBPND
Timer
Interrupt A
Timer
Interrupt B
TnAEN
Timer/Counter II
TnCNT2
Timer II
Clock TnDIEN
TnDPND
Timer
Interrupt D
TnB
Clock
Selector
Underflow
Obsolete
49 www.national.com
14.2.2 Mode 2: Dual Input Capture
Mode 2 is the Dual Input Capture mode, which measures the
elapsed time between occurrences of external events, and
which also provides a separate general-purpose timer/
counter.
Figure14 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 2. The time base of the capture
timer depends on Timer/Counter I, which counts down using
the clock selected with the Timer/Counter I clock selector.
The TnA and TnB pins function as capture inputs. A transi-
tion received on the TnA pin transfers the timer contents to
the TnCRA register. Similarly, a transition received on the
TnB pin transfers the timer contents to the TnCRB register.
Each input pin can be configured to sense either rising or fall-
ing edges.
The TnA and TnB inputs can be configured to preset the
counter to FFFF hex upon reception of a valid capture event.
In this case, the current value of the counter is transferred to
the corresponding capture register and then the counter is
preset to FFFF hex. Using this approach allows the software
to determine the on-time and off-time and period of an exter-
nal signal with a minimum of CPU overhead.
The values captured in the TnCRA register at different times
reflect the elapsed time between transitions on the TnA pin.
The same is true for the TnCRB register and the TnB pin. The
input signal on TnA or TnB must have a pulse width equal to
or greater than one system clock cycle.
There are three separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
three interrupt events are reception of a transition on TnA, re-
ception of a transition on TnB, and underflow of the TnCNT1
counter. The enable bits for these events are TnAIEN, TnBI-
EN, and TnCIEN, respectively.
In Mode 2, Timer/Counter II (TnCNT2) can be used as a sim-
ple system timer. The clock counts down using the clock se-
lected with the Timer/Counter II clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TnDIEN bit.
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
counter or to operate in the pulse accumulate mode because
the TnB input is used as a capture input. Attempting to select
one of these configurations will cause one or both counters
to stop.
Figure 14.Mode 2: Dual Input Capture Block Diagram
Capture A
Timer/Counter I
Capture B
TnCNT1
TnCRA
TnCRB
Timer/Counter II
TnCNT2
Timer I
Clock
Timer II
Clock
TnB
TnA
TnAIEN
TnAPND
Timer
Interrupt I
TnBIEN
TnBPND
Timer
Interrupt I
TnCIEN
TnCPND Timer
Interrupt I
Underflow
TnDIEN
TnDPND
Timer
Interrupt II
Underflow
TnAEN
Preset
Preset
TnBEN
Obsolete
www.national.com 50
14.2.3 Mode 3: Dual Independent Timer/Counter
Mode 3 is the Dual Independent Timer mode, which gener-
ates system timing signals or counts occurrences of external
events.
Figure15 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 3. The timer is configured to oper-
ate as a dual independent system timer or dual external
event counter. In addition, Timer/Counter I can generate a
50% duty cycle PWM signal on the TnA pin. The TnB pin can
be used as an external event input or pulse accumulate input
and can be used as the clock source for either Timer/Counter
I or Timer/Counter II. Both counters can also be clocked by
the prescaled system clock.
Timer/Counter I (TnCNT1) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRA
register and counting proceeds down from the reloaded val-
ue. In addition, the TnA pin is toggled on each underflow if
this function is enabled by the TnAEN bit. The initial state of
the TnA pin is software-programmable. When the TnA pin is
toggled from low to high, it sets the TnCPND interrupt pend-
ing flag and also generates an interrupt if the interrupt is en-
abled by the TnAIEN bit.
Because TnA toggles on every underflow, a 50% duty cycle
PWM signal can be generated on TnA without any further ac-
tion from the CPU once the pulse train is initiated.
Timer/Counter II (TnCNT2) counts down at the rate of the se-
lected clock. Upon underflow, it is reloaded from the TnCRB
register and counting proceeds down from the reloaded val-
ue. In addition, each underflow sets the TnDPND interrupt
pending flag and generates an interrupt if the interrupt is en-
abled by the TnDIEN bit.
14.2.4 Mode 4: Input Capture Plus Timer
Mode 4 is the Single Input Capture and Single Timer mode,
which provides one external event counter and one system
timer.
Figure16 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 4. This mode offers a combination
of Mode 3 and Mode 2 functions. Timer/Counter I is used as
a system timer as in Mode 3 and Timer/Counter II is used as
a capture timer as in Mode 2, but with a single input rather
than two inputs.
Timer/Counter I (TnCNT1) operates the same as in Mode 3.
It counts down at the rate of the selected clock. Upon under-
flow, it is reloaded from the TnCRA register and counting pro-
ceeds down from the reloaded value. The TnA pin is toggled
on each underflow if this function is enabled by the TnAEN
bit. When the TnA pin is toggled from low to high, it sets the
TnCPND interrupt pending flag and also generates an inter-
rupt if the interrupt is enabled by the TnAIEN bit. A 50% duty
cycle PWM signal can be generated on TnA without any fur-
ther action from the CPU once the pulse train is initiated.
Figure 15.Mode 3: Dual Independent Timer/Counter Block Diagram
Reload A
Timer/Counter I
Reload B
Timer I
Clock TnA
TnAIEN
TnAPND
TnCNT1
TnCRA
TnCRB
TnDIEN
TnDPND
Timer
Interrupt I
Timer
Interrupt II
TnAEN
Timer/Counter II
TnCNT2
Timer II
Clock
TnB
Clock
Selector
Underflow
Underflow
Obsolete
51 www.national.com
Timer/Counter II (TnCNT1) counts down at the rate of the se-
lected clock. The TnB pin functions as the capture input. A
transition received on TnB transfers the timer contents to the
TnCRB register. The input pin can be configured to sense ei-
ther rising or falling edges.
The TnB input can be configured to preset the counter to
FFFF hex upon reception of a valid capture event. In this
case, the current value of the counter is transferred to the
capture register and then the counter is preset to FFFF hex.
The values captured in the TnCRB register at different times
reflect the elapsed time between transitions on the TnA pin.
The input signal on TnB must have a pulse width equal to or
greater than one system clock cycle.
There are two separate interrupts associated with the cap-
ture timer, each with its own enable bit and pending flag. The
two interrupt events are reception of a transition on TnB and
underflow of the TnCNT2 counter. The enable bits for these
events are TnBIEN and TnDIEN, respectively.
Neither Timer/Counter I (TnCNT1) nor Timer/Counter II
(TnCNT2) can be configured to operate as an external event
counter or to operate in the pulse accumulate mode because
the TnB input is used as a capture input. Attempting to select
one of these configurations will cause one or both counters
to stop. In this mode, Timer/Counter II must be enabled at all
times.
14.3 TIMER INTERRUPTS
Each Multi-Function Timer unit has four interrupt sources,
designated A, B, C, and D. Interrupt sources A, B, and C are
mapped into a single system interrupt called Timer Interrupt
I, while interrupt source D is mapped into a system interrupt
called Timer Interrupt II. Each of the four interrupt sources
has its own enable bit and pending flag. The enable flags are
named TnAIEN, TnBIEN, TnCIEN, and TnDIEN. The pend-
ing flags are named TnAPND, TnBPND, TnCPND, and TnD-
PND.
For Multi-Function Timer unit MFT1, Timer Interrupts I and II
are system interrupts T1A and T1B (IRQ13 and IRQ12), re-
spectively. For Multi-Function Timer unit MFT2, Timer Inter-
rupts I and II are system interrupts T2A and T2B (IRQ11 and
IRQ10), respectively.
Table15 shows the events that trigger interrupts A, B, C, and
D in each of the four operating modes. Note that some inter-
rupt sources are not used in some operating modes, as indi-
cated by the notation “N/A” (Not Applicable) in the table.
14.4 TIMER I/O FUNCTIONS
Each Multi-Function Timer unit uses two I/O pins, called T1A
and T1B (for Timer MFT1) or T2A and T2B (for Timer MFT2).
The function of each pin depends on the timer operating
mode and the TnAEN and TnBEN enable bits. Table16
shows the functions of the pins in each operating mode, and
for each combination of enable bit settings.
When pin TnA is configured to operate as a PWM output
(TnAEN = 1), the state of the pin is toggled on each under-
Figure 16.Mode 4: Input Capture Plus Timer Block Diagram
Reload A
Timer/Counter I
Capture B
Timer I
Clock TnA
TnAIEN
TnAPND
TnCNT1
TnCRA
TnCRB
Timer
Interrupt I
TnATEN
Timer/Counter II
TnCNT2
Timer II
Clock
Underflow
TnDIEN
TnDPND Timer
Interrupt II
TnBIEN
TnBPND
Timer
Interrupt I
TnB
TnBEN
Preset
Obsolete
www.national.com 52
flow of the TnCNT1 counter. In this case, the initial value on
the pin is determined by the TnAOUT bit. For example, to
start with TnA high, the software should set the TnAOUT bit
to 1 prior to enabling the timer clock. This option is available
only when the timer is configured to operate in Mode 1, 3, or
4 (in other words, when TnCRA is not used in Capture
mode).
14.5 TIMER REGISTERS
The following CPU-accessible registers are used to control
the Multi-Function Timers:
•Clock Prescaler Register (TnPRSC)
•Clock Unit Control Register (TnCKC)
•Timer/Counter I Register (TnCNT1)
•Timer/Counter II Register (TnCNT2)
•Reload/Capture A Register (TnCRA)
•Reload/Capture B Register (TnCRB)
•Timer Mode Control Register (TnCTRL)
•Timer Interrupt Control Register (TnICTL)
•Timer Interrupt Clear Register (TnICLR)
14.5.1 Clock Prescaler Register (TnPRSC)
The Clock Prescaler (TnPRSC) register is a byte-wide, read/
write register that holds the current value of the 5-bit clock
prescaler (CLKPS). This register is cleared upon reset. The
register format is shown below.
CLKPS Clock Prescaler. When the timer is configured
to use the prescaled clock, the system clock is
divided by CLKPS+1 to produce the timer
clock. Thus, the system clock divide-by factor
can range from 1 to 32.
14.5.2 Clock Unit Control Register (TnCKC)
The Clock Unit Control (TnCKC) register is a byte-wide, read/
write register that selects the clock source for each timer/
counter. This register is cleared upon reset, which disables
the timer/counters. The register format is shown below.
C1CSEL Counter I Clock Select. This 3-bit field defines
the clock mode for Timer/Counter I as follows:
000 = no clock (timer/counter I stopped)
001 = prescaled system clock
010 = external event on TnB (modes 1 and 3
only)
Table 15Timer Interrupts Overview
Sys. Int. Interrupt
pending
flag
Mode 1 Mode 2 Mode 3 Mode 4
PWM + Counter Dual Input Capture +
counter Dual Counter Single Capture +
counter
Timer
Int. I
(TnA)
TnAPND TnCNT1 reload from
TnCRA Input capture on TnA
transition TnCNT1 reload from
TnCRA TnCNT1 reload from
TnCRA
TnBPND TnCNT1 reload from
TnCRB Input Capture on TnB
transition N/A Input Capture on TnB
transition
TnCPND N/A TnCNT1 underflow N/A N/A
Timer
Int. II
(TnB)
TnDPND TnCNT2 underflow TnCNT2 underflow TnCNT2 reload from
TnCRB TnCNT2 underflow
Table 16Timer I/O Functions
I/O TnAEN
TnBEN
Mode 1 Mode 2 Mode 3 Mode 4
PWM + Counter Dual Input Capture +
counter Dual Counter Single Capture +
counter
TnA TnAEN=0
TnBEN=X No Output Capture TnCNT1 into
TnCRA No Output toggle No Output toggle
TnAEN=1
TnBEN=X Toggle Output on
underflow of TnCNT1 Capture TnCNT1 into
TnCRA and preset
TnCNT1
Toggle Output on
underflow of TnCNT1 Toggle Output on
underflow of TnCNT1
TnB TnAEN=X
TnBEN=0 Ext. Event or Pulse
Accumulate Input Capture TnCNT1 into
TnCRB Ext. Event or Pulse
Accumulate Input Capture TnCNT2 into
TnCRB
TnAEN=X
TnBEN=1 Ext. Event or Pulse
Accumulate Input Capture TnCNT1 into
TnCRB and preset
TnCNT1
Ext. Event or Pulse
Accumulate Input Capture TnCNT2 into
TnCRB and preset
TnCNT2
7 6 5 4 3 2 1 0
Reserved CLKPS
7 6 5 4 3 2 1 0
Reserved C2CSEL C1CSEL
Obsolete
53 www.national.com
011 = pulse accumulate mode based on TnB
(modes 1 and 3 only)
100 = slow clock *
other values = undefined
C2CSEL Counter II Clock Select. This 3-bit field defines
the clock mode for Timer/Counter II as follows:
000 = no clock (Timer/Counter II stopped
modes 1, 2, and 3 only)
001 = prescaled system clock
010 = external event on TnB (modes 1 and 3
only)
011 = pulse accumulate mode based on TnB
(modes 1 and 3 only)
100 = slow clock *
other values = undefined
* Operation of the slow clock is determined by the CRC-
TRL.SCLK control bit, as described in Section11.6.1.
14.5.3 Timer/Counter I Register (TnCNT1)
The Timer/Counter I (TnCNT1) register is a word-wide, read/
write register that holds the current count value for Timer/
Counter I. The register contents are not affected by a reset
and are unknown upon power-up.
14.5.4 Timer/Counter II Register (TnCNT2)
The Timer/Counter II (TnCNT2) register is a word-wide, read/
write register that holds the current count value for Timer/
Counter II. The register contents are not affected by a reset
and are unknown upon power-up.
14.5.5 Reload/Capture A Register (TnCRA)
The Reload/Capture A (TnCRA) register is a word-wide,
read/write register that holds the reload or capture value for
Timer/Counter I. The register contents are not affected by a
reset and are unknown upon power-up.
14.5.6 Reload/Capture B Register (TnCRB)
The Reload/Capture B (TnCRB) register is a word-wide,
read/write register that holds the reload or capture value for
Timer/Counter II. The register contents are not affected by a
reset and are unknown upon power-up.
14.5.7 Timer Mode Control Register (TnCTRL)
The Timer Mode Control (TnCTRL) register is a byte-wide,
read/write register that sets the operating mode of the timer/
counter and the TnA and TnB pins. This register is cleared
upon reset. The register format is shown below.
MDSEL Mode Select. This 2-bit field sets the operating
mode of the timer/counter as follows:
00 = Mode 1: PWM plus system timer
01 = Mode 2: Dual Input Capture plus system
timer
10 = Mode 3: Dual Timer/Counter
11 = Mode 4: Single Input Capture and Single
Timer
TnAEDG TnA Edge Polarity. When cleared (0), input pin
TnA is sensitive to falling edges (high to low
transitions). When set (1), input pin TnA is sen-
sitive to rising edges (low to high transitions).
TnBEDG TnB Edge Polarity. When cleared (0), input pin
TnB is sensitive to falling edges (high to low
transitions). When set (1), input pin TnB is sen-
sitive to rising edges (low to high transitions). In
pulse accumulate mode, when this bit is set (1),
the counter is enabled only when TnB is high;
when this bit is cleared (0), the counter is en-
abled only when TnB is low.
TnAEN TnA Enable. When set (1), the TnA pin is en-
abled to operate as a preset input or as a PWM
output, depending on the timer operating
mode. In Mode 2 (Dual Input Capture), a tran-
sition on the TnA pin presets the TnCNT1
counter to FFFF hex. In the other modes, TnA
functions as a PWM output. When this bit is
cleared (0), operation of the pin for the timer/
counter is disabled.
TnBEN TnB Enable. When set (1), the TnB pin in en-
abled to operate in Mode 2 (Dual Input Cap-
ture) or Mode 4 (Single Input Capture and
Single Timer). A transition on the TnB pin pre-
sets the corresponding timer/counter to FFFF
hex (TnCNT1 in Mode 2 or TnCNT2 in Mode
4). When this bit is cleared (0), operation of the
pin for the timer/counter is disabled. This bit
setting has no effect in Mode 1 or Mode 3.
TnAOUT TnA Output Data. This is a status bit that indi-
cates the current state of the TnA pin when the
pin is used as a PWM output. When set (1), the
TnA pin is high; when cleared (0), the TnA pin
is low. The hardware sets and clears this bit,
but the software can also read or write this bit
at any time and thus control the state of the out-
put pin. In case of conflict, a software write has
precedence over a hardware update. This bit
setting has no effect when TnA is used as an
input.
14.5.8 Timer Interrupt Control Register (TnICTL)
The Timer Interrupt Control (TnICTL) register is a byte-wide,
read/write register that contains the interrupt enable bits and
interrupt pending bits for the four timer interrupt sources,
designated A, B, C, and D. The condition that causes each
type of interrupt depends on the operating mode, as shown
in Table15.
This register is cleared upon reset. The register format is
shown below.
TnAPND Timer Interrupt Source A Pending. When this
bit is set (1), it indicates that timer interrupt con-
dition “A” has occurred. When this bit is cleared
(0), it indicates that the interrupt condition has
not occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table15
This bit can be set by the hardware or by the
software. To clear this bit, the software must
use the Timer Interrupt Clear Register (TnI-
7 6 5 4 3 2 1 0
Reserved TnAOUT TnBEN TnAEN TnBEDG TnAEDG MDSEL 76543210
TnDIEN TnCIEN TnBIEN TnAIEN TnDPND TnCPND TnBPND TnAPND
Obsolete
www.national.com 54
CLR). Any attempt by the software to directly
write a 0 to this bit is ignored.
TnBPND Timer Interrupt Source B Pending. See the de-
scription of TnAPND.
TnCPND Timer Interrupt Source C Pending. See the de-
scription of TnAPND.
TnDPND Timer Interrupt Source D Pending. See the de-
scription of TnAPND.
TnAIEN Timer Interrupt A Enable. When set (1), this bit
enables an interrupt on each occurrence of in-
terrupt condition “A.” When cleared (0), an oc-
currence of interrupt condition “A” does not
generate an interrupt to the CPU, but still sets
the associated pending flag (TnAPND). For an
explanation of interrupt conditions A, B, C, and
D, see Table15.
TnBIEN Timer Interrupt B Enable. See the description
of TnAIEN.
TnCIEN Timer Interrupt C Enable. See the description
of TnAIEN.
TnDIEN Timer Interrupt D Enable. See the description
of TnAIEN.
14.5.9 Timer Interrupt Clear Register (TnICLR)
The Timer Interrupt Clear (TnICLR) register is a byte-wide,
write-only register that allows the software to clear the TnAP-
ND, TnBPND, TnCPND, and TnDPND bits in the Timer Inter-
rupt Control (TnICTRL) register. The register format is shown
below.
TnACLR Timer Pending A Clear. When written with a 1,
the Timer Interrupt Source A Pending bit
(TnAPND) is cleared in the Timer Interrupt
Control register (TnICTL). Writing a 0 to the
TnACLR bit has no effect.
TnBCLR Timer Pending B Clear. See the description of
TnACLR.
TnCCLR Timer Pending C Clear. See the description of
TnACLR.
TnDCLR Timer Pending D Clear. See the description of
TnACLR.
7 6 5 4 3 2 1 0
Reserved TnDCLR TnCCLR TnBCLR TnACLR
Obsolete
55 www.national.com
15.0 MICROWIRE/SPI
MICROWIRE/PLUS is a synchronous serial communications
protocol, originally implemented in National Semiconductor's
COPS™ and HPC™ families of microcontrollers to minimize
the number of connections, and therefore the cost, of com-
municating with peripherals.
The device has an enhanced MICROWIRE interface module
(MWSPI) that can communicate with all peripherals that con-
form to MICROWIRE or Serial Peripheral Interface (SPI)
specifications. This enhanced MICROWIRE interface is ca-
pable of operating as either a master or slave. Figure17
shows a typical enhanced MICROWIRE interface applica-
tion.
The enhanced MICROWIRE interface module includes the
following features:
—Programmable operation as a Master or Slave
—Programmable shift-clock frequency (master only)
—8-bit serial I/O data shift register
—Two modes of clocking data
—Serial clock can be low or high when idle
—Double read buffer (master mode only)
—Busy flag, Read Buffer Full flag, and Overrun flag for
polling and as interrupt sources
—Supports multiple masters
—Maximum bit rate of 4M bits/second (master and slave)
—Supports very low-end slaves with the Slave Ready
output
—Echo back enable/disable (Slave only)
15.1 MICROWIRE OPERATION
The MICROWIRE interface allows several devices to be con-
nected on one three-wire system. At any given time, one of
these devices operates as the master while all other devices
operate as slaves.
The master device supplies the synchronous clock (MSK) for
the serial interface and initiates the data transfer. The slave
devices respond by sending (or receiving) the requested da-
ta. Each slave device uses the master’s clock for serially
shifting data out (or in), while the master shifts the data in (or
out).
The three-wire system includes: the serial data in signal
(MDIDO for master mode, MDODI for slave mode), the serial
data out signal (MDODI for master mode, MDIDO for slave
mode) and the serial clock (MSK).
In slave mode, an optional fourth signal (MCS) may be used
to enable the slave transmit. At any given time, only one
slave can respond to the master. Each slave device has its
own chip select signal (MCS) for this purpose.
The MICROWIRE interface allows the device to operate ei-
ther as a master or slave. This is configured via the MMNS
bit.
Figure18 shows a block diagram of the enhanced MICROW-
IRE serial interface in the device.
15.1.1 Shifting
The MICROWIRE interface is a full duplex transmitter/receiv-
er. An 8-bit shifter is used for both transmitting and receiving.
The transmitted data is shifted out through MDODI pin (mas-
ter mode) or MDIDO pin (slave mode), starting with the most
significant bit. At the same time, the received data is shifted
in through MDIDO pin (master mode) or MDODI pin (slave
mode), also starting with the most significant bit first.
The shift in and shift out are controlled by the MSK clock. In
each clock cycle of MSK, one bit of data is transmitted/re-
ceived. The 8-bit shifter is accessible via the MWDAT regis-
ter. Reading the MWDAT register returns the value in the
read buffer. Writing to the MWDAT register updates the 8-bit
shifter.
15.1.2 Reading
The enhanced MICROWIRE interface implements a double
buffer on read. As illustrated in Figure18, the double read
buffer consists of the 8-bit shifter and a buffer, called the read
buffer.
The 8-bit shifter loads the read buffer with new data when the
data transfer sequence is completed and previous data in the
Figure 17.MICROWIRE Interface
DO
5Chip Select Lines
CS CS CS CS
MDIDO
DO
MDIDO
MDODI MDODI
DI DI DI DI
Master Slave
MSK MSK
SK SK SK SK
8-Bit
A/D 1K Bit
EEPROM LCD
Display
driver
VF
Display
Driver
I/O
Lines I/O
Lines
MCS
MCS
Obsolete
www.national.com 56
read buffer has been read. In master mode, an Overrun error
occurs when the read buffer is full, the 8-bit shifter is full and
a new data transfer sequence starts.
The “Receive Buffer Full” (MRBF) bit indicates if the MWDAT
register holds valid data. The MOVR bit indicates that an
overrun condition has occurred.
15.1.3 Writing
The “MICROWIRE Busy” (MBSY) bit indicates whether the
MWDAT register can be written. All write operations to the
MWDAT register update the shifter while the data contained in
the read buffer is not affected. Undefined results will occur if
the MWDAT register is written while the MBSY bit is set to 1.
15.1.4 Clocking Modes
Two clocking modes are supported: the normal mode and the
alternate mode.
In the normal mode, the output data is shifted out on the ris-
ing edge of MSK on the MDODI pin (master mode) or MDIDO
(slave mode). The input data, which is received via MDIDO
pin (master mode) or the MDODI pin (slave mode), is sam-
pled on the fallowing edge of MSK.
In the alternate mode, the output data is shifted out on the ris-
ing edge of MSK on the MDODI pin (master mode) or MDIDO
pin (slave mode). The input data, which is received via MDI-
DO pin (master mode) or MDODI pin (slave mode), is sam-
pled on the falling edge of MSK.
The clocking modes are selected with the MSKM bit. The
MIDL bit allows selection of the value of MSK when it is idle
(when there is no data being transferred). Various MSK clock
frequencies can be programmed via the MCDV bits. Figures
19, 20, 21, and 22 show the data transfer timing for the nor-
mal and the alternate modes with the MIDL bit equal to 0 and
equal to 1.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 6 is shifted out on the second leading edge of the
MSK clock. When data are shifted out on MDODI (master
mode) or MDIDO (slave mode) on the trailing edge of MSK,
bit 6 is shifted out on the first trailing edge of MSK.
15.2 MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the 8-bit shifter (MWDAT regis-
ter), eight clocks are generated to shift the eight bits of data
and then MSK goes idle again. The MSK idle state can be ei-
ther high or low, depending on the MIDL bit.
If MDIDO is sampled on the leading edge of MSK, a se-
quence of eight clock is generated after a delay that may
range from half a period of MSK to one and a half periods of
MSK. If MDIDO is sampled on the trailing edge of MSK, a se-
Figure 18.MICROWIRE Block Diagram
Master
Master
Slave
Slave
8-bit Shift Register
Master
Clock Prescaler + Select
8
Read Buffer
MWDAT
System Clock
Write Data
Read Data
Control + Status
Interrupt Request
Data In
Data Out
MSK
MCS
MRDY
MDODI
MDIDO
MSK
Obsolete
57 www.national.com
quence of eight clocks is generated after a delay that may
range from zero to one period of MSK.
15.3 SLAVE MODE
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO and MRDY (an optional signal) are placed in
TRI-STATE mode when MCS is inactive. Data transfer is en-
abled when MCS is active. MWCTL3.MBFL must be cleared
to 0.
The slave starts driving MDIDO when MCS is activated. The
most significant bit (MSB) of the 8-bit shifter is output onto the
MDIDO pin first. After eight clocks, the data transfer is com-
pleted.
Figure 19.Normal Mode, MIDL Bit = 0
Figure 20.Normal Mode, MIDL Bit = 1
Figure 21.Alternate Mode, MIDL Bit = 0
Data In
MSB msb-1 msb-2 5 Bit 1 Bit 0
End of Transfer
MSB msb-1 msb-2 Bit 1 Bit 0
Sample PointShift Out
Data Out
MSK
(lsb)
(lsb)
Data Out
Data In
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
End of Transfer
Sample Point
Shift Out
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
MSK
End of Transfer
Data Out
Data In
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
MSKn
Sample Point
Shift Out
Obsolete
www.national.com 58
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the “Echo
Enable” (MECH) bit is set to 1, the data received from MDO-
DI is transmitted on MDIDO in addition to being shifted to
MWDAT. If the MECH bit is cleared to 0, the data transmitted
on MDIDO is the data held in the MWDAT register, regard-
less of its validity. The master may negate the MCS signal to
synchronize the bit count between the master and the slave.
In the case that the slave is the only slave in the system, MCS
can be tied to VSS.
An additional output signal, MRDY, may be used. This signal
supports very low-end slaves by indicating to the master the
current status of the MICROWIRE channel.
Upon reset, MRDY is inactive. Before transfer starts, MRDY
should be asserted by setting the MWCTL3.MRDY bit.
MRDY is de-asserted when the data transfer of one data byte
has been completed.
MRDY is asserted again only by writing 1 to the MRDY bit.
This should be done after the MWDAT register is read.
15.4 INTERRUPT GENERATION
An interrupt is generated in any of the following cases:
•When the read buffer is full (MRBF=1) and the “Enable In-
terrupt for Read” bit is set (MEIR=1).
•Whenever the shifter is not busy, i.e. the MBSY bit is
cleared (MBSY=0) and the “Enable Interrupt for Write” bit
is set (MEIW=1).
•When an overrun condition occurs (MOVR is set to 1) and
the “Enable Interrupt on Overrun” bit is set (MEIO=1). This
usage is restricted to master mode.
Figure24 illustrates the various interrupt capabilities of this
module.
Figure 22.Alternate Mode, MIDL Bit = 1
End of Transfer
Sample PointShift Out
Data Out
Data In
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
msb msb-1 msb-2 Bit 1 Bit 0 (lsb)
MSKn
Figure 23.Slave, Normal Mode, MIDL Bit = 0, MRBF Bit = 1
MSK
Sample Point
(MSB)
Bit 7 In
(MSB)
Bit 7 Out Bit 6 Bit 5 Bit 1 Bit 0
Bit 6 Bit 5 Bit 1 Bit 0
End of Transfer
Shift Out READY Bit
Set to 1
MDIDO
MDODI
MCS
MRDY
Obsolete
59 www.national.com
15.5 MICROWIRE INTERFACE REGISTERS
The software interacts with the MICROWIRE interface by ac-
cessing the MICROWIRE registers. There are five such reg-
isters:
•MICROWIRE Data Register (MWDAT)
•MICROWIRE Control 1 Register (MWCTL1)
•MICROWIRE Control 2 Register (MWCTL2)
•MICROWIRE Control 3 Register (MWCTL3)
•MICROWIRE Status Register (MWSTAT)
15.5.1 MICROWIRE Data Register (MWDAT)
The MWDAT register is a byte-wide, read/write register used
to transmit and receive data through the MDODI and MDIDO
pins. Figure25 shows the hardware structure of the register.
Reading the MWDAT register returns the data received
through the MDIDO pin in master mode or the MDODI pin in
slave mode. This data is read from a buffer. After the CPU
reads the buffer, if new data is ready in the shifter, the hard-
ware immediately transfers the new value from the shifter to
the buffer.
Writing the MWDAT register loads the shifter directly without
buffering, thus overwriting any existing data in the shifter. The
data byte is shifted out through the MDODI pin in master
mode or through the MDIDO pin in slave mode, most signifi-
cant bit first.
The MWDAT register should be accessed only after a MI-
CROWIRE interrupt. Before the CPU reads the register, the
Read Buffer Full status bit should be set (MW-
STAT.MRBF=1). Before the CPU writes the register, the MI-
CROWIRE Busy status bit should be cleared
(MWSTAT.MBSY=0).
For normal operation, the CPU should first read the received
data, thus allowing pending received data to be transferred
from the shifter into the MWDAT register, before it writes the
next transmit data into the MWDAT address, which loads the
shifter directly. (MWSTAT.MBSY=0 is an indicator that the
shifter is empty and ready to receive the next transmit data.)
Otherwise, a second received data byte pending in the shifter
may get overwritten by the transmit byte.
The MWDAT register contains unknown data following a re-
set operation.
15.5.2 MICROWIRE Control 1 Register (MWCTL1)
The MWCTL1 register is a byte-wide, read/write register that
controls the operating mode of the MICROWIRE interface
module. Upon reset, all non-reserved bits are cleared to 0.
The register format is shown below.
MMNS MICROWIRE Master/Slave Select. When
cleared to 0, the device operates as a slave.
When set to 1, the device operates as the mas-
ter.
MSKM MICROWIRE Clocking Mode. When cleared to
0, the device uses the normal clocking mode.
When set to 1, the device uses the alternate
clocking mode. In the normal mode, the output
data is clocked out on the falling edge of MSK
and the input data is sampled on the rising
edge of MSK. In the alternate mode, the output
data is clocked out on the rising edge of MSK
and the input data is sampled on the falling
edge of MSK.
MIDL MICROWIRE Idle. This bit sets the value of the
MSK output when the MICROWIRE interface is
idle: 0 for low or 1 for high. This bit should be
changed only when the MICROWIRE interface
module is disabled (MEN=0) or when no bus
transaction is in progress (MWSTAT.MBSY=0).
MEN MICROWIRE Enable. This bit enables (1) or
disables (0) the MICROWIRE interface mod-
ule. Clearing this bit disables the module,
clears the status bits in the MICROWIRE status
register (the MBSY, MRBF, and MOVR flags in
MWSTAT), and places the MICROWIRE inter-
face pins in the states described in Table17.
Figure 24.MWSPI Interrupts
Figure 25.MWDAT Register Structure
Interrupt
MWSPI
MOVR = 1
MRBF = 1
MBSY = 0
MEIW
MEIR
MEIO
SHIFTER
READ BUFFER
Write
Read
8
Data In Data Out
7 6 5 4 3 2 1 0
Reserved MEN MIDL MSKM MMNS
Table 17Pin Values with MICROWIRE Disabled
MSK Master: MnIDL Bit
Slave: input
MCS Input
MDIDO Master: input
Slave: TRI-STATE
MDODI Master: known Value
Slave: input
MRDY TRI-STATE
Obsolete
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15.5.3 MICROWIRE Control 2 Register (MWCTL2)
The MWCTL2 register is a byte-wide, read/write register that
controls the clock divider used to generate the MSK shift
clock from the system clock. The MICROWIRE interface
module generates the MSK clock only in master mode, so
this register is ignored in slave mode. Upon reset, all non-re-
served bits are cleared to 0. The register format is shown be-
low.
MCDV MICROWIRE Clock Divider Value. This 7-bit
field specifies the divide-by factor used for gen-
erating the MSK shift clock from the system
clock. The divide-by factor is 2*(MCDV+1).
This allows selection of a divide-by ratio from 2
to 256. This field is ignored in slave mode
(MWCTL1.MMNS=0) or if the MDV1 bit is set.
MDV1 MICROWIRE Clock Divide-by-1. When cleared
to 0, the MSK shift clock rate is determined by
the MCDV field. When set to 1, the divide-by
factor is 1 and the MSK clock operates at the
same rate as the system clock. This bit is ig-
nored in slave mode (MWCTL1.MMNS=0).
15.5.4 MICROWIRE Control 3 Register (MWCTL3)
The MWCTL3 register is a byte-wide, read/write register that
controls the MRDY pin and enables or disables the MI-
CROWIRE interrupts and echo back function. Upon reset, all
non-reserved bits are cleared to 0. When the software writes
to this register, the reserved bits must be written with 0 for the
MICROWIRE interface to function properly. The register for-
mat is shown below.
MBFL MICROWIRE Buffer Length. This bit sets the
data buffer length in slave mode to either one
or two bytes.
When MBFL is cleared to 0, the buffer length is
one byte. The MRDY pin goes high when trans-
mission or reception of one data byte is com-
pleted. This is the proper setting for slave
mode.
When MBFL is set to 1, the buffer length is two
bytes. The MRDY pin goes high when the read
buffer is full and a subsequent transmission or
reception of a data byte is completed. This set-
ting is only intended for master mode and
should not be used for slave mode.
MRDY MICROWIRE Ready. This write-only bit allows
the software to control the MRDY pin when the
device operates in slave mode. Writing a 1 to
this bit position asserts the MRDY pin (makes
it go low). This should be done only when the
MICROWIRE interface is idle (MWSTAT.MB-
SY=0).
The hardware changes the MRDY pin from low
to high at the end of a data transfer, as defined
by the MBFL bit.
Writing a 0 to MRDY has no effect. The MRDY
bit is ignored entirely in master mode
(MWCTL1.MMNS=1).
Reading this bit returns an unknown value.
MECH MICROWIRE Echo Back. This bit enables (1)
or disables (0) the echo back function in slave
mode. This bit should be written only when the
MICROWIRE interface is idle (MWSTAT.MB-
SY=0). The MECH bit is ignored in master
mode.
In the echo back mode, MDODI is transmitted
(echoed back) on MDIDO if MWDAT does not
contain any valid data. With the echo back
function disabled, the data held in the MWDAT
register is transmitted on MDIDO, whether or
not the data is valid.
MEIO MICROWIRE Enable Interrupt on Overrun.
This bit enables or disables the overrun error
interrupt. When set to 1, an interrupt is gener-
ated when the Receive Overrun Error flag
(MWSTAT.MOVR) is set. Otherwise, no inter-
rupt is generated when an overrun error oc-
curs. This bit should only be enabled in master
mode.
MEIR MICROWIRE Enable Interrupt for Read. When
set to 1, an interrupt is generated when the
Read Buffer Full flag (MWSTAT.MRBF) is set.
Otherwise, no interrupt is generated when the
read buffer is full.
MEIW MICROWIRE Enable Interrupt for Write. When
set to 1, an interrupt is generated when the
Busy bit (MWSTAT.MBSY) is cleared, which in-
dicates that a data transfer sequence has been
completed and the read buffer is ready to re-
ceive the new data. Otherwise, no interrupt is
generated when the Busy bit is cleared.
15.5.5 MICROWIRE Status Register (MWSTAT)
The MICROWIRE Status Register is a byte-wide, read-only
register that shows the current status of the MICROWIRE in-
terface module. Upon reset, all non-reserved bits are cleared
to 0. The register format is shown below.
MBSY MICROWIRE Busy. This bit, when set to 1, in-
dicates that the MICROWIRE shifter is busy.
In master mode, MBSY is set to 1 when the
MWDAT register is written. In slave mode, this
bit is set to 1 on the first leading edge of MSK
when MCS is asserted or when the MWDAT
register is written, whatever occurs first.
In both master and slave modes, this bit is
cleared to 0 when the MICROWIRE data trans-
fer sequence is completed and the read buffer
is ready to receive the new data; in other
words, when the previous data held in the read
buffer has already been read.
If the previous data in the read buffer has not
been read and a new data has been received
into the shift register, the MBSY will not be
cleared, as the transfer could not be complet-
ed. This is because the contents of the shift
7 6543210
MDV1 MCDV
7 6 5 4 3 2 1 0
Reserved MEIW MEIR MEIO MECH MRDY MBFL
7 6 5 4 3 2 1 0
Reserved MOVR Reserved MRBF MBSY
Obsolete
61 www.national.com
register could not be copied into the read buff-
er.
MRBF MICROWIRE Read Buffer Full. This bit, when
set to 1, indicates that the MICROWIRE read
buffer is full and ready to be read by the soft-
ware. It is set to 1 when the shifter loads the
read buffer, which occurs upon completion of a
transfer sequence if the read buffer is empty.
The MRBF bit is updated when the MWDAT
register is read. At that time, the MRBF bit is
cleared to 0 if the shifter does not contain any
new data (in other words, the shifter is not re-
ceiving data or has not yet received a full byte
of data). The MRBF bit remains set to 1 if the
shifter already holds new data at the time that
MWDAT is read. In that case, MWDAT is imme-
diately reloaded with the new data and is ready
to be read by the software.
MOVR MICROWIRE Receive Overrun Error. This bit,
when set to 1 in master mode, indicates that a
receive overrun error has occurred. This error
occurs when the read buffer is full, the 8-bit
shifter is full, and a new data transfer sequence
starts. This bit is undefined in slave mode.
The MOVR bit, once set, remains set until
cleared by the software. The software clears
this bit by writing a 1 to its bit position. Writing
a 0 to this bit position has no effect. No other
bits in the MWSTAT register are affected by a
write operation to the register.
Obsolete
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16.0 USART
The USART module is a full-duplex Universal Synchronous/
Asynchronous Receiver/Transmitter that supports a wide
range of software-programmable baud rates and data for-
mats. It handles automatic parity generation and several er-
ror detection schemes. There are one or two independent
USART modules in each device, depending on the package
type.
Each USART module offers the following features:
—Full-duplex double-buffered receiver/transmitter
—Synchronous or asynchronous operation
—Programmable baud rate from SYS_CLK/
[2*(1+2^11)*16] up to SYSCLK/2 for USART config-
ured to run in synchronous mode
—Programmable baud rate from SYS_CLK/
[16*(1+2^11)*16] up to SYSCLK/16 for USART config-
ured to run in asynchronous mode
—Programmable framing formats: seven, eight, or nine
data bits; one or two stop bits; and odd, even, mark,
space, or no parity
—Hardware parity generation for data transmission and
parity check for data reception
—Interrupts on “transmit ready” and “receive ready” con-
ditions, separately enabled
—Software-controlled break transmission and detection
—Internal diagnostic capability
—Automatic detection of parity, framing, and overrun er-
rors
16.1 FUNCTIONAL OVERVIEW
Figure26 is a block diagram of the USART module showing
the basic functional units in the USART:
—Transmitter
—Receiver
—Baud Rate Generator
—Control and Error Detection
Note: In the description of the USART, the lower-case letter
“n” represents the USART number. For example, TDXn
means TDX1 or TDX2.
The Transmitter block consists of an 8-bit transmit shift reg-
ister and an 8-bit transmit buffer. Data bytes are loaded in
parallel from the buffer into the shift register and then shifted
out serially on the TDXn pin.
The Receiver block consists of an 8-bit receive shift register
and an 8-bit receive buffer. Data is received serially on the
RDXn pin and shifted into the shift register. Once eight bits
have been received, the contents of the shift register are
transferred in parallel to the receive buffer.
The Transmitter and Receiver blocks both contain exten-
sions for 9-bit data transfers, as required by the 9-bit and
loopback operating modes.
The Baud Rate Generator generates the clock for the syn-
chronous and asynchronous operating modes. It consists of
two registers and a two-stage counter. The registers are used
to specify a prescaler value and a baud rate divisor. The first
stage of the counter divides the USART clock based on the
value of the programmed prescaler to create a slower clock.
The second stage of the counter divides the output of the first
stage based on the programmed baud rate divisor to create
the baud rate clock.
The Control and Error Detection block contains the USART
control registers, control logic, error detection circuit, parity
generator/checker, and interrupt generation logic. The con-
trol registers and control logic determine the data format,
mode of operation, clock source, and type of parity used. The
error detection circuit generates parity bits and checks for
parity, framing, and overrun errors.
16.2 USART OPERATION
The USART has two basic modes of operation: synchronous
and asynchronous. In addition, there are two special-
purpose synchronous and asynchronous modes, called at-
tention and diagnostic. This section describes the operating
modes of the USART.
16.2.1 Asynchronous Mode
The asynchronous mode of the USART enables the device
to communicate with other devices using just two communi-
cation signals: transmit and receive.
In the asynchronous mode, the transmit shift register (TSFT)
and the transmit buffer (UnTBUF) double-buffer the data for
transmission. To transmit a character, a data byte is loaded
in the UnTBUF register. The data is then transferred to the
TSFT register. While the TSFT is shifting out the current char-
acter (LSB first) on the TDXn pin, the UnTBUF register is
loaded by software with the next byte to be transmitted.
When TSFT finishes transmission of the last stop bit of the
current frame, the contents of UnTBUF are transferred to the
TSFT register and the Transmit Buffer Empty flag (UnTBE) is
set. The UnTBE flag is automatically reset by the USART
when the software loads a new character into the UnTBUF
register. During transmission, the UnXMIP bit is set high by
the USART. This bit is reset only after the USART has sent
the last stop bit of the current character and the UnTBUF reg-
ister is empty. The UnTBUF register is a read/write register.
The TSFT register is not user accessible.
In asynchronous mode, the input frequency to the USART is
16 times the baud rate. In other words, there are 16 clock cy-
cles per bit time. In asynchronous mode the baud rate gen-
erator is always the USART clock source.
The receive shift register (RSFT) and the receive buffer (Un-
RBUF) double buffer the data being received. The USART
receiver continuously monitors the signal on the RDXn pin for
a low level to detect the beginning of a start bit. Upon sensing
this low level, the USART waits for seven input clock cycles
and samples again three times. If all three samples still indi-
cate a valid low, then the receiver considers this to be a valid
start bit, and the remaining bits in the character frame are
each sampled three times, around the mid-bit position. For
any bit following the start bit, the logic value is found by ma-
jority voting, i.e. the two samples with the same value define
the value of the data bit. Figure27 illustrates the process of
start bit detection and bit sampling.
Serial data input on the RDXn pin is shifted into the RSFT
register. Upon receiving the complete character, the contents
of the RSFT register are copied into the UnRBUF register
and the Receive Buffer Full flag (UnRBF) is set. The UnRBF
Obsolete
63 www.national.com
flag is automatically reset when software reads the character
from the UnRBUF register. The RSFT register is not user ac-
cessible.
16.2.2 Synchronous Mode
The synchronous mode of the USART enables the device to
communicate with other devices using three communication
signals: transmit, receive, and clock. In this mode, data bits
are transferred synchronously with the USART clock signal.
Data bits are transmitted on the rising edges and received on
the falling edges of the clock signal, as shown in Figure28.
Data bytes are transmitted and received least significant bit
(LSB) first.
In the synchronous mode, the transmit shift register (TSFT)
and the transmit buffer (UnTBUF) double-buffer the data for
transmission. To transmit a character, a data byte is loaded
in the UnTBUF register. The data is then transferred to the
TSFT register. The TSFT register shifts out one bit of the cur-
rent character, LSB first, on each rising edge of the clock.
While the TSFT is shifting out the current character on the
TDXn pin, the UnTBUF register may be loaded by the soft-
ware with the next byte to be transmitted. When the TSFT fin-
ishes transmission of the last stop bit within the current
frame, the contents of UnTBUF are transferred to the TSFT
Figure 26.USART Block Diagram
Internal Bus
Sys_clk Baud clock
Baud Clock
TDXn
RDXn
Transmitter
Receiver
Baud Rate Generator
Control and
Error Detection
Parity
Generator/Checker
CKXn
Figure 27.USART Asynchronous Communication
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 116
SampleSample
STARTBIT DATA (LSB)
12345678910 11 12 13 14 15 16 116
Sample
DATABIT
Obsolete
www.national.com 64
register and the Transmit Buffer Empty flag (UnTBE) is set.
The UnTBE flag is automatically reset by the USART when
the software loads a new character into the UnTBUF register.
During transmission, the UnXMIP bit is set high by the
USART. This bit is reset only after the USART has sent the
last frame bit of the current character and the UnTBUF regis-
ter is empty.
The receive shift register (RSFT) and the receive buffer
(UnRBUF) double-buffer the data being received. Serial data
received on the RDXn pin is shifted into the RSFT register at
the first falling edge of the clock. Each subsequent falling
edge of the clock causes an additional bit to be shifted into
the RSFT register. The USART assumes a complete charac-
ter has been received after the correct number of rising edg-
es on CKXn (based on the selected frame format) have been
detected. Upon receiving a complete character, the contents
of the RSFT register are copied into the UnRBUF register
and the Receive Buffer Full flag (UnRBF) is set. The UnRBF
flag is automatically reset when the software reads the char-
acter from the UnRBUF register.
The transmitter and receiver may be clocked from either an
external source provided to the CKXn pin or by the internal
baud rate generator. In the latter case, the clock signal is
placed on the CKXn pin as an output.
16.2.3 Attention Mode
The Attention mode is available for networking this device
with other processors. This mode requires the 9-bit data for-
mat with no parity. The number of start bits and number of
stop bits are programmable. In this mode, two types of 9-bit
characters are sent on the network: address characters con-
sisting of 8 address bits and a 1 in the ninth bit position and
data characters consisting of 8 data bits and a 0 in the ninth
bit position.
While in Attention mode, the USART receiver monitors the
communication flow but ignores all characters until an ad-
dress character is received. Upon the receipt of an address
character, the contents of the receive shift register are copied
to the receive buffer. The UnRBF flag is set and an interrupt
(if enabled) is generated. The UnATN bit is automatically re-
set to zero, and the USART begins receiving all subsequent
characters. The software must examine the contents of the
UnRBUF register and respond by accepting the subsequent
characters (by leaving the UnATN bit reset) or waiting for the
next address character (by setting the UnATN bit again).
The operation of the USART transmitter is not affected by the
selection of this mode. The value of the ninth bit to be trans-
mitted is programmed by setting or clearing a bit called
UnXB9 in the USART Frame Select Register. The value of
the ninth bit received is read from another register bit called
UnRB9 in the USART Status Register.
16.2.4 Diagnostic Mode
The Diagnostic mode is available for testing of the USART. In
this mode, the TDXn and RDXn pins are internally connected
together, and data that is shifted out of the transmit shift reg-
ister is immediately transferred to the receive shift register.
This mode supports only the 9-bit data format with no parity.
The number of start and stop bits is programmable.
16.2.5 Frame Format Selection
The format shown in Figure29 consists of a start bit, seven
data bits (excluding parity), and one or two stop bits. If parity
bit generation is enabled by setting the UnPEN bit, a parity
bit is generated and transmitted following the seven data bits.
The format shown in Figure30 consists of one start bit, eight
data bits (excluding parity), and one or two stop bits. If parity
bit generation is enabled by setting the UnPEN bit, a parity
bit is generated and transmitted following the eight data bits.
The format shown in Figure31 consists of one start bit, nine
data bits, and one or two stop bits. This format also supports
the USART attention feature. When operating in this format,
all eight bits of UnTBUF and UnRBUF are used for data. The
ninth data bit is transmitted and received using two bits in the
control registers, called UnXB9 and UnRB9. Parity is not
generated or verified in this mode.
16.2.6 Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from
the system clock. The system clock is passed through a two-
Figure 28.USART Synchronous Communication
CKX
TDX
RDX
Sample Input
Figure 29.Seven Data Bit Frame Options
Figure 30.Eight Data Bit Frame Options
1START
BIT 7 BIT DATA S
1a START
BIT 7 BIT DATA 2S
1c START
BIT 7 BIT DATA 2SPA
1b START
BIT 7 BIT DATA SPA
2
START
BIT 8 BIT DATA S
2a START
BIT 8 BIT DATA 2S
2b START
BIT 8 BIT DATA SPA
2c START
BIT 8 BIT DATA 2SPA
Obsolete
65 www.national.com
stage divider chain consisting of a 5-bit baud rate prescaler
(UnPSC) and an 11-bit baud rate divisor (UnDIV).
The relationship between the 5-bit prescaler select (UnPSC)
setting and the prescaler factors is shown in Table18.
A prescaler factor of zero corresponds to “no clock.” The “no
clock” condition is the USART power down mode, in which
the USART clock is turned off to reduce power consumption.
The application program should select the “no clock” condi-
tion before entering a new baud rate. Otherwise, it could
cause incorrect data to be received or transmitted. The
UnPSR register must contain a value other than zero when
an external clock is used at CKXn.
In asynchronous mode, the baud rate is calculated by:
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the USART is 16 times the baud
rate. In synchronous mode, the input clock to the USART is
equal to the baud rate.
16.2.7 Interrupts
The USART is capable of generating interrupts on:
•Receive Buffer Full
•Receive Error
•Transmit Buffer Empty
Figure32 shows a diagram of the interrupt sources and as-
sociated enable bits.
The interrupts can be individually enabled or disabled using
the Enable Transmit Interrupt (UnETI), Enable Receive Inter- rupt (UnERI) and Enable Receive Error Interrupt (UnEER)
bits in the UnICTRL register.
Figure 31.Nine Data Bit Frame Options
Table 18Prescaler Factors
Prescaler
Select Prescaler
Factor Prescaler
Select Prescaler
Factor
00000 110000 8.5
00001 110001 9
00010 1.5 10010 9.5
00011 210011 10
00100 2.5 10100 10.5
00101 310101 11
00110 3.5 10110 11.5
00111 410111 12
01000 4.5 11000 12.5
01001 511001 13
01010 5.5 11010 13.5
01011 611011 14
01100 6.5 11100 14.5
01101 711101 15
01110 7.5 11110 15.5
3
START
BIT 9 BIT DATA S
3a START
BIT 9 BIT DATA 2S 01111 811111 16
Table 18Prescaler Factors
Prescaler
Select Prescaler
Factor Prescaler
Select Prescaler
Factor
BR
SYS
_
CLK
16
NP
××
()
-------------------------------=
Figure 32.USART Interrupts
UnEEI
UnERI
UnERR
UnRBF
UnFE
UnDOE
UnPE
RX
Interrupt
UnETI
UnTBE TX
Interrupt
Obsolete
www.national.com 66
A transmit interrupt is generated when both the UnTBE and
UnETI bits are set. To remove this interrupt, software must ei-
ther disable the interrupt by clearing the UnETI bit or write to
the UnTBUF register (thus clearing the UnTBE bit).
A receive interrupt is generated on two conditions:
1. Both the UnRBF and UnERI bits are set. To remove this
interrupt, software must either disable the interrupt by
clearing the UnERI bit or read from the UnRBUF register
(thus clearing the UnRBF bit).
2. Both the UnERR and the UnEEI bits are set. To remove
this interrupt the software must either disable it by clear-
ing the UnEEI bit or read the UnSTAT register (thus
clearing the UnERR bit).
16.2.8 Break Generation and Detection
A line break is generated when the BRK bit is set in the Un-
MDSL register. The TDXn line remains low until the program
resets the BRK bit.
A line break is detected if RDXn remains low for 10 bit times
or longer after a missing stop bit is detected.
16.2.9 Parity Generation and Detection
Parity is only generated or checked with the 7-bit and 8-bit
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in the normal mode
with the 9-bit data format. Parity generation and checking are
enabled and disabled via the PEN bit in the UnFRS register.
The UnPSEL bits in the UnFRS register are used to select
odd, even, mark, or space parity.
16.3 USART REGISTERS
The software interacts with the USART by accessing the US-
ART registers. There are eight such registers:
•USART Receive Data Buffer (UnRBUF)
•USART Transmit Data Buffer (UnTBUF)
•USART Baud Rate Prescaler Register (UnPSR)
•USART Baud Rate Divisor Register (UnBAUD)
•USART Frame Select Register (UnFRS)
•USART Mode Select Register (UnMDSL)
•USART Status Register (UnSTAT)
•USART Interrupt Control Register (UnICTRL)
16.3.1 USART Receive Data Buffer (UnRBUF)
The USART Receive Data Buffer is a byte-wide, read/write
register used to receive each data byte.
16.3.2 USART Transmit Data Buffer (UnTBUF)
The USART Transmit Data Buffer is a byte-wide, read/write
register used to transmit each data byte.
16.3.3 USART Baud Rate Prescaler (UnPSR)
The USART Baud Rate Prescaler Register is a byte-wide,
read/write register that contains the 5-bit clock prescaler and
the upper three bits of the baud rate divisor. This register is
cleared upon reset. The register format is shown below.
UnPSC Prescaler. This 5-bit field specifies the prescal-
er value used for dividing the system clock in
the first stage of the two-stage divider chain.
For the prescaler factors corresponding to
each 5-bit value, see Table18.
UnDIV[10:8] Baud Rate Divisor (bits 10-8). This field con-
tains the three highest-order bits (bits 10, 9,
and 8) of the USART baud rate divisor used in
the second stage of the two-stage divider
chain. The remaining bits of the baud rate divi-
sor are contained in the UnBAUD register.
16.3.4 USART Baud Rate Divisor (UnBAUD)
The USART Baud Rate Divisor Register is a byte-wide, read/
write register that contains the lower eight bits of the baud
rate divisor. This register contents are unknown upon power-
up and are left unchanged by a reset operation. The register
format is shown below.
UnDIV[7:0] Baud Rate Divisor (bits 7-0). This field contains
the eight lowest-order bits of the USART baud
rate divisor used in the second stage of the
two-stage divider chain. The three highest-or-
der bits are contained in the UnPSR register.
The divisor value used is the 11-bit UnDIV val-
ue plus 1.
16.3.5 USART Frame Select Register (UnFRS)
The USART Frame Select Register is a byte-wide, read/write
register that controls the frame format, including the number
of data bits, number of stop bits, and parity type. This register
is cleared upon reset. The register format is shown below.
UnCHAR Character Frame Format. This 2-bit field se-
lects the number of data bits per frame, not in-
cluding the parity bit, as follows:
00 = eight data bits per frame
01 = seven data bits per frame
10 = nine data bits per frame
11 = loopback mode; nine data bits per frame
UnSTP Number of Stop Bits. This bit sets the number
of stop bits transmitted in each frame. If this bit
is 0, one stop bit is transmitted. If this bit is 1,
two stop bits are transmitted.
UnXB9 Transmit 9th Data Bit. This bit is the value of the
ninth data bit, either 0 or 1, transmitted when
the USART is configured to transmit nine data
bits per frame. It has no effect when the US-
ART is configured to transmit seven or eight
data bits per frame.
UnPSEL Parity Select. This 2-bit field selects parity type
as follows:
00 = odd parity
01 = even parity
10 = mark (0)
11 = space (1)
When the USART is configured to transmit nine
7 6 5 4 3 2 1 0
UnPSC UnDIV10 UnDIV9 UnDIV8
76543210
UnDIV7 UnDIV6 UnDIV5 UnDIV4 UnDIV3 UnDIV2 UnDIV1 UnDIV0
7 6 5 4 3 2 1 0
Reserved UnPEN UnPSEL UnXB9 UnSTP UnCHAR
Obsolete
67 www.national.com
data bits per frame, the parity bit is omitted and
the UnPSEL field is ignored.
UnPEN Parity Enable. This bit enables (1) or disables
(0) parity bit generation and parity checking.
When the USART is configured to transmit nine
data bits per frame, there is no parity bit and
the UnPEN bit is ignored.
16.3.6 USART Mode Select Register (UnMDSL)
The USART Mode Select Register is a byte-wide, read/write
register that selects the clock source, synchronization mode,
attention mode, and line break generation. This register is
cleared upon reset. When the software writes to this register,
the reserved bits must be cleared to 0 for proper operation.
The register format is shown below.
UnMOD Mode of Operation. Set to 0 for asynchronous
operation or 1 for synchronous operation.
UnATN Attention Mode. When set to 1, this bit selects
the attention mode of operation for the USART.
When cleared to 0, the attention mode is dis-
abled. The hardware clears this bit after an ad-
dress frame is received. An address frame is a
9-bit character with a 1 in the ninth bit position.
UnBRK Force Transmission Break. Setting this bit to 1
causes the TDXn pin to go low. TDXn remains
low until the UnBRK bit is cleared to 0 by the
software.
UnCKS Synchronous Clock Source. This bit controls
the clock source when the USART operates in
the synchronous mode (UnMOD=1). If the
UnCKS bit is set to 1, the USART operates
from an external clock provided on the CKXn
pin. If the UnCKS bit is cleared to 0, the USART
operates from the baud rate clock produced by
the USART on the CKXn pin. This bit is ignored
when the USART operates in the asynchro-
nous mode.
16.3.7 USART Status Register (UnSTAT)
The USART Status Register is a byte-wide, read-only regis-
ter that contains the receive and transmit status bits. This
register is cleared upon reset. Any attempt by the software to
write to this register is ignored. The register format is shown
below.
UnPE Parity Error. This bit is set to 1 when a parity er-
ror is detected within a received character. This
bit is automatically cleared to 0 by the hard-
ware when the UnSTAT register is read.
UnFE Framing Error. This bit is set to 1 when the US-
ART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared to 0
by the hardware when the UnSTAT register is
read.
UnDOE Data Overrun Error. This bit is set to 1 when a
new character is received and transferred to
the UnBUF register before the software has
read the previous character from UnBUF. This
bit is automatically cleared to 0 by the hard-
ware when the UnSTAT register is read.
UnERR Error Status Flag. This bit is set when a parity,
framing, or overrun error occurs (any time that
the UnPE, UnFE, or UnDOE bit is set). It is au-
tomatically cleared to 0 by the hardware when
the UnPE, UnFE, and UnDOE bits are all 0.
UnBKD Break Detect. This bit is set to 1 when a line
break condition occurs. This condition is de-
tected if RDXn remains low for at least ten bit
times after a missing stop bit has been detect-
ed at the end of a frame.
The hardware automatically clears the UnBKD
bit upon read of the UnSTAT register, but only
if the break condition on RXDn no longer ex-
ists. If reading the UnSTAT register does not
clear the UnBKD bit because the break is still
actively driven on the line, the hardware clears
the bit as soon as the break condition no longer
exists (when RXDn returns to a high level).
UnRB9 Received 9th Data Bit. With the USART config-
ured to operate in the 9-bit data format, this is
equal to the ninth data bit of the last frame re-
ceived.
UnXMIP Transmit In Progress. The hardware sets this
bit to 1 when the USART is transmitting data
and clears it to 0 at the end of the last frame bit.
16.3.8 USART Interrupt Control Register (UnICTRL)
The USART Interrupt Control Register is a byte-wide register
that contains the receive and transmit interrupt status flags
(read-only bits) and the interrupt enable bits (read/write bits).
The register is set to 01 hex upon reset. The register format
is shown below.
UnTBE Transmit Buffer Empty. This read-only bit is set
to 1 by the hardware when the USART trans-
fers data from the UnTBUF register to the
transmit shift register for transmission. It is au-
tomatically cleared to 0 by the hardware on the
next write to the UnTBUF register.
UnRBF Receive Buffer Full. This read-only bit is set by
the hardware when the USART has received a
complete data frame and has transferred the
data from the receive shift register to the UnR-
BUF register. It is automatically cleared to 0 by
the hardware when the UnRBUF register is
read.
UnETI Enable Transmitter Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnTBE bit.
UnERI Enable Receiver Interrupt. This read/write bit,
when set to 1, enables generation of an inter-
rupt when the hardware sets the UnRBF bit.
UnEEI Enable Receive Error Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnERR bit
in the UnSTAT register.
7 6 5 4 3 2 1 0
Reserved UnCKS UnBRK UnATN UnMOD
7 6 5 4 3 2 1 0
Reserved UnXMIP UnRB9 UnBKD UnERR UnDOE UnFE UnPE
7 6 5 4 3 2 1 0
UnEEI UnERI UnETI Reserved UnRBF UnTBE
Obsolete
www.national.com 68
16.4 BAUD RATE CALCULATIONS
The USART baud rate is determined by the system clock fre-
quency and the values programmed into the UnPSR and Un-
BAUD registers. Unless the system clock frequency is an
exact multiple of the desired baud rate, there will be a small
amount of error in the resulting baud rate clock.
The method of baud rate calculation depends on whether the
USART is configured to operate in the asynchronous or syn-
chronous mode.
16.4.1 Baud Rate in Asynchronous Mode
The equation for calculating the baud rate in asynchronous
mode is:
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Assuming a system clock of 5 MHz and a desired baud rate
of 9600, the NxP term according to the equation above is:
The NxP term is then divided by each Prescaler Factor from
Table18 to obtain a value closest to an integer. The factor for
this example is 6.5.
The baud rate register is programmed with a baud rate divi-
sor of 4 (N = baud rate divisor +1). This produces a baud
clock of:
Note that the percent error is much lower than would be pos-
sible without the non-integer prescaler factor. Refer to the ta-
ble below for more examples.
16.4.2 Baud Rate in Synchronous Mode
The equation for calculating the baud rate in synchronous
mode is:
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Use the same procedure to determine the values of N and P
as in the asynchronous mode. In this case, however, only in-
teger prescaler values are allowed.
System
Clock Desired
Baud Rate NPActual
Baud Rate Percent
Error
4 MHz 9600 2 13 9615.385 0.16
5 MHz 9600 56.5 9615.385 0.16
10 MHz 19200 56.5 19230.769 0.16
20 MHz 19200 5 13 19230.769 0.16
BR
SYS
_
CLK
16
NP
××
()
-------------------------------=
NP×5
6
×10()
169600×()
----------------------------- 32.552
==
N
32.552
6.5
---------------- 5.008 (N = 5)==
BR 5
6
×10()
1656.5××()
--------------------------------- 9615.385
==
%error
9615.3859600
–
()
9600
--------------------------------------------- 0.16
==
BR
SYS
_
CLK
2NP××
()
----------------------------=
Obsolete
69 www.national.com
17.0 Analog Comparators
The Dual Analog Comparator (ACMP2) module contains two
independent analog comparators with all necessary control
logic. Each comparator unit compares the analog input volt-
ages applied to two input pins and determines which voltage
is higher. The comparison results can be placed on two out-
put pins and/or read by the software from a register.
Figure33 is a block diagram of the Dual Analog Comparator
module.
The two comparators are designated Comparator 1 (CMP1)
and Comparator 2 (CMP2). Each comparator has a positive
and a negative input, called CMP1P and CMP1N for Com-
parator 1 and CMP2P and CMP2N for Comparator 2. An op-
tional output, CMP1O for Comparator 1 or CMP2O for
Comparator 2, allows the external hardware to read the com-
parison results. If the positive input is greater than the nega-
tive input, the result is a logic 1. Otherwise, the result is a
logic 0. These same results are available to the software by
reading the CMPCTRL register. CMP1OP and CMP2OP are
the direct outputs of the analog comparator. These signals
are connected to the channels of the Multi-Wake-Up Module.
17.1 ANALOG COMPARATOR CONTROL/
STATUS REGISTER (CMPCTRL)
The CMPCTRL register is a byte-wide, read/write register
that controls the comparator module and contains the com-
parison results. The control bits are read/write bits and the
result bits are read-only bits. This register is cleared upon re-
set. The register format is shown below.
CMP1RD Comparator 1 Read. This read-only bit con-
tains the output of Comparator 1 when the
comparator is enabled (CMP1EN=1).
CMP1RD is set to 1 when the voltage on
CMP1P is greater than the voltage on CMP1N.
This bit is always 0 when Comparator 1 is dis-
abled.
CMP2RD Comparator 2 Read. This read-only bit con-
tains the output of Comparator 2 when the
comparator is enabled (CMP2EN=1).
CMP2RD is set to 1 when the voltage on
CMP2P is greater than the voltage on CMP2N.
This bit is always 0 when Comparator 2 is dis-
abled.
CMP1EN Comparator 1 Enable. This read/write bit en-
ables (1) or disables (0) Comparator 1.
CMP2EN Comparator 2 Enable. This read/write bit en-
ables (1) or disables (0) Comparator 2.
CMP1OE Comparator 1 Output Enable. This read/write
bit, when set to 1, enables the use of the
CMP1O pin as the output of Comparator 1
when Comparator 1 is enabled (CMP1EN=1).
If Comparator 1 is disabled (CMP1EN=0), set-
ting the CMP1OE bit results in a logic 0 on the
CMP1O output pin.
CMP2OE Comparator 2 Output Enable. This read/write
bit, when set to 1, enables the use of the
CMP2O pin as the output of Comparator 2
when Comparator 2 is enabled (CMP2EN=1).
If Comparator 2 is disabled (CMP2EN=0), set-
ting the CMP2OE bit results in a logic 0 on the
CMP2O output pin.
17.2 ANALOG COMPARATOR USAGE
The comparator I/O pins are alternate functions of the Port L
pins. In order for a comparator to operate, its two input pins
must be configured to operate as inputs in the alternate func-
tion mode.
Using a comparator's output pin is optional. If it is to be used,
it must be configured to operate as an output in the alternate
function mode. The comparison result bits in the CMPCTRL
register are available to the CPU whether or not the output
pin is enabled.
The comparators uses DC current whenever they are en-
abled. Therefore, in order to reduce power consumption, it is
recommended that the comparators be disabled when they
are not needed, especially before entering any of the Power
Save modes.
7 6 5 4 3 2 1 0
Reserved CMP2OE CMP1OE CMP2EN CMP1EN CMP2RD CMP1RD
Obsolete
www.national.com 70
Figure 33.Dual Analog Comparator Block Diagram
+
_
CMP1
CMP1EN CMP1OE
+
_CMP2
CMP2EN CMP2OE
CONTROL + STATUS
CMP1P
CMP2P
CMP1N
CMP2N
CMP1O
CMP2O
Obsolete
71 www.national.com
18.0 A/D Converter
The A/D Converter (ADC) module is an 8-channel, multi-
plexed-input, analog-to-digital converter. The A/D Converter
receives an analog voltage on an input pin and converts that
voltage into an 8-bit digital value using successive approxi-
mation. The CPU can then read the result from a memory-
mapped register. The module supports four automated oper-
ating modes, providing single-channel or 4-channel scanned
operation in single-conversion or continuous mode.
Figure34 is a block diagram of the A/D Converter module.
The analog input signal is selected from eight analog inputs
using an 8-channel analog multiplexer. The input pins are al-
ternate functions of Port I.
A sample-and-hold circuit samples the analog voltage prior
to conversion and holds it stable and throughout the conver-
sion process. A programmable initial delay period allows the
sampled voltage to stabilize before the conversion process
begins.
A capacitor should be connected between the VREF and the
AVCC pin in order to minimize noise. The recommended val-
ue for this capacitor is about 0.47 µF
The input voltage range is from 0V to VREF (the A/D refer-
ence voltage). The 80-pin device have a separate pin, VREF,
for the reference voltage. The 44-pin devices use the AVCC
(analog VCC) power supply pin as the reference voltage.
The internal analog-to-digital converter block is based on a
successive approximation algorithm, which compares the
sampled voltage against an internally generated sequence of
analog voltages. The result is a linear conversion of the ana-
log voltage to an unsigned 8-bit value ranging from 00 hex for
0.0 volts to FF hex for VREF.
The clock used by the converter block is generated by a clock
divider that scales down the system clock by a programma-
ble factor. The conversion algorithm requires ten A/D Con-
verter clock cycles, or 10 microseconds at the maximum
allowed A/D Converter clock rate of 1 MHz.
Conversion can start after the power supply is stable and AD-
CEN set for 100 µs.
The conversion results are stored in a 4-level data buffer. De-
pending on the operating mode, the buffer can hold the re-
sults of four successive conversions from a single channel or
four conversions from adjacent channels scanned in se-
quence.
18.1 OPERATING MODES
The A/D Converter can be configured to operate in any one
of four modes:
•Single channel, single conversion
•Single channel, continuous conversion
•4-channel scan, single conversion
•4-channel scan, continuous conversion
The configuration is set by the SCAN and CONT fields in the
ADC Control 2 Register (ADCCNT2), as indicated in
Table19. The A/D converter must be disabled when switch-
ing to a different mode.
18.1.1 Single Channel, Single Conversion Mode
In the single channel, single conversion mode, the A/D Con-
verter performs a single conversion using a specified chan-
nel.
The software starts a conversion by setting the START bit in
the ADCCNT2 register. Upon completion of the conversion,
the A/D Converter places the result in register ADDATA0,
clears the START bit, and sets the EOC (end of conversion)
bit in the ADCST register. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
Table 19ADC Operation Modes
SCAN CONT Mode
00 0 Single Channel, Single Conversion
00 1 Single Channel, Continuous Conversion
01 0 4 Channels Scan, Single Conversion
01 1 4 Channel Scan, Continuous Conversion
Figure 34.A/D Converter Block Diagram
SAMPLE
&
HOLD
CONFIGURATION
STATUS
&
CONTROL
DATA
BUFFER
CLOCK
DIVIDER
PERIPHERAL
BUS
CLK
CLK
VREF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ANALOG
TO
DIGITAL
CONVERTER /
/3
5
8:1
ANALOG
MUX
Obsolete
www.national.com 72
18.1.2 Single Channel, Continuous Conversion Mode
In the single channel, continuous conversion mode, the A/D
Converter performs conversions repeatedly using the same
specified channel.
The software starts a conversion sequence by setting the
START bit. The A/D Converter performs four A/D conver-
sions in sequence using the same channel, pausing only for
the programmable sampling delay time used in all conver-
sion operations. It loads the four results into the A/D data reg-
isters in sequence, starting with ADDATA0 and ending with
ADDATA3. After it loads all four registers, it sets the EOC
(end of conversion) bit. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
The START bit remains set until cleared by the software. If
the software does not clear the START bit, the A/D Converter
continues performing conversions using the same input
channel, storing the results in ADDATA0 following ADDATA3.
To prevent an overrun error, the software must read the re-
sults from the data registers before the A/D Converter writes
the next result into ADDATA0 following ADDATA3.
When the software clears the START bit, the A/D Converter
first completes the conversion currently in progress, then
stops and sets the EOC bit. A 2-bit buffer pointer in the
ADCST register points to the register containing the final re-
sult.
18.1.3 4-Channel Scan, Single Conversion Mode
In the 4-channel scan, single conversion mode, the A/D Con-
verter performs four conversions using four adjacent input
channels.
The software starts the conversion sequence by setting the
START bit. The A/D Converter performs four A/D conver-
sions in sequence using four adjacent channels, starting with
the specified channel and pausing only for the programmable
sampling delay time. It loads the four results into the A/D data
registers in sequence, starting with ADDATA0 and ending
with ADDATA3. After it loads all four registers, it clears the
START bit and sets the EOC (end of conversion) bit. If the A/
D Converter interrupt is enabled, an interrupt to the CPU is
generated at this time.
18.1.4 Channel Scan, Continuous Conversion Mode
In the 4-channel scan, continuous conversion mode, the A/D
Converter performs conversions repeatedly using four adja-
cent input channels.
The software starts conversion operations by setting the
START bit. The A/D Converter performs four A/D conver-
sions in sequence using four adjacent channels, starting with
the specified channel and pausing only for the programmable
sampling delay time. It loads the four results into the A/D data
registers in sequence, starting with ADDATA0 and ending
with ADDATA3. After it loads all four registers, it sets the EOC
(end of conversion) bit. If the A/D Converter interrupt is en-
abled, an interrupt to the CPU is generated at this time.
The START bit remains set until cleared by the software. If
the software does not clear the START bit, the A/D Converter
continues performing conversions, repeating the same se-
quence using the same four input channels and the same se-
quence of data registers. To prevent an overrun error, the
software must read the results from the data registers before
the A/D Converter writes the next result into ADDATA0.
When the software clears the START bit, the A/D Converter
first completes the 4-channel conversion sequence currently
in progress, then stops and sets the EOC bit.
18.2 A/D CONVERTER REGISTERS
The software controls the A/D Converter and reads the A/D
results by accessing the ADC registers. There are eight such
registers:
•ADC Status Register (ADCST)
•ADC Control 1 Register (ADCCNT1)
•ADC Control 2 Register (ADCCNT2)
•ADC Control 3 Register (ADCCNT3)
•ADC Data Registers (ADDATA0 through ADDATA3)
18.2.1 ADC Status Register (ADCST)
The ADCST register is a byte-wide register that indicates the
current status of the A/D Converter. One bit in this register,
the OVF flag bit, is cleared by writing a 1 to its bit position.
The other bits are read-only bits, so the values written to
them are ignored. Upon reset, the register is set to 30 hex.
The register format is shown below.
EOC End of Conversion. This read-only bit reports
the status of the most recent A/D Converter op-
eration. When cleared to 0, it indicates that the
conversion is not complete. When set to 1, it in-
dicates that the conversion is complete. The
hardware sets this bit when it places the con-
version results in the buffer and clears it when
any of the data registers are read.
BUSY ADC Busy. This read-only bit is set to 1 when
the A/D Converter is busy converting data and
is cleared to 0 when the A/D Converter is idle
or disabled.
OVF Overflow. The hardware sets this bit to 1 when
the A/D Converter finishes a conversion and at-
tempts to store the results in one of the data
registers (ADDATA0-ADDATA3) while the reg-
ister is full. When this happens, the A/D Con-
verter overwrites the data in the data register,
sets the OVF flag, and continues operating.
The OVF flag remains set until cleared by the
software. The software clears the flag by writ-
ing a 1 to it. Writing a 0 to this bit has no effect.
BUFPTR Buffer Pointer. This 2-bit, read-only field identi-
fies the data register that was most recently
written with new data:
00 = ADDATA0
01 = ADDATA1
10 = ADDATA2
11 = ADDATA3
This register is initialized to 11 when a new con-
version is started (when ADCCNT2.START is
changed from 0 to 1) and is automatically incre-
mented every time a result is written to buffers
ADDATA0-ADDATA3. The result is a four-entry
7 6 5 4 3 2 1 0
Reserved BUFPTR Reserved OVF BUSY EOC
Obsolete
73 www.national.com
cyclic FIFO buffer, with BUFPTR pointing to the
last entry written by the A/D Converter.
18.2.2 ADC Control 1 Register (ADCCNT1)
The ADCCNT1 register is a byte-wide, read/write register
used to enable the A/D Converter and its interrupts, and also
to control the reference voltage source. When writing to this
register, all reserved bits must be written with 0 for the A/D
Converter to function properly. Changing any bits other than
ADCEN (bit 0) is not allowed while the A/D Converter is ac-
tive (ADCST.BUSY or ADCCNT2.START set). Upon reset,
all non-reserved bits are cleared to 0. The register format is
shown below.
ADCEN A/D Converter Enable. Setting this bit enables
the A/D Converter and allows a conversion to
be started by setting the start bit
(ADCCNT2.START). Clearing the ADCEN bit
disables the A/D Converter, terminates any
conversion in progress, and clears the ADC
status flags (ADCST.EOC, ADCST.BUSY,
ADCST.OVF, and ADCCNT2.START).
INTE Interrupt Enable. This bit enables (1) or dis-
ables (0) A/D Converter interrupts. If enabled,
and interrupt occurs at the end of a conversion
sequence or when the ADC data buffer is full,
depending on the operating mode.
All reserved bits must be written with 0 for ADC to operate
properly.
18.2.3 ADC Control 2 Register (ADCCNT2)
The ADCCNT2 register is a byte-wide, read/write register
used to specify the A/D Converter operating mode and to
start conversion operations. All register fields other than the
START bit should be changed only while the A/D Converter
is inactive (START=0). Data written to the SCAN and CONT
fields is ignored if the START bit is already set. Upon reset,
the non-reserved bits of this register are cleared to 0. The
register format is shown below.
CHANNEL Channel Select. This 4-bit field selects one of
the eight analog input channels as follows:
0000 = ACH0
0001 = ACH1
0010 = ACH2
0011 = ACH3
0100 = ACH4
0101 = ACH5
0110 = ACH6
0111 = ACH7
1XXX = reserved
CONT Continuous Conversion. When cleared to 0,
the A/D Converter stops operating upon com-
pletion of the programmed conversion cycle (a
single conversion or a sequence of four con-
versions on four channels). When set to 1, the
A/D Converter operates continuously by re-
peating the programmed conversion cycle.
SCAN Scan Mode. This 2-bit field selects the single-
conversion mode or 4-channel scan mode as
follows:
00 = single-conversion mode
01 = 4-channel scan mode
1X = reserved
START Start Conversion. The software sets this bit to
1 to start a conversion or a 4-channel conver-
sion cycle. In the “continuous” mode, this bit re-
mains set until cleared by the software. In the
“single” (non-continuous) mode, the hardware
clears this bit upon completion of the pro-
grammed conversion cycle. The software
should not attempt to set this bit while the A/D
Converter is busy (ADCST.BUSY=1).
18.2.4 ADC Control 3 Register (ADCCNT3)
The ADCCNT3 register is a byte-wide, read/write register
used to specify the analog sampling time delay and the di-
vide-by factor for generating the ADC clock. This register
should be written only when the A/D Converter is disabled
(ADCCNT1.ADCEN=0). Upon reset, the non-reserved bits of
the ADCCNT3 register are cleared to 0. The register format
is shown below.
CDIV Clock Divide. This 3-bit field sets the divide-by
factor for generating the A/D Converter clock
from the system clock. The frequency of the A/
D Converter clock is equal to the system clock
divided by the programmed factor. The result-
ing A/D Converter clock frequency must be
less than or equal to 1 MHz. The divide-by fac-
tor is defined as follows:
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
100 = divide by 16
101 = divide by 32
110 = reserved
111 = reserved
DELAY Sampling Time Delay. This 3-bit field defines
the number of A/D Converter clock cycles of
delay from the time that the input channel is se-
lected until the analog voltage is sampled. The
programmed delay should be sufficient, depen-
dent on the source impedance, to allow the
sampled signal to reach its final level before the
conversion begins. The delay is defined as fol-
lows:
000 = 1 A/D Converter clock cycle
001 = 2 A/D Converter clock cycles
010 = 4 A/D Converter clock cycles
011 = 8 A/D Converter clock cycles
100 = 16 A/D Converter clock cycles
101 = 32 A/D Converter clock cycles
7 6 5 4 3 2 1 0
Reserved INTE Reserved ADCEN
7 6 5 4 3 2 1 0
START SCAN CONT CHANNEL
7 6 5 4 3 2 1 0
Reserved DELAY CDIV
Obsolete
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110 = 64 A/D Converter clock cycles
111 = reserved
18.2.5 ADC Data Registers (ADDATA0-ADDATA3)
The four ADC Data Registers (ADDATA0 through ADDATA3)
are byte-wide, read/write registers that hold the conversion
results, which are stored sequentially starting with ADDATA0
and ending with ADDATA3. The results held in these regis-
ters are valid only after the ADCST.EOC flag is set. Upon re-
set, the contents of these registers are undefined.
The value read from a data register is a linear mapping of the
analog input voltage to an 8-bit value. The value 00 hex rep-
resents 0.0 volts and the value FF hex represents the refer-
ence voltage, VREF.
18.3 A/D CONVERTER PROGRAMMING
The software should set the A/D Converter configuration be-
fore it enables the A/D Converter module. The configuration
consists of the following settings:
•ADC clock rate: ADCCNT3.CDIV
•Sampling delay: ADCCNT3.DELAY
•Interrupt enable (if required): ADCCNT1.INTE
The ADC clock is created by scaling down the system clock.
The fastest allowable clock for the A/D Converter is 1 MHz.
Therefore, for the fastest possible operation of the A/D Con-
verter, use the smallest available divide-by factor that results
in a clock frequency of 1 MHz or lower. The available divide-
by factors are 1, 2, 4, 8, 16, and 32.
For example, if the system clock is 10 MHz, use a divide-by
factor of 16. In that case, the A/D Converter clock frequency
is 625 kHz, the clock period is 1.6 microseconds, and the A/
D conversion time is 16 microseconds (ten clock A/D Con-
verter clock cycles).
The programmable sampling time delay should be made
small for faster operation, but large enough to allow the input
voltage to settle. The internal resistance and capacitance of
the A/D Converter, together with the source resistance of the
device that drives the A/D input determine the charge-up time
required for the voltage to settle. Figure35 shows a schemat-
ic of the charge-up circuit. For the values of RAIN and CAIN,
see Section21.0.
Interrupts or polling can be used to read the A/D Converter
results. For interrupts, the A/D Converter interrupt must be
enabled by setting the ADCCNT1.INTE bit. The interrupt is
cleared automatically when any one of the data registers
(ADDATA0-ADDATA3) is read. For polling, the software
reads the ADCST.EOC bit to determine whether the conver-
sion sequence is completed.
Once the A/D Converter configuration has been set up, the
software can use the following procedure to perform an A/D
conversion sequence:
1. Enable the A/D Converter by setting the ADCCNT1.AD-
CEN bit and wait 100 µs before performing any conver-
sion.
2. Select the operating mode and channel by writing to the
SCAN, CONT, and CHANNEL fields of the ADCCNT2
register. At the same time, start the conversion by setting
the START bit in the same register.
3. Wait until the conversion is finished, either by polling or
using the A/D Converter interrupt.
4. Read the conversion results from the data registers,
ADDATA0 through ADDATA3 (or just ADDATA0 in the
single-channel, single-conversion mode).
5. In the continuous conversion modes, repeat Step 3 and
Step 4 for as long as samples are needed. Then stop the
A/D Converter by clearing either the START bit
(ADCCNT2.START) or the A/D Converter enable bit
(ADCCNT1.ADCEN).
To minimize power consumption, the A/D Converter should
be disabled when it is not needed, especially before entering
a Power Save mode.
Figure 35.Sample-and-Hold Charge-Up Schematic
A/D Converter
Analog
Multiplexer Sample &
Hold
RAIN
CAIN
Input
signal
RSOURCE
Obsolete
75 www.national.com
19.0 Memory Map
Please refer to individual datasheets for its own set of mem-
ory maps. The CompactRISC architecture supports a uni-
form linear address space of 2 megabytes. The device
implementation of this architecture uses only the lowest 64
kbytes of address space, ranging from 0000 to FFFF hex.
Table20 is a memory map showing the types of memory and
peripherals that occupy this memory space. Address ranges
not listed in the table are reserved and should not be read or
written.
Table21 is a detailed memory map showing the specific
memory address of the memory, I/O ports, and registers. The
table shows the starting address, the size, and a brief de-
scription of each memory block and register. For detailed in-
formation on using these memory locations, see the
applicable sections in the data sheet.
All addresses not listed in the table are reserved and should
not be read or written. An attempt to access an unlisted ad-
dress will have unpredictable results.
Each byte-wide register occupies a single address and can
be accessed only in a byte-wide transaction. Each word-wide
register occupies two consecutive memory addresses and
can be accessed only in a word-wide transaction. Both the
byte-wide and word-wide registers reside at word boundaries
(even address). Thus, each byte-wide register uses only the
lowest eight bits of the internal data bus.
Most device registers are read/write registers. However,
some registers are read-only or write-only, as indicated in the
table. An attempt to read a write-only register or to write a
read-only register will have unpredictable results.
When the software writes to a register in which one or more
bits are reserved, it must write a zero to each reserved bit un-
less indicated otherwise in the description of the register.
Reading a reserved bit returns an undefined value.
Table 20Device Memory Map
Address
Range (hex) Description
0000-BFFF Flash Program Memory (48 kbytes)
DA00-DFF7 ISP Memory (1.5 kbytes)
DFF8-DFFF Program ROM control/status
E000-E7FF Static RAM (2 kbytes)
F000-F27F EEPROM Data Memory (640 bytes)
F900-F930 Device configuration registers
FB00-FB06 Port B registers
FB10-FB16 Port C registers
FC40-FC88 Clock, Power Management, and Wake-up
registers
FCA0-FCA8 Port G registers
FD20-FD28 Port F registers
FE00-FE0C Interrupt registers
FE40-FE4E USART 1 registers
FE60-FE68 MICROWIRE registers
FE80-FE8E USART 2 registers
FEE0-FEE8 Port I registers
FF00-FF08 Port L registers
FF20-FF2A Timer and WATCHDOG registers
FF40-FF50 MFT1 Timer registers
FF60-FF70 MFT2 Timer registers
FFC0-FFD0 A/D Converter registersa
FFE0-FFE0 Analog Comparator registera
a. 44 pin devices may not include this module
Obsolete
www.national.com 76
Table 21Device Detailed Memory Map
Register Name Size Register
Address
(hex)
Access
Type Contents
48K 0000 Read/Write Flash Program Memory
FLCTRL byte DFFE Read/Write Flash Program Memory Control Register (EMPTY bit)
FLSEC byte DFFF Read/Write Flash Program Memory Security Register
2K E000 Read/Write Static RAM
640 F000 Read/Write EEPROM Data Memory
BCFG byte F900 Read/Write BIU Configuration Register
SZCFG0 word F904 Read/Write Static Zone 0 Configuration Register
MCFG byte F910 Read/Write Module Configuration Register
MSTAT byte F914 Read Only Module Status Register
DMCSR byte F940 Read/Write EEPROM Data Memory Control and Status Register
DMPSLR byte F942 Read/Write EEPROM Data Memory Prescaler Register
DMKEY byte F954 Read/Write EEPROM Data Memory Write Key Register
FLCSR byte F960 Read/Write Flash Program Memory Control and Status Register
FLPSLR byte F962 Read/Write Flash Program Memory Prescaler Register
PGMKEY byte F974 Read/Write Flash Program Memory Write Key Register
PBDIR byte FB00 Read/Write Port B Direction Register
PBDIN byte FB02 Read Only Port B Data Input Register
PBDOUT byte FB04 Read/Write Port B Data Output Register
PBWKPU byte FB06 Read/Write Port B Weak Pull-Up Register
PCDIR byte FB10 Read/Write Port C Direction Register
PCDIN byte FB12 Read/Write Port C Data Input Register (read-only)
PCDOUT byte FB14 Read/Write Port C Data Output Register
PCWKPU byte FB16 Read/Write Port C Weak Pull-Up Register
CRCTRL byte FC40 Read/Write Clock and Reset Control Register
PRSSC byte FC42 Read/Write Slow Clock Prescaler Register
PMCSR byte FC60 Read/Write Power Management Control/Status Register
WKEDG byte FC80 Read/Write Wake-Up Edge Detection Register
WKENA byte FC82 Read/Write Wake-Up Enable Register
WKCTRL byte FC84 Read/Write Wake-Up Source Select Register
WKPND byte FC86 Read Set Wake-Up Pending Register
WKPCL byte FC88 Write Only Wake-Up Pending Clear Register
PGALT byte FCA0 Read/Write Port G Alternate Function Register
PGDIR byte FCA2 Read/Write Port G Direction Register
PGDIN byte FCA4 Read Only Port G Data Input Register
PGDOUT byte FCA6 Read/Write Port G Data Output Register
PGWKPU byte FCA8 Read/Write Port G Weak Pull-Up Register
PGSCHEN byte FCAA Read/Write Port G Schmitt Trigger Enable Register
PFALT byte FD20 Read/Write Port F Alternate Function Register
PFDIR byte FD22 Read/Write Port F Direction Register
PFDIN byte FD24 Read Only Port F Data Input Register
PFDOUT byte FD26 Read/Write Port F Data Output Register
Obsolete
77 www.national.com
PFWKPU byte FD28 Read/Write Port F Weak Pull-Up Register
PFSCHEN byte FD2A Read/Write Port F Schmitt Trigger Enable Register
IVCT byte FE00 Read Only Interrupt Vector Register
NMISTAT byte FE02 Read Only NMI Status Register
EXNMI byte FE04 Read/Write External NMI Control/Status Register
ISTAT0 byte FE0A Read Only Interrupt Status Register 0
ISTAT1 byte FE0C Read Only Interrupt Status Register 1
IENAM byte FE0E Read/Write Interrupt and Enable Mask Register 0
IENAM1 byte FE10 Read/Write Interrupt and Enable Mask Register 1
U1TBUF byte FE40 Read/Write USART 1 Transmit Data Buffer
U1RBUF byte FE42 Read Only USART 1 Receive Data Buffer
U1ICTRL byte FE44 Read/Write USART 1 Interrupt Control Register
U1STAT byte FE46 Read Only USART 1 Status Register
U1FRS byte FE48 Read/Write USART 1 Frame Select Register
U1MDSL byte FE4A Read/Write USART 1 Mode Select Register
U1BAUD byte FE4C Read/Write USART 1 Baud Rate Divisor Register
U1PSR byte FE4E Read/Write USART 1 Baud Rate Prescaler
MWDAT byte FE60 Read/Write MICROWIRE Data Register
MWCTL1 byte FE62 Read/Write MICROWIRE Control 1 Register
MWCTL2 byte FE64 Read/Write MICROWIRE Control 2 Register
MWCTL3 byte FE66 Read/Write MICROWIRE Control 3 Register
MWSTAT byte FE68 Read Only MICROWIRE Status Register
U2TBUF byte FE80 Read/Write USART 2 Transmit Data Buffer
U2RBUF byte FE82 Read Only USART 2 Receive Data Buffer
U2ICTRL byte FE84 Read/Write USART 2 Interrupt Control Register
U2STAT byte FE86 Read Only USART 2 Status Register
U2FRS byte FE88 Read/Write USART 2 Frame Select Register
U2MDSL byte FE8A Read/Write USART 2 Mode Select Register
U2BAUD byte FE8C Read/Write USART 2 Baud Rate Divisor Register
U2PSR byte FE8E Read/Write USART 2 Baud Rate Prescaler
PIALT byte FEE0 Read/Write Port I Alternate Function Register
PIDIR byte FEE2 Read/Write Port I Direction Register
PIDIN byte FEE4 Read Only Port I Data Input Register
PIDOUT byte FEE6 Read/Write Port I Data Output Register
PIWKPU byte FEE8 Read/Write Port I Weak Pull-Up Register
PISCHEN byte FEEA Read/Write Port I Schmitt Trigger Enable Register
PLALT byte FF00 Read/Write Port L Alternate Function Register
PLDIR byte FF02 Read/Write Port L Direction Register
PLDIN byte FF04 Read Only Port L Data Input Register (read-only)
PLDOUT byte FF06 Read/Write Port L Data Output Register
PLWKPU byte FF08 Read/Write Port L Weak Pull-Up Register
PLSCHEN byte FF0A Read/Write Port L Schmitt Trigger Enable Register
Table 21Device Detailed Memory Map
Register Name Size Register
Address
(hex)
Access
Type Contents
Obsolete
www.national.com 78
TWCFG byte FF20 Read/Write Timer and WATCHDOG Configuration Register
TWCP byte FF22 Read/Write Timer and WATCHDOG Clock Prescaler Register
TWMT0 word FF24 Read/Write TWM Timer 0 Register
T0CSR byte FF26 Read/Write TWMT0 Control and Status Register
WDCNT byte FF28 Write Only WATCHDOG Count Register
WDSDM byte FF2A Write Only WATCHDOG Service Data Match Register
T1CNT1 word FF40 Read/Write T1 Timer/Counter I Register
T1CRA word FF42 Read/Write T1 Reload/Capture A Register
T1CRB word FF44 Read/Write T1 Reload/Capture B Register
T1CNT2 word FF46 Read/Write T1 Timer/Counter II Register
T1PRSC byte FF48 Read/Write T1 Clock Prescaler Register
T1CKC byte FF4A Read/Write T1 Clock Unit Control Register
T1CTRL byte FF4C Read/Write T1 Timer Mode Control Register
T1ICTL byte FF4E Read/Write T1 Timer Interrupt Control Register
T1ICLR byte FF50 Read/Write T1 Timer Interrupt Clear Register
T2CNT2 word FF60 Read/Write T2 Timer/Counter I Register
T2CRA word FF62 Read/Write T2 Reload/Capture A Register
T2CRB word FF64 Read/Write T2 Reload/Capture B Register
T2CNT2 word FF66 Read/Write T2 Timer/Counter II Register
T2PRSC byte FF68 Read/Write T2 Clock Prescaler Register
T2CKC byte FF6A Read/Write T2 Clock Unit Control Register
T2CTRL byte FF6C Read/Write T2 Timer Mode Control Register
T2ICTL byte FF6E Read/Write T2 Timer Interrupt Control Register
T2ICLR byte FF70 Read/Write T2 Timer Interrupt Clear Register
ADCST byte FFC0 Read/Write A/D Converter Status Register
ADCCNT1 byte FFC2 Read/Write A/D Converter Control 1 Register
ADCCNT2 byte FFC4 Read/Write A/D Converter Control 2 Register
ADCCNT3 byte FFC6 Read/Write A/D Converter Control 3 Register
ADDATA0 byte FFCA Read/Write A/D Converter Data 0 Register
ADDATA1 byte FFCC Read Only A/D Converter Data 1 Register
ADDATA2 byte FFCE Read Only A/D Converter Data 2 Register
ADDATA3 byte FFD0 Read Only A/D Converter Data 3 Register
CMPCTRL byte FFE0 Read/Write Analog Comparator Control/Status Register
Table 21Device Detailed Memory Map
Register Name Size Register
Address
(hex)
Access
Type Contents
Obsolete
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20.0 Register Layouts
The following tables show the functions of the bit fields of the device registers. For more information on using these registers,
see the detailed description of the applicable function elsewhere in the data sheet.
20.1 REGISTER LAYOUT
System
Configuration
Registers 7 6 5 4 3 2 1 0
MCFG Reserved CLK2OE SLCOE2 FEEDM SLCLKOE CLKOE Reserved
MSTAT Reserved PGMBUSY OENV2 OENV1 OENV0
BIU Registers 15 12 11 10 9 8 7 6 5 4 3 2 1 0
BCFG Reserved EWR
IOCFG Reserved 1IPST Res BW Reserved HOLD WAIT
SZCFG0 Reserved FRE IPRE IPST Res BW Reserved HOLD WAIT
EEPROM Data
Memory Registers 76543210
DMCSR Reserved DMBUSY ERASE Reserved
DMPSLRFTDIV
DMKEY DMKEYVAL
Flash Program
Memory Registers 76543210
FLCSR Reserved IENPROG PMLFULL PMBUSY ERASE Reserved
FLCSR FTDIV
PGMKEY PMKEYVAL
FLSEC Reserved FROMWR ERASE FROMRD
GPIO Registers 7 6 5 4 3 2 1 0
PxALT Px Pins Alternate Function Enable
PxDIR Px Port Direction
PxDIN Px Port Output Data
PxDOUT Px Port Input Data
PxWPU Px Port Weak Pull-up Enable
PxSCHEN Px Port Schmitt Trigger Enable
Obsolete
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ICU Registers 76543210
IVCT 0 0 0 1 INTVECT
NMISTAT Reserved EXT
NMIMNTR Reserved WD ERR UND EXT
ISTAT0 IST(7:0)
ISTAT1 IST(15:8)
IENAM0 IENA(7:0)
IENAM1 IENA(15:8)
EXNMI Reserved ENCLK PIN EN
MIWU Registers 7 6 5 4 3 2 1 0
WKEDG WKED7 WKED6 WKED5 WKED4 WKED3 WKED2 WKED1 WKED0
WKENA WKEN7 WKEN6 WKEN5 WKEN4 WKEN3 WKEN2 WKEN1 WKEN0
WKCTRL Reserved WKSEL0
WKPND WKPD7 WKPD6 WKPD5 WKPD4 WKPD3 WKPD2 WKPD1 WKPD0
WKPCL WKCL7 WKCL6 WKCL5 WKCL4 WKCL3 WKCL2 WKCL1 WKCL0
Dual Clock + Reset Registers 7 6 5 4 3 2 1 0
CRCTRLReserved POR SCLK
PRSSC SCDIV
Power Management Register 7 6 5 4 3 2 1 0
PMCSR OLFC OHFC WBPSM Reserved HALT IDLE DHF PSM
USART Registers 7 6 5 4 3 2 1 0
UnTBUF UnTBUF
UnRBUF UnRBUF
UnICTRL UnEEI UnERI UnETI Reserved UnRBF UnTBE
UnSTAT Reserved UnXMIP UnRB9 UnBKD UnERR UnDOE UnFE UnPE
UnFRS Reserved UnPEN UnPSEL UnXB9 UnSTP UnCHAR
UnMDSL Reserved UnCKS UnBRK UnATN UnMOD
UnBAUD UnDIV[7]: UnDIV[0]
UnPSR UnPSC UnDIV[10]: UnDIV[8]
Obsolete
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MWSPI Registers 76543210
MWDAT MWnDAT
MWCTL1 Reserved MEN MIDL MCKM MMNS
MWCTL2 MDV1 MCDV
MWCTL3 Reserved MEIW MEIR MEIO MECH MRDY MBFL
MWSTAT Reserved MOVR Reserved MRBF MBSY
TIMER Registers 15 8 76543210
TnCNT1 TnCNT1
TnCRA TnCRA
TnCRB TnCRB
TnCNT2 TnCNT2
TnPRSC Reserved CLKPS
TnCKC Reserved C2CSEL C1CSEL
TnCTRL Reserved TnAOUT TnBEN TnAEN TnBEDG TnAEDG MDSEL
TnICTL TnDIEN TnCIEN TnBIEN TnAIEN TnDPND TnCPND TnBPND TnAPND
TnICLR Reserved TnDCLR TnCCLR TnBCLR TnACLR
TWM Registers 15 8 7 6 5 4 3 2 1 0
TWCFG Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
TWCP Reserved MDIV
TWMTO PRESET
T0CSR Reserved T0INTE TC RST
WDCNT PRESET
WDSDM RSTDATA
A/D Registers 7 6 5 4 3 2 1 0
ADCST Reserved BUFPTR Reserved OVF BUSY EOC
ADCCNT1 Reserved INTE Reserved ADCEN
ADCCNT2 START SCAN CONT CHANNEL
ADCCNT3 Reserved DELAY CDIV
ADDATA0 RESULT 1 DATA
ADDATA1 RESULT 2 DATA
ADDATA2 RESULT 3 DATA
ADDATA3 RESULT 4 DATA
Obsolete
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Analog Comp. Registers 7 6 543210
CMPCTRL Reserved CMP2OE CMP1OE CMP2EN CMP1EN CMP2RD CMP1RD
Obsolete
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21.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device at
absolute maximum ratings.
Thermal Characteristics
DC Electrical Characteristics: –40°C ≤ TA ≤ +85°C (also supports -40°C to 125°C) depends on package type
Supply Voltage (VCC) 7V
Voltage at Any Pin –0.6V to VCC +0.6V
ESD Protection Level 6 kV
(Human Body Model)
Total Current into VCC Pin (Source) 80 mA
Total Current out of GND Pin (Sink) 100 mA
Storage Temperature Range –65°C to +140°C
Characteristics Symbol Value Unit
Average junction temperature TJTA + (PD X ~JA)°C
Ambient temperature TAUser-determined °C
Package thermal resistance (junction-to-ambient)
80-pin quad flat pack (QFP)
44-pin package (PLCC) ~JA 49.8
56 °C/W
Total power dissipation1
PD
PINT + PI/O
or
K
TJ + 273°C
W
Device internal power
dissipation PINT IDD X VDD W
I/O pin power dissipation2PI/O User-determined W
A constant3KPD x (TA + 273°C) +
~ JA x PD2W, °C
1. This is an approximate value, neglecting PI/O.
2. For most applications PI/O << PINT and can be neglected.
3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of K to solve for
PD and TJ iterntively for any value of TA.
Symbol Parameter Conditions Min Max Units
Operating Voltage 4.5 5.5 V
VIH Logical 1 CMOS Hysteresis Input Voltage 0.8Vcc Vcc + 0.5 V
VIL Logical 0 CMOS Input Voltage -0.5 0.2Vcc V
Vxl Low Level Input Voltage OSC External X1 clock 0 Vcc 0.2Vcc V
Vxh High Level Input Voltage OSC External X1 clock 0.5Vcc Vcc V
Vxl2 X2CKI Logical 0 Input Voltage External X2 clock 0.3 V
Vxh2 X2CKI Logical 1 Input Voltage External X2clock 1.2 V
Vhys Hysteresis Loop Width a b0.1Vcc V
IOH Logical 1 CMOS Output Current VOH = 3.8V, Vcc=4.5V -1.6 mA
IOL Other Pins
Logical 0 CMOS Output Current VOL = 0.45V, Vcc=4.5V 1.6 mA
IOHW Weak Pull-up Current VOH = 3.8V, Vcc=4.5V -10 µA
ILInput Leakage Current 0V ≤ Vin ≤ Vcc - 2.0 2.0jµA
IO(Off) Output Leakage Current (I/O pins in input mode) 0V ≤ Vout ≤ Vcc - 2.0 2.0jµA
Obsolete
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A/D Converter Characteristics
Icca1 Digital Supply Current Active Mode, normal cTC = 20 MHz, Vcc= 5.5V 38 mA
Iccprog Digital Supply Current Active Mode, flash mem.dTC = 20 MHz, Vcc = 5.5V 46 mA
Icca2 Digital Supply Current Active Mode, WAIT eTC = 20 MHz, Vcc = 5.5V 23.2 mA
Icca1 Digital Supply Current Active Mode, normal cTC = 8 MHz, Vcc= 5.5V 38 mA
Iccprog Digital Supply Current Active Mode, flash mem.dTC = 8 MHz, Vcc = 5.5V 46 mA
Icca2 Digital Supply Current Active Mode, WAIT eTC = 8 MHz, Vcc = 5.5V 23.2 mA
Iccps Digital Supply Current Power Save Mode fVcc= 5.5V 9mA
Iccid Digital Supply Current Idle Mode gVcc = 5.5V 60 µA
Iccq Digital Supply Current Halt Mode hVcc = 5.5V 15kµA
Iacc Analog Supply Current Active Mode iVcc = 5.5V 3mA
a. Guaranteed by design.
b. Hysteresis applies only when the Schmitt trigger is enabled or when alternate function is selected.
c. Running from internal memory, Iout = 0 mA, XCKI1 = 20 and 8 MHz, not programming flash memory.
d. Same conditions as c. (Icca1), but while programming or erasing one of the flash memory arrays.
e. CPU executing an WAIT instruction, Iout = 0 mA, XCKI1 = 20 and 8 MHz, peripherals not active.
f. Running from internal memory, Iout = 0mA, Iout = 0mA, XCKI1 = 20 MHz, XCKI2 = 32.768 kHz.
g. Iout = 0mA, XCKI1 = Vcc, X2CKI = 32.768 kHz
h. Same conditions as g. (Iccps), but in Halt mode instead of Idle mode
i. A/D converter and analog comparators enabled.
j. IL and IO are 2.0 µA at 85°C and 5.0 µA at 125°C
k. Iacq is 20 µA at 85°C and 50 µA at 125°Ci.
i.
Symbol Parameter Conditionsa
a. All parameters specified for fOSC = 1 MHz,
VDD = 5.0V ± 10%, VDD = 5.0V ± 10% unless otherwise noted.
Min Typ Max Units
NIL Integral Errorb
b. Integral (non-linearity) error; the maximum difference between the best-fit straight line reference and the actual
conversion curve.
VREF = VCC 1LSB
NDL Differential Errorc
c. Differential (non-linearity) error; the maximum difference between the best-fit stair-step reference with 1-LSB
resolution and the actual conversion curve.
VREF = VCC 1LSB
VIN Input Voltage Range VREF < VCC - 0.1 0VREF V
VREFEX External Reference Voltage 3.0 VDD V
VREFI Internal Reference Voltage 2.375 2.5 2.625 V
IVREF VREF input current VREF = 5 V 1.0 mA
IAL Analog input leakage current VREF = VCC ±1µA
RAIN Analog input resistanced
d. The resistance between the device input and the internal analog input capacitance.
200 Ω
CAIN Analog input capacitancee
e. The input signal is measured across the internal capacitance.
5pF
tADCCLK Conversion Clock period 1µs
CREFEX External Vref bypass capacitance 0.47 µF
tACT First A/D conversion after Vcc stable 100 µsec
Symbol Parameter Conditions Min Max Units
Obsolete
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Comparator AC and DC Characteristics
Flash EEPROM Program Memory Programming
Symbol Parameter Conditions Min Typ Max Units
VOS Input Offset Voltage Vcc = 5V,
0.4V ≤ VIN ≤ VCC – 1.5V ±25 mV
VCM Input Common Mode Voltage Range 0.4 VCC -1.5 V
ICS DC Supply Current per Comparator (When
Enabled) VCC=5.5V 250 µA
Response Time 1V Step / 100mV Overdrive 1µs
Symbol Parameter Conditions Min Max Units
tPWP Programming pulse width a
a. The programming pulse width is determined by the following equation:
tPWP
= Tclk x (FTDIV+1) x (FTPROG+1), where Tclk is the system clock period, FTDIV is the contents of the
FLPSLR register and FTPROG is the contents of the FLPROG register.
30 40 µs
tEWP Erase pulse widthb
b. The erase pulse width is determined by the following equation:
tEWP
= Tclk x (FTDIV+1) x 4 x (FTER+1), where Tclk is the system clock period, FTDIV is the contents of the
FLPSLR register and FTER is the contents of the FLERASE register.
1-ms
tSDP Charge pump power-up delayc
c. The program/erase start delay time is determined by the following equation:
tSDP = Tclk x (FTDIV+1) x (FTSTART+1), where Tclk is the system clock period, FTDIV is the contents of the
FLPSLR register and FTSTART is the contents of the FLSTART register.
10 -µs
tTTP Program/erase transition timed
d. The program/erase transition time is determined by the following equation:
tTTP = Tclk x (FTDIV+1) x (FTTRAN+1), where Tclk is the system clock period, FTDIV is the contents of the
FLPSLR register and FTTRAN is the contents of the FLTRAN register.
5-µs
tPAH Programming address hold, new address setup
time 2-clock
cycles
tPEP Charge pump enable hold time 1-clock
cycles
tEDP Charge pump power hold timee
e. The program/erase end delay time is determined by the following equation:
tEDP = Tclk x (FTDIV+1) x (FTEND+1), where Tclk is the system clock period, FTDIV is the contents of the FLPSLR
register and FTEND is the contents of the FLEND register.
5µs
tCHVP Cumulative program high voltage period for each
row after erase.f
f. Cumulative program high voltage period for each row after erase tCHVP
is the accumulated duration a flash cell is
exposed to the programming voltage after the last erase cycle. It is the sum of all tHV after the last erase.
-25 ms
Data retention 100 -years
-100K cycles
Obsolete
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Flash EEPROM Data Programming
Flash EEPROM ISP-Memory Programming
Symbol Parameter Conditions Min Max Units
re-programming timea
a. One re-programming cycle involves one erase pulse followed by programming of four bytes.
1.32 -ms
tPWD Programming pulse width b
b. The programming pulse width is determined by the following equation:
tPWD = Tclk x (FTDIV+1) x (FTPROG+1), where Tclk is the system clock period, FTDIV is the contents of the
DMPSLR register and FTPROG is the contents of the DMPROG register.
30 40 µs
tEWD Erase pulse widthc
c. The erase pulse width is determined by the following equation:
tEWD = Tclk x (FTDIV+1) x 4 x (FTER+1), where Tclk is the system clock period, FTDIV is the contents of the
DMPSLR register and FTER is the contents of the DMERASE register.
1-ms
tSDD Charge pump power-up timed
d. The program/erase start delay time is determined by the following equation:
tSDD = Tclk x (FTDIV+1) x (FTSTART+1), where Tclk is the system clock period, FTDIV is the contents of the
DMPSLR register and FTSTART is the contents of the DMSTART register.
10 -µs
tTTD Program/erase transition timee
e. The program/erase transition time is determined by the following equation:
tTTD = Tclk x (FTDIV+1) x (FTTRAN+1), where T
clk is the system clock period, FTDIV is the contents of the
DMPSLR register and FTTRAN is the contents of the DMTRAN register.
5-µs
tPED Charge pump enable hold time 1-clock
cycles
tEDD Charge pump power hold timef
f. The program/erase end delay time is determined by the following equation:
tEDD = Tclk x (FTDIV+1) x (FTEND+1), where Tclk is the system clock period, FTDIV is the contents of the
DMPSLR register and FTEND is the contents of the DMEND register.
5-µs
Write/erase endurance (high endurance) 100,000 -cycles
Data retention 100 -years
Symbol Parameter Conditions Min Max Units
tPWI Programming pulse witha
a. Programming timing is controlled by the flash EEPROM data memory interface
30 40 µs
tEWI Erase pulse widthb
b. Erase timing is controlled by the flash EEPROM data memory interface
1-ms
Data retention 100 -years
Obsolete
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Output Signal Levels
All output signals are powered by the digital supply (VCC).
Table22 summarizes the states of the output signals during
the reset state (when VCC power exists in the reset state)
and during the Power Save mode.
The RESET and NMI input pins are active during the Power
Save mode. In order to guarantee that the Power Save cur-
rent not exceed 1mA, these inputs must be driven to a volt-
age lower than 0.5V or higher than V
CC-0.5V. An input
voltage between 0.5V and (VCC-0.5V) may result in power
consumption exceeding 1 mA.
Table 22Output Pins During Reset and Power-Save
Signals on a pin Reset state
(with Vcc) Power Save mode Comments
PF[0:7] TRI-STATE Previous state I/O ports will maintain their values when
entering power-save mode
PG[0:7] TRI-STATE Previous state
PI[0:7] TRI-STATE Previous state
PL[0:7] TRI-STATE Previous state
PB[0:7] TRI-STATE Previous state
PC[0:7] TRI-STATE Previous state
Obsolete
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21.0.1 Timing Waveforms
Figure 36.Clock Waveforms
Figure 37. ISE & NMI Signal Timing
ac-1
tXSh tXSl
tCLKp
X1 & X2
CLK
tCLKh tCLKl
tCLKf tCLKr
Output Valid Output Hold
Output
Signal
Input
Signal
Input Setup Input Hold
Control
Signal 1
Control
Signal 2
Output Active/Inactive time
Output Active/Inactive time
t
XSp
CLK
ISE
NMI
tIh
tIs
tIh
tIs tIw
tIw
Obsolete
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Figure 38.Non-Power-On Reset
Figure 39.USART Asynchronous Mode Timing
Figure 40.USART Synchronous Mode Timing
CLK
RESET tRST
CLK
TXD
121212121212
tIS
tIH
RXD
tCOv2 tCOv2
CKXn
TXDn
RXDn
tCLKX
tTXD
tRXS
tRXH
Obsolete
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Figure 41.Ports Signals Timing
Figure 42.MICROWIRE Transaction Timing, Normal Mode, MIDL Bit = 1
CLK
BUZCLK
PORTS B, C (output)
121212121212
tCOv2 tCOv2
tIs
tIh
tCOv1
tOf
PORTS B, C (input)
tCOv1
D6D7
t
MSKp
tMSKl tMSKh
tMDIs tMDIh
tMCSs
tMDOf
MSK
Data In
MDIDO
MCS
D0
tMDOf
tMDOv
tMDOh
tMSKs tMSKh
MRDY
tMCSh
tMRDYia
CLK
tMRDYa
(Slave)
(Slave)
MDODI
(slave)
(master)
D1
D7 D6 D1
D7 D6 D1 D0
D0
Obsolete
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Figure 43.MICROWIRE Transaction Timing, Alternate Mode, MIDL bit = 0
tMSKh tMSKl
tMDIs tMDIh
tMCSs
MSK
Data In
MDIDO
MCS
tMSKs tMSKh
MRDY
tMCSh
tMRDYia
CLK tMRDYa
(Slave)
(Slave)
t
MSKp
D7 D6 D1 D0
tMDOf tMDOf
tMDOv
tMDOh
(Slave)
MDODI
(Master) D7 D6 D1 D0
D7 D6 D1 D0
Obsolete
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Figure 44.MICROWIRE Transaction Timing, Normal Mode, MIDL bit = 0
D6D7
tMSKp
tMSKh tMSKl
tMDIs tMDIh
tMCSs
D6
tMDOf
MSK
Data In
MDIDO
MCS
D0
D0
tMDOf
tMDOv
tMDOh
D7
tMSKs tMSKh
MRDY
tMCSh
tMRDYia
CLK
tMRDYa
(Slave)
(Slave)
MDODI
(slave)
(master) D6 D0
D7
tMSKd
Obsolete
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Figure 45.MICROWIRE Transaction Timing, Alternate Mode, MIDL bit = 1
t
MSKp
tMSKl tMSKh
tMDIs tMDIh
tMCSs
tMDOf
MSK
MDIDO
MCS
tMDOf
tMCSh
tMDOv
tMDOh
tMSKs tMSKh
MRDY
tMRDYia
CLK tMRDYa
(Slave only)
(Slave only)
D0D7 D6
(Slave)
MDODI
(Master)
D7 D6 D0
D7 D6 D0
tSKd
Data In
Obsolete
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Figure 46.MICROWIRE Transaction Timing, Data Echoed to Output, Normal Mode, MIDLBit= 0, MECHBit= 1, Slave
Figure 47.Multi-Function-Timer (MFT16) Input Timing
DI6
tMSKp
tMSKh tMSKl
tMDIh
tMCSs
tMDOnf
MSK
MDODI
MDIDO
MCS
DI0
DO0
tMDOf
DO7
tMSKs tMSKh
MRDY
tMCSh
tMRDYia
CLK
tMRDYa
tMITOp
tMITOp
tMDIs
DI7
DO6
(Slave)
(Slave)
CLK
TnA/TnB
tTAL/ tTBL tTAH/ tTBH
Obsolete
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21.0.2 Timing Tables
Table 23Output Signals
Symbol Figure Description Reference Min (ns) Max (ns)
Tclk a36 CLK clock period R.E. CLK to next R.E. CLK 50 64000a
tCLKh 36 CLK high time At 2.0V
(Both Edges) 17.3
tCLKl 36 CLK low time At 0.8V
(Both Edges) 17.3
tCLKr 36 CLK rise time on R.E. CLK 0.8V to 2.0V 3
tCLKf 36 CLK fall time on F.E. CLK 2.0V to 0.8V 3
tCOv1
CMOS output valid
All signals with prop. delay from CLK
R.E.
After R.E. CLK 35
USART Output Signals
tTXD 45 TXDn output valid After R.E. CLKXn 35
MICROWIRE / SPI Output Signals
tMSKh 42 MICROWIRE Clock High At 2.0V (both edges) 80
tMSKl 42 MICROWIRE Clock Low At 0.8V (both edges) 80
tMSKp 42 MICROWIRE Clock Period MnIDL bit = 0: R.E. MSK to next R.E. MSKn 200
43 MnIDL bit = 1: F.E. MSK to next F.E. MSKn
tMSKd 42 MSK Leading Edge Delayed (master
only) Data Out Bit #7 Valid 0.5 tMSK 1.5 tMSK
tMDOf 42 MICROWIRE Data Float b
(slave only) After R.E. MCSn 56
tMDOh 42 MICROWIRE Data Out Hold Normal Mode: After F.E. MSK 0.0
Alternate Mode: After R.E. MSK
tMDOnf 42 MICROWIRE Data No Float (slave only) After F.E. MWCS 056
tMDOv 42 MICROWIRE Data Out Valid Normal Mode: After F.E. MSK 56
Alternate Mode: After R.E. MSK
tMITOp 46
MDODI to MDIDO
(slave only) Propagation Time
Value is the same in all clocking modes of the
MICROWIRE 56
tMRDYa 42 MRDY Active (slave only) After R.E. of CLK 028
tMRDYia 42 MRDY Inactive (slave only) MIDL bit = 0: After F.E. MSK 056
MIDL bit = 1: After R.E. MSK
a. Tclk is the actual clock period of the CPU clock used in the system.
The value of Tclk is system dependent.
The maximum cycle time of 64000ns is for Power Save mode; in active mode, the maximum cycle time is limited to 250ns by the
high frequency oscillator.
b. Guaranteed by design, but not fully tested.
c. Hold time is 0 ns (min) for all outputs, unless specified otherwise.
Table 24Input Signal Requirements
Symbol Figure Description Reference Min (ns) Max (ns)
tXSp 36 X1 period R.E. X1 to next R.E. X1 50 250
tXSh 36 X1 high time, external clock At 2V level (Both Edges) 0.5 Tclk - 4
tXSl 36 X1 low time, external clock At 0.8V level (Both Edges) 0.5 Tclk - 4
tX2p 36 X2 period aR.E. X2 to next R.E. X2 10,000
tX2h 36 X2 high time, external clock At 2V level (both edges) 0.5 Tclk - 500
Obsolete
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tX2l 36 X2 low time, external clock At 0.8V level (both edges) 0.5 Tclk - 500
tIs 42 Input setup time
ISE Before R.E. CLK 12
tIh 42 Input hold time
ISE, NMI, RXD1, RXD2 After R.E. CLK 0
tRST 43 Reset time Reset active to reset end 4Tclk
Input Signals
Input Pulse Width 1*Tclk+13
USART Input Signals
tIs 39 Input setup time
RXDn (asynchronous mode) Before R.E. CLK 12
tIh 39 Input hold time
RXDn (asynchronous mode) After R.E. CLK 0
tCLKX 40 CKXn input period
(synchronous mode) 200
tRXS 40 RDXn setup time
(synchronous mode) Before F.E. CKX in synchronous mode 4
tRXH 40 RDXn hold time
(synchronous mode) After F.E. CKX in synchronous mode 2
MICROWIRE / SPI Input Signals
tMSKh 42 MICROWIRE Clock High At 2.0V (both edges) 80
tMSKl 42 MICROWIRE Clock Low At 0.8V (both edges) 80
tMSKp 42 MICROWIRE Clock Period MnIDL bit = 0; R.E. MSK to next R.E. MSK 200
43 MIDL bit = 1; F.E. MSK to next F.E. MSK
tMSKh 42 MSK Hold (slave only) After MCS becomes inactive 40
tMSKs 42 MSK Setup (slave only) Before MCS becomes active 80
tMCSh 42 MCS Hold (slave only) MIDL bit = 0: After F.E. MSK 40
43 MIDL bit = 1: After R.E. MSK
tMCSs 42 MCS Setup (slave only) MIDL bit = 0: Before R.E. MSK 80
43 MIDL bit = 1: Before F.E. MSK
tMDIh
42 MICROWIRE Data In Hold (master) Normal Mode: After R.E. MSK 0
44 Alternate Mode: After F.E. MSK
42 MICROWIRE Data In Hold (slave) Normal Mode: After R.E. MSK 40
44 Alternate Mode: After F.E. MSK
tMDIs 42 MICROWIRE Data In Setup Normal Mode: Before R.E. MSK 80
44 Alternate Mode: Before F.E. MSK
Multi-Function Timer Input Signals
tTAH 47 TnA High Time R.E. CLK TCLK+5
tTAL 47 TnA Low Time R.E. CLK TCLK+5
tTBH 47 TnB High Time R.E. CLK TCLK+5
tTBL 47 TnB Low Time R.E. CLK TCLK+5
a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used
between X2CKI and X2CKO. If the slow clock is internally generated from the fast clock, it may not exceed this
given limit.
Table 24Input Signal Requirements
Symbol Figure Description Reference Min (ns) Max (ns)
Obsolete
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22.0 Appendix
22.1 8-BIT MICROWIRE/SPI (MWSPI)
22.1.1 MWSPI Problem Description
According to the specification, the MSKn clock output in mas-
ter mode should have the value of the MnIDL bit of the
MUnCTL1 register, even when the module is disabled. How-
ever, the MSKn pin will always be at low level, when the al-
ternate function of the MSKn pin is enabled and the module
is disabled. Thus, even if the MnIDL bit is set, the MSKn clock
will change to a low level as soon as the module is disabled.
If any slave is selected at this time, it will interpret this un-
wanted transition as a shift clock.
22.1.2 MWSPI Problem Cause
Even if the module is disabled and the alternate function of
the MSKn pin is enabled, the module can still influence the
MSKn pin and drives the default value ‘0’.
22.1.3 MWSPI Problem Solutions
When the MSKn idle level of ‘1’ is to be used, the following
procedure should be followed when the module is disabled:
1. Set the MSKn pin to high level in the corresponding port
data output register.
2. Configure the MSKn pin to an output in the correspond-
ing port direction register.
3. Disable the alternate function of the MSKn pin in the cor-
responding port alternate function register.
4. Disable the MWSPI module.
22.2 TIMING AND WATCHDOG MODULE
22.2.1 Timing and WATCHDOG Module Problem
Description
The available window for a valid WATCHDOG service varies
with the TWM configuration and the operating mode of the
R16MHS9. Therefore it is not possible to generally provide
the limits for the maximum service window. However, the lim-
its for the minimum service window is guaranteed and should
be used.
22.2.2 Timing and WATCHDOG Module Problem
Cause
The timing and WATCHDOG module uses two different clock
signals for its operation, the slow system clock as well as the
fast system clock.
The slow system clock can either be generated by an exter-
nal 32 kHz quartz or it can be derived from the fast system
clock by means of a prescaler counter in the CLK2RES mod-
ules. The TWM can operate off a maximum slow system
clock of 100 kHz. The WATCHDOG counter (down-counter)
is either clocked directly by the slow system (T0IN) or it is
decremented every time the counter T0 underflows
(T0OUT).
The fast system clock is used for accesses to TWM registers,
which build the user interface of the TWM. These user inter-
face registers include all memory-mapped registers of the
TWM.
Every time the user (CR16B core) writes to a TWM configu-
ration register or to the WATCHDOG Service Data Match
register, this “high speed operation” must be synchronized to
the internal TWM logic running at the slow clock rate. This
synchronization process takes a variable number of low
speed clock cycles, depending on the ratio between the low-
speed and the high-speed system clock and the phase shift
between the two clock signals. The more the two frequencies
differ from each other, the longer it takes the synchronization
process.
In other words, write operations to the TWM registers take a
certain number of low-speed clock cycles to show the de-
sired effects to the TWM logic.
This fact is especially critical for the write operation for the
WATCHDOG service, as it affects the allowed window for a
valid WATCHDOG service.
If the device runs in active mode, the synchronization pro-
cess can take up to four WATCHDOG counter clock cycles.
This limits the available WATCHDOG service to the window
shown in Figure48:
Figure 48.WATCHDOG Services Windows in Active Mode
Obsolete
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If the device runs in power save mode, the synchronization
process can take up to eight WATCHDOG counter clock cy- cles. This limits the available WATCHDOG service to the win-
dow shown in Figure49:
22.2.3 Timing and WATCHDOG Module Problem
Solutions
In order to guarantee a valid WATCHDOG service under all
circumstances, the WATCHDOG should only be serviced
within the guaranteed minimum valid window, as illustrated in
figure 48 and figure 49 in the previous section.
Figure 49.WATCHDOG Services Windows in Power Save Mode
Obsolete
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/
CR16MUS5/CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time without notice, to change said circuitry or specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to per-
form, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably ex-
pected to result in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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23.0 Physical Dimension inches (millimeters) unless otherwise noted
80 Lead Molded Plastic Quad Flat Package
See NS Package Number VJE80A
Obsolete
