4 Megabit CMOS EEPROM DPE512S8N DESCRIPTION: The DPE512S8N is a 512K X 8 high-density, low-power EEPROM module comprised of four ceramic 128K X 8 monolithic EEPROM's, an advanced high-speed CMOS decoder and decoupling capacitors surface mounted on a co-fired ceramic substrate having side-brazed leads. The DPE512S8N is available in a 600-mil-wide, 32-pin dual-in-line package that conforms to the same JEDEC standard pin configuration as the future four megabit monolithics. The DPE512S8N operates from a single +5V supply and all input and output pins are completely TTL-compatible. FEATURES: * 524,288 by 8 bit configuration * Fast Access Times: 135, 170, 250, 300ns (max.) * Low Power Available in Commercial Only * * * * * Dissipation: 495 mW Operating 6.6 mW (CMOS) Standby Fast Write Cycle Times 128 Byte Page Write Operation 10ms Typical Byte Write Operation Data Protection Hardware and Software (JEDEC - Approved) Write Protection High Endurance 10,000 Program / Erase Cycles 10 Year Data Retention JEDEC Approved Byte Wide Pinout Only 1.660 x 0.600 x 0.400 inches PIN NAMES A0 - A18 Address Inputs I/O0 - I/O7 Data In/Out CE Chip Enable WE Write Enable OE Output Enable VDD Power (+5V) VSS Ground PIN-OUT DIAGRAM FUNCTIONAL BLOCK DIAGRAM 30A046-00 REV. C This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 DPE512S8N Dense-Pac Microsystems, Inc. RECOMMENDED OPERATING RANGE Symbol Characteristic Min. Typ. VDD Supply Voltage 4.5 5.0 VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage C 0 +25 Operating TA I -40 +25 Temperature M/B -55 +25 Max. 5.5 0.8 +70 +85 +125 ABSOLUTE MAXIMUM RATINGS Symbol TSTG TBIAS VDD VI/O Parameter Storage Temperature Temperature Under Bias Supply Voltage 2 Input/Output Voltage 2 TRUTH TABLE 1 oC L = LOW 1 Value -65 to +150 -65 to +135 -0.6 to +6.25 -0.6 to +6.25 CE H L L X X Mode Standby Read Write Write Inhibit Write Inhibit Unit V V V OE X L H L X WE X H L X H H = HIGH I/I Pin HIGH-Z DOUT DIN HIGH-Z HIGH-Z X = Don't Care CAPACITANCE 3: TA = 25C, F = 1.0MHz Unit C C C V Symbol CCE CADR CWE COE CI/O Parameter Chip Enable Address Input Write Enable Output Enable Data Input/Output Max. 20 50 50 50 60 Unit Condition pF VIN = 0V AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels 0V to 3.0V 5ns* Figure 1. Output Load ** Including Probe and Jig Capacitance. 1.5V +5V * Transition between 0.8V and 2.2V. 1.8K DOUT OUTPUT LOAD Load 1 2 CL 100pF 5pF Parameters Measured except tDF tDF CL** 1.3K DC OPERATING CHARACTERISTICS: Over operating ranges Symbol IIN IOUT ICC ISB1 ISB2 VIL VIH VOL VOH 2 Characteristics Input Leakage Current Output Leakage Current Operating Supply Current VDD Standby Current (TTL) VDD Standby Current (CMOS) Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Test Conditions X8 Unit Min. Max. VIN = VDD Max. -40 +40 A VOUT = VDD Max. -40 +40 A 90 mA 12 1.2 0.8 mA mA V V V V CE = OE = VIL, all I/O = 0mA, f = 5MHz CE = VIH CE = VDD -0.3Vdc 2.0 IOUT = 2.1mA IOUT = -400A 0.45 2.4 30A046-00 REV. C DPE512S8N Dense-Pac Microsystems, Inc. AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol 1 2 3 4 5 tRC tCE tACC tOE tDF 6 tOH 135ns Parameter Min. Read Cycle Time Chip Enable to Output Valid Address Access Time Output Enable Access Time Chip Enable or Output Enable to Output Float 3 Output Hold from Chip Enable, Output Enable, or Address, Whichever Occurs First 170ns Max. 135 0 Min. 170 135 135 50 60 0 0 0 250ns Max. Min. Max. 250 170 170 55 65 0 300ns Unit Min. Max. 300 250 250 55 65 0 0 ns ns ns ns ns 300 300 55 65 0 ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges 5, 6 No. 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol tWC tAS tAH tCS tCH tWP tDS tDH tOES tOEH tWPH tBLC tWR Parameter Write Cycle Time Address Set-up Time * Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data Hold Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Byte Load Cycle Time Write Recovery Time Min. Max. 10 10 100 0 0 150 100 10 10 10 50 150 0 Unit ms ns ns ns ns ns ns ns ns ns ns s ns * Valid for both Read and Write Cycles. READ CYCLE ADDRESS CE OE DATA I/O 30A046-00 REV. C 3 DPE512S8N Dense-Pac Microsystems, Inc. WRITE CYCLE 1: WE Controlled. OE ADDRESS CE WE DATA IN WRITE CYCLE 2: CE Controlled. OE ADDRESS WE CE DATA IN WAVEFORM KEY Data Valid 4 Transition from HIGH to LOW Transition from LOW to HIGH Data Undefined or Don't Care 30A046-00 REV. C DPE512S8N Dense-Pac Microsystems, Inc. PAGE MODE WRITE WAVEFORM OE CE WE A0 - A6 DATA DATA POLLING WAVEFORM WE CE OE I/O7 A0 - A6 DEVICE OPERATION READ: The DPE512S8N is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention. WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE. Once a byte Write has been started it will automatically time itself to completion. PAGE WRITE: The page write operation of the DPE512S8N allows 1 to 128 bytes of data to be loaded into the device and then simultaneously written during the internal programming period. After the first byte of data has been loaded into the device, successive bytes may be loaded in the same manner. Each new byte to be written must have its high to low transition on WE (or CE) within 150s of the low to high 30A046-00 REV. C transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150s of the last low to high transition, the load period will end and the internal programming period will start. A7 to A18 specify the page address. The page address must be valid during each high to low transition of WE (or CE). A0 to A6 are used to specify which byte within the page are to be written. The bytes may loaded in any order and may be changed within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: Write cycles typically are completed in less time than the maximum write cycle time of 10ms. To determine when the write is completed, a method called DATA Polling is utilized. If a read is performed on the address of the last byte written to the DPE512S8N while a write cycle is in progress, the one's compliment of the most significant bit (I/O7) will appear on the output. When the write is completed, a read from the last address written will return valid data. A DATA Polling may begin at any time during the Write Cycle. 5 DPE512S8N Dense-Pac Microsystems, Inc. ORDERING INFORMATION * * B grade modules are constructed with 883 devices. NOTES: 1. All voltages are with respect to VSS. 2. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. This parameter is guaranteed and not 100% tested. 4. Address hold time is with respect to the falling edge of the control signal WE or CE. 5. WE and CE are noise protected. Less than a 15ns write pulse will not activate a write cycle. MECHANICAL DIAGRAM Dense-Pac Microsystems, Inc. 7321 Lincoln Way u Garden Grove, California 92841-1428 (714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com 6 30A046-00 REV. C