4 Megabit CMOS EEPROM
DPE512S8N
PIN NAMES
A0 - A18 Address Inputs
I/O0 - I/O7 Data In/Out
CE Chip Enable
WE Write Enable
OE Output Enable
VDD Power (+5V)
VSS Ground
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The DPE512S8N is a 512K X 8 high-density,
low-power EEPROM module comprised of four
ceramic 128K X 8 monolithic EEPROM’s, an advanced
high-speed CMOS decoder and decoupling capacitors
surface mounted on a co-fired ceramic substrate
having side-brazed leads.
The DPE512S8N is available in a 600-mil-wide, 32-pin
dual-in-line package that conforms to the same JEDEC
standard pin configuration as the future four megabit
monolithics.
The DPE512S8N operates from a single +5V supply
and all input and output pins are completely
TTL-compatible.
FEATURES:
•524,288 by 8 bit configuration
•Fast Access Times: 135, 170, 250, 300ns (max.)
•Low Power Available in Commercial Only
Dissipation:
495 mW Operating
6.6 mW (CMOS) Standby
•Fast Write Cycle Times
128 Byte Page Write Operation
10ms Typical Byte Write Operation
•Data Protection
Hardware and Software (JEDEC - Approved)
Write Protection
•High Endurance
10,000 Program / Erase Cycles
10 Year Data Retention
•JEDEC Approved Byte Wide Pinout
•Only 1.660 x 0.600 x 0.400 inches
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A046-00
REV. C 1
DPE512S8N Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE 1
Symbol Characteristic Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
VIH Input HIGH Voltage 2.0 V
VIL Input LOW Voltage 0.8 V
TAOperating
Temperature
C0+25 +70
oCI-40 +25 +85
M/B -55 +25 +125
ABSOLUTE MAXIMUM RATINGS 1
Symbol Parameter Value Unit
TSTG Storage Temperature -65 to +150 °C
TBIAS Temperature Under Bias -65 to +135 °C
VDD Supply Voltage 2 -0.6 to +6.25 °C
VI/O Input/Output Voltage 2 -0.6 to +6.25 V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol Characteristics Test Conditions X8 Unit
Min. Max.
IIN Input
Leakage Current VIN = VDD Max. -40 +40 µA
IOUT Output
Leakage Current VOUT = VDD Max. -40 +40 µA
ICC Operating Supply
Current CE = OE = VIL,
all I/O = 0mA, f = 5MHz 90 mA
ISB1 VDD Standby Current (TTL) CE = VIH 12 mA
ISB2 VDD Standby Current (CMOS) CE = VDD -0.3Vdc 1.2 mA
VIL Input Voltage Low 0.8 V
VIH Input Voltage High 2.0 V
VOL Output Voltage Low IOUT = 2.1mA 0.45 V
VOH Output Voltage High IOUT = -400µA2.4 V
CAPACITANCE 3: TA = 25°C, F = 1.0MHz
Symbol Parameter Max. Unit Condition
CCE Chip Enable 20
pF VIN = 0V
CADR Address Input 50
CWE Write Enable 50
COE Output Enable 50
CI/O Data Input/Output 60
+5V
1.3KΩ
1.8KΩ
CL**
DOUT
Figure 1. Output Load
** Including Probe and Jig Capacitance.
OUTPUT LOAD
Load CLParameters Measured
1100pF except tDF
25pF tDF
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Pulse Rise and Fall Times 5ns*
Input and Output
Timing Reference Levels 1.5V
* Transition between 0.8V and 2.2V.
TRUTH TABLE
Mode CE OE WE I/I Pin
Standby HX X HIGH-Z
Read L L H DOUT
Write LHLDIN
Write Inhibit XLXHIGH-Z
Write Inhibit X X HHIGH-Z
L = LOW H = HIGH X = Don’t Care
30A046-00
REV. C
2
Dense-Pac Microsystems, Inc. DPE512S8N
READ CYCLE
ADDRESS
CE
OE
DATA I/O
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol Parameter 135ns 170ns 250ns 300ns Unit
Min. Max. Min. Max. Min. Max. Min. Max.
1tRC Read Cycle Time 135 170 250 300 ns
2tCE Chip Enable to Output Valid 135 170 250 300 ns
3tACC Address Access Time 135 170 250 300 ns
4tOE Output Enable Access Time 50 55 55 55 ns
5tDF Chip Enable or Output Enable to Output Float 3 060 065 065 065 ns
6tOH Output Hold from Chip Enable, Output Enable,
or Address, Whichever Occurs First 0 0 0 0ns
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges 5, 6
No. Symbol Parameter Min. Max. Unit
7tWC Write Cycle Time 10 ms
8tAS Address Set-up Time * 10 ns
9tAH Address Hold Time 100 ns
10 tCS Chip Select Set-up Time 0ns
11 tCH Chip Select Hold Time 0ns
12 tWP Write Pulse Width (WE or CE)150 ns
13 tDS Data Set-up Time 100 ns
14 tDH Data Hold Time 10 ns
15 tOES Output Enable Set-up Time 10 ns
16 tOEH Output Enable Hold Time 10 ns
17 tWPH Write Pulse Width High 50 ns
18 tBLC Byte Load Cycle Time 150 µs
19 tWR Write Recovery Time 0ns
* Valid for both Read and Write Cycles.
30A046-00
REV. C 3
DPE512S8N Dense-Pac Microsystems, Inc.
WAVEFORM KEY
Data Valid Transition from Transition from Data Undefined
HIGH to LOW LOW to HIGH or Don’t Care
WRITE CYCLE 1: WE Controlled.
OE
ADDRESS
CE
WE
DATA IN
WRITE CYCLE 2: CE Controlled.
OE
ADDRESS
WE
CE
DATA IN
30A046-00
REV. C
4
Dense-Pac Microsystems, Inc. DPE512S8N
DEVICE OPERATION
READ: The DPE512S8N is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored at
the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual line
control gives designers flexibility in preventing bus
contention.
WRITE: A low pulse on the WE or CE input with CE or WE
low (respectively) and OE high initiates a write cycle. The
address is latched on the falling edge of CE or WE. Once a
byte Write has been started it will automatically time itself to
completion.
PAGE WRITE: The page write operation of the DPE512S8N
allows 1 to 128 bytes of data to be loaded into the device and
then simultaneously written during the internal programming
period. After the first byte of data has been loaded into the
device, successive bytes may be loaded in the same manner.
Each new byte to be written must have its high to low
transition on WE (or CE) within 150µs of the low to high
transition of WE (or CE) of the preceding byte. If a high to low
transition is not detected within 150µs of the last low to high
transition, the load period will end and the internal
programming period will start. A7 to A18 specify the page
address. The page address must be valid during each high to
low transition of WE (or CE). A0 to A6 are used to specify
which byte within the page are to be written. The bytes may
loaded in any order and may be changed within the same
load period. Only bytes which are specified for writing will
be written; unnecessary cycling of other bytes within the page
does not occur.
DATA POLLING: Write cycles typically are completed in
less time than the maximum write cycle time of 10ms. To
determine when the write is completed, a method called
DATA Polling is utilized. If a read is performed on the address
of the last byte written to the DPE512S8N while a write cycle
is in progress, the one’s compliment of the most significant
bit (I/O7) will appear on the output. When the write is
completed, a read from the last address written will return
valid data. A DATA Polling may begin at any time during the
Write Cycle.
PAGE MODE WRITE WAVEFORM
OE
CE
WE
A0 - A6
DATA
DATA POLLING WAVEFORM
WE
CE
OE
I/O7
A0 - A6
30A046-00
REV. C 5
DPE512S8N Dense-Pac Microsystems, Inc.
NOTES:
1. All voltages are with respect to VSS.
2. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
3. This parameter is guaranteed and not 100% tested.
4. Address hold time is with respect to the falling edge of the control signal WE or CE.
5. WE and CE are noise protected. Less than a 15ns write pulse will not activate a write cycle.
Dense-Pac Microsystems, Inc.
7321 Lincoln Way u Garden Grove, California 92841-1428
(714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com
ORDERING INFORMATION
MECHANICAL DIAGRAM
* B grade modules are constructed with 883 devices.
*
30A046-00
REV. C
6
