ADC101C021CIMK/NOPB - NATIONAL SEMICONDUCTOR

ADC101C021, ADC101C027

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SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

ADC101C021/ADC101C027 I

C-Compatible, 10-Bit Analog-to-Digital Converter (ADC) with

Alert Function

Check for Samples: ADC101C021,ADC101C027

1FEATURES DESCRIPTION

The ADC101C021 is a low-power, monolithic, 10-bit,

23• I2C-Compatible 2-wire Interface which analog-to-digital converter (ADC) that operates from a

supports standard (100kHz), fast (400kHz), and +2.7 to 5.5V supply. The converter is based on a

high speed (3.4MHz) modes successive approximation register architecture with

• Extended power supply range (+2.7V to +5.5V) an internal track-and-hold circuit that can handle input

frequencies up to 11MHz. The ADC101C021

• Up to nine pin-selectable chip addresses operates from a single supply which also serves as

(VSSOP-8 only) the reference. The device features an I2C-compatible

• Out-of-range Alert Function serial interface that operates in all three speed

• Automatic Power-down mode while not modes, including high speed mode (3.4MHz).

converting The ADC's Alert feature provides an interrupt that is

• Very small SOT-6 and VSSOP-8 packages activated when the analog input violates a

• ±8kV HBM ESD protection (SDA, SCL) programmable upper or lower limit value. The device

features an automatic conversion mode, which frees

up the controller and I2C interface. In this mode, the

APPLICATIONS ADC continuously monitors the analog input for an

• System Monitoring "out-of-range" condition and provides an interrupt if

• Peak Detection the measured voltage goes out-of-range.

• Portable Instruments The ADC101C021 comes in two packages: a small

• Medical Instruments SOT-6 package with an alert output, and an VSSOP-

8 package with an alert output and two address

• Test Equipment selection inputs. The ADC101C027 comes in a small

SOT-6 package with an address selection input. The

KEY SPECIFICATIONS ADC101C027 provides three pin-selectable

• Resolution 10 bits; no missing codes addresses while the VSSOP-8 version of the

ADC101C021 provides nine pin-selectable

• Conversion Time 1µs (typ) addresses. Pin-compatible alternatives to the SOT-6

• INL & DNL ±0.5 LSB (max) options are available with additional address options.

• Throughput Rate 188.9 kSPS (max) Normal power consumption using a +3V or +5V

• Power Consumption (at 22kSPS) supply is 0.26mW or 0.78mW, respectively. The

– 3V Supply 0.26 mW (typ) automatic power-down feature reduces the power

consumption to less than 1µW while not converting.

– 5V Supply 0.78 mW (typ) Operation over the industrial temperature range of

−40°C to +105°C is guaranteed. Their low power

consumption and small packages make this family of

ADCs an excellent choice for use in battery operated

equipment.

The ADC101C021 and ADC101C027 are part of a

family of pin-compatible ADCs that also provide 12

and 8 bit resolution. For 12-bit ADCs see the

ADC121C021 and ADC121C027. For 8-bit ADCs see

the ADC081C021 and ADC081C027.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2I2C is a registered trademark of Phillips Corporation.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ALERT

SDA

ADR1

GND

SCL

VIN

ADC101C021

ADR0

ADDR

SCL

SDA

VIN

GND

ADC101C027

ALERT

SCL

SDA

VIN

GND

ADC101C021

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

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Table 1. Pin-Compatible Alternatives(1)

Resolution SOT-6 (Alert only) and VSSOP-8 SOT-6 (Addr only)

12-bit ADC121C021 ADC121C027

10-bit ADC101C021 ADC101C027

8-bit ADC081C021 ADC081C027

(1) All devices are fully pin and function compatible.

Connection Diagrams

SOT PACKAGE

VSSOP PACKAGE

Product Folder Links: ADC101C021 ADC101C027

SDA

SCL

Lowest Conversion

Configuration

I2C Serial Interface

ADC101C021/

ADC101C027

Conversion Result

High Limit

Low Limit

Pointer

and

Decode

Logic

Alert

Set-Point

Comparator

ADDR*

Highest Conversion

10-Bit

Successive

Approximation

ADC

GND

Hysteresis

VIN

Alert Status

ALERT*

T/H

Oscillator

REF

* Note: The ADC101C021 has the ALERT pin but no ADDR pin.

The ADC101C027 has the ADDR pin but no ALERT pin.

ADC101C021, ADC101C027

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Block Diagram

Product Folder Links: ADC101C021 ADC101C027

Snap

Back

GND

V+

2.1k 41.5k

41.5k

Snap

Back

GND

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

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PIN DESCRIPTIONS

Symbol Type Equivalent Circuit Description

Power and unbufferred reference voltage. VAmust be free

VASupply of noise and decoupled to GND.

GND Ground Ground for all on-chip circuitry.

VIN Analog Input See Figure 19 Analog input. This signal can range from GND to VA.

Alert output. Can be configured as active high or active low.

ALERT Digital Output This is an open drain data line that must be pulled to the

supply (VA) with an external pull-up resistor.

Serial Clock Input. SCL is used together with SDA to control

the transfer of data in and out of the device. This is an open

drain data line that must be pulled to the supply (VA) with an

SCL Digital Input external pull-up resistor. This pin's extended ESD tolerance(

8kV HBM) allows extension of the I2C bus across multiple

boards without extra ESD protection.

Serial Data bi-directional connection. Data is clocked into or

out of the internal 16-bit register with SCL. This is an open

Digital drain data line that must be pulled to the supply (VA) with an

SDA Input/Output external pull-up resistor. This pin's extended ESD tolerance(

8kV HBM) allows extension of the I2C bus across multiple

boards without extra ESD protection.

Tri-level Address Selection Input. Sets Bits A0 & A1 of the

ADR0 7-bit slave address. (see Table 3)

Digital Input,

three levels Tri-level Address Selection Input. Sets Bits A2 & A3 of the

ADR1 7-bit slave address. (see Table 3)

Table 2. Package Pinouts

VAGND VIN ALERT SCL SDA ADR0 ADR1

ADC101C021 1 2 3 4 5 6 N/A N/A

SOT-6

ADC101C027 1 2 3 N/A 5 6 4 N/A

SOT-6

ADC101C021 57421836

VSSOP-8

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: ADC101C021 ADC101C027

I/O

GND

TO INTERNAL

CIRCUITRY

ADC101C021, ADC101C027

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SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

Absolute Maximum Ratings(1)(2)(3)

Supply Voltage, VA-0.3V to +6.5V

Voltage on any Analog Input Pin to GND −0.3V to (VA+0.3V)

Voltage on any Digital Input Pin to GND −0.3V to 6.5V

Input Current at Any Pin(4) ±15 mA

Package Input Current(4) ±20 mA

Power Dissipation at TA= 25°C See (5)

Human Body Model 2500 V

VA, GND, VIN, ALERT, ADR pins: Machine Model 250 V

ESD Susceptibility Charged Device Model (CDM) 1250 V

Human Body Model 8000 V

SDA, SCL pins: Machine Model 400 V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating

Ratings is not recommended.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited per the Absolute Maximum

Ratings. The maximum package input current rating limits the number of pins that can safely exceed the power supplies.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe

fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

Operating Ratings(1) (2)

Operating Temperature Range −40°C ≤TA≤+105°C

Supply Voltage, VA+2.7V to 5.5V

Analog Input Voltage, VIN 0V to VA

Digital Input Voltage(3) 0V to 5.5V

Sample Rate up to 188.9 ksps

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating

Ratings is not recommended.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion

result. For example, if VAis 3V, the digital input pins can be driven with a 5V logic device.

Package Thermal Resistances

Package θJA

6-Lead SOT 250°C/W

8-Lead VSSOP 200°C/W

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Electrical Characteristics

The following specifications apply for VA= +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz, fIN

= 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C

unless otherwise noted. Typical Limits

Symbol Parameter Conditions Units (Limits)

(1) (1)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 10 Bits

VA= +2.7V to +3.6V ±0.1 ±0.5 LSB (max)

Integral Non-Linearity (End Point

INL +0.21 +0.7 LSB (max)

Method) VA= +2.7V to +5.5V. fSCL up to 400 kHz(2)

−0.16 −0.7 LSB (min)

VA= +2.7V to +3.6V ±0.1 ±0.5 LSB (max)

DNL Differential Non-Linearity +0.25 +0.7 LSB (max)

VA= +2.7V to +5.5V. fSCL up to 400 kHz(2)

−0.16 −0.7 LSB (min)

VA= +2.7V to +3.6V +0.25 ±0.8 LSB (max)

fSCL up to 3.4 MHz

VOFF Offset Error VA= +2.7V to +5.5V. fSCL up to 400kHz (2) +0.27 ±0.8 LSB (max)

GE Gain Error -0.13 ±1 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

VA= +2.7V to +3.6V 9.97 9.87 Bits (min)

ENOB Effective Number of Bits VA= +3.6V to +5.5V 9.94 Bits

VA= +2.7V to +3.6V 61.8 61.2 dB (min)

SNR Signal-to-Noise Ratio VA= +3.6V to +5.5V 61.6 dB

VA= +2.7V to +3.6V −88.9 −74 dB (max)

THD Total Harmonic Distortion VA= +3.6V to +5.5V −85.7 dB

VA= +2.7V to +3.6V 61.8 61.2 dB (min)

SINAD Signal-to-Noise Plus Distortion Ratio VA= +3.6V to +5.5V 61.6 dB

VA= +2.7V to +3.6V 84 76 dB (min)

SFDR Spurious-Free Dynamic Range VA= +3.6V to +5.5V 84.3 dB

Intermodulation Distortion, Second fa= 1.035 kHz, fb= 1.135 kHz −83.9 dB

Order Terms (IMD2)

IMD Intermodulation Distortion, Third fa= 1.035 kHz, fb= 1.135 kHz −82.4 dB

Order Terms (IMD3)VA= +3.0V 8 MHz

FPBW Full Power Bandwidth (−3dB) VA= +5.0V 11 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current (3) ±1 µA (max)

Track Mode 30 pF

CINA Input Capacitance Hold Mode 3 pF

(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average

Outgoing Quality Level).

(2) The ADC will meet Minimum/Maximum specifications for fSCL up to 3.4MHz when operating in the Quiet Interface Mode (Section 1.11).

(3) This parameter is guaranteed by design and/or characterization and is not tested in production.

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Electrical Characteristics (continued)

The following specifications apply for VA= +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz, fIN

= 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C

unless otherwise noted. Typical Limits

Symbol Parameter Conditions Units (Limits)

(1) (1)

SERIAL INTERFACE INPUT CHARACTERISTICS (SCL, SDA)

VIH Input High Voltage 0.7 x VAV (min)

VIL Input Low Voltage 0.3 x VAV (max)

IIN Input Current (4) ±1 µA (max)

CIN Input Pin Capacitance 3 pF

VHYST Input Hysteresis 0.1 x VAV (min)

ADDRESS SELECTION INPUT CHARACTERISTICS (ADDR)

VIH Input High Voltage VA- 0.5V V (min)

VIL Input Low Voltage 0.5 V (max)

IIN Input Current (4) ±1 µA (max)

LOGIC OUTPUT CHARACTERISTICS, OPEN-DRAIN (SDA, ALERT)

ISINK = 3 mA 0.4 V (max)

VOL Output Low Voltage ISINK = 6 mA 0.6 V (max)

High-Impedence Output

IOZ ±1 µA (max)

Leakage Current (4)

Output Coding Straight (Natural) Binary

POWER REQUIREMENTS

Supply Voltage Minimum 2.7 V (min)

VASupply Voltage Maximum 5.5 V (max)

Continuous Operation Mode -- 2-wire interface active. VA= 2.7V to 3.6V 0.08 0.14 mA (max)

fSCL=400kHz VA= 4.5V to 5.5V 0.16 0.30 mA (max)

INSupply Current VA= 2.7V to 3.6V 0.37 0.55 mA (max)

fSCL=3.4MHz VA= 4.5V to 5.5V 0.74 0.99 mA (max)

VA= 3.0V 0.26 mW

fSCL=400kHz VA= 5.0V 0.78 mW

PNPower Consumption VA= 3.0V 1.22 mW

fSCL=3.4MHz VA= 5.0V 3.67 mW

Automatic Conversion Mode -- 2-wire interface stopped and quiet (SCL = SDA = VA). fSAMPLE = TCONVERT * 32

VA= 2.7V to 3.6V 0.41 0.59 mA (max)

IASupply Current VA= 4.5V to 5.5V 0.78 1.2 mA (max)

VA= 3.0V 1.35 mW

PAPower Consumption VA= 5.0V 3.91 mW

Power Down Mode (PD1) -- 2-wire interface stopped and quiet. (SCL = SDA = VA).(4)

IPD1 Supply Current 0.1 0.2 µA (max)

PPD1 Power Consumption 0.5 0.9 µW (max)

Power Down Mode (PD2) -- 2-wire interface active. Master communicating with a different device on the bus.

VA= 2.7V to 3.6V 13 45 µA (max)

fSCL=400kHz VA= 4.5V to 5.5V 27 80 µA (max)

IPD2 Supply Current VA= 2.7V to 3.6V 89 150 µA (max)

fSCL=3.4MHz VA= 4.5V to 5.5V 168 250 µA (max)

(4) This parameter is guaranteed by design and/or characterization and is not tested in production.

Product Folder Links: ADC101C021 ADC101C027

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Electrical Characteristics (continued)

The following specifications apply for VA= +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz, fIN

= 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C

unless otherwise noted. Typical Limits

Symbol Parameter Conditions Units (Limits)

(1) (1)

VA= 3.0V 0.04 mW

fSCL=400kHz VA= 5.0V 0.14 mW

PPD2 Power Consumption VA= 3.0V 0.29 mW

fSCL=3.4MHz VA= 5.0V 0.84 mW

A.C. and Timing Characteristics

The following specifications apply for VA= +2.7V to +5.5V. Boldface limits apply for TMIN ≤TA≤TMAX and all other limits are

at TA= 25°C, unless otherwise specified. Typical Limits Units

Symbol Parameter Conditions (1) (2) (2) (1) (Limits)

CONVERSION RATE

Conversion Time 1 µs

fSCL = 100kHz 5.56 ksps

fSCL = 400kHz 22.2 ksps

fCONV Conversion Rate fSCL = 1.7MHz 94.4 ksps

fSCL = 3.4MHz 188.9 ksps

DIGITAL TIMING SPECS (SCL, SDA)

Standard Mode 100 kHz (max)

Fast Mode 400 kHz (max)

fSCL Serial Clock Frequency High Speed Mode, Cb= 100pF 3.4 MHz (max)

High Speed Mode, Cb= 400pF 1.7 MHz (max)

Standard Mode 4.7 us (min)

Fast Mode 1.3 us (min)

tLOW SCL Low Time High Speed Mode, Cb= 100pF 160 ns (min)

High Speed Mode, Cb= 400pF 320 ns (min)

Standard Mode 4.0 us (min)

Fast Mode 0.6 us (min)

tHIGH SCL High Time High Speed Mode, Cb= 100pF 60 ns (min)

High Speed Mode, Cb= 400pF 120 ns (min)

Standard Mode 250 ns (min)

tSU;DAT Data Setup Time Fast Mode 100 ns (min)

High Speed Mode 10 ns (min)

0us (min)

Standard Mode (3) 3.45 us (max)

0us (min)

Fast Mode (3) 0.9 us (max)

tHD;DAT Data Hold Time 0ns (min)

High Speed Mode, Cb= 100pF 70 ns (max)

0ns (min)

High Speed Mode, Cb= 400pF 150 ns (max)

Standard Mode 4.7 us (min)

Setup time for a start or a repeated

tSU;STA Fast Mode 0.6 us (min)

start condition High Speed Mode 160 ns (min)

Standard Mode 4.0 us (min)

Hold time for a start or a repeated start

tHD;STA Fast Mode 0.6 us (min)

condition High Speed Mode 160 ns (min)

Bus free time between a stop and start Standard Mode 4.7 us (min)

tBUF condition Fast Mode 1.3 us (min)

(1) Cbrefers to the capacitance of one bus line. Cbis expressed in pF units.

(2) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average

Outgoing Quality Level).

(3) The ADC101C021 will provide a minimum data hold time of 300ns to comply with the I2C Specification.

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A.C. and Timing Characteristics (continued)

The following specifications apply for VA= +2.7V to +5.5V. Boldface limits apply for TMIN ≤TA≤TMAX and all other limits are

at TA= 25°C, unless otherwise specified. Typical Limits Units

Symbol Parameter Conditions (1) (2) (2) (1) (Limits)

Standard Mode 4.0 us (min)

tSU;STO Setup time for a stop condition Fast Mode 0.6 us (min)

High Speed Mode 160 ns (min)

Standard Mode 1000 ns (max)

20+0.1Cbns (min)

Fast Mode 300 ns (max)

trDA Rise time of SDA signal 10 ns (min)

High Speed Mode, Cb= 100pF 80 ns (max)

20 ns (min)

High Speed Mode, Cb= 400pF 160 ns (max)

Standard Mode 250 ns (max)

20+0.1Cbns (min)

Fast Mode 250 ns (max)

tfDA Fall time of SDA signal 10 ns (min)

High Speed Mode, Cb= 100pF 80 ns (max)

20 ns (min)

High Speed Mode, Cb= 400pF 160 ns (max)

Standard Mode 1000 ns (max)

20+0.1Cbns (min)

Fast Mode 300 ns (max)

trCL Rise time of SCL signal 10 ns (min)

High Speed Mode, Cb= 100pF 40 ns (max)

20 ns (min)

High Speed Mode, Cb= 400pF 80 ns (max)

Standard Mode 1000 ns (max)

20+0.1Cbns (min)

Fast Mode 300 ns (max)

Rise time of SCL signal after a

trCL1 repeated start condition and after an 10 ns (min)

High Speed Mode, Cb= 100pF

acknowledge bit. 80 ns (max)

20 ns (min)

High Speed Mode, Cb= 400pF 160 ns (max)

Standard Mode 300 ns (max)

20+0.1Cbns (min)

Fast Mode 300 ns (max)

tfCL Fall time of a SCL signal 10 ns (min)

High Speed Mode, Cb= 100pF 40 ns (max)

20 ns (min)

High Speed Mode, Cb= 400pF 80 ns (max)

Capacitive load for each bus line (SCL

Cb400 pF (max)

and SDA)

Pulse Width of spike suppressed Fast Mode 50 ns (max)

tSP (4) High Speed Mode 10 ns (max)

(4) Spike suppression filtering on SCL and SDA will suppress spikes that are less than 50ns for standard and fast modes, and less than

10ns for hs-mode.

Product Folder Links: ADC101C021 ADC101C027

SCL

SDA

tHD;STA

tLOW

tHD;DAT tHIGH

tSU;DAT

tSU;STA tSU;STO

START REPEATED

START STOP

tHD;STA

START

tSP

trtBUF

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Timing Diagrams

Figure 1. Serial Timing Diagram

Specification Definitions

ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold

capacitor is charged by the input voltage.

APERTURE DELAY is the time between the start of a conversion and the time when the input signal is internally

acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the

power in both the second and third order intermodulation products to the power in one of the original frequencies.

Second order products are fa± fb, where faand fbare the two sine wave input frequencies. Third order products

are (2fa± fb) and (fa± 2fb). IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC output. The ADC101C021 is

guaranteed not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

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A++A

logTHD = 20 /

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SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is

any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first n harmonic

components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated

(1)

where Af1 is the RMS power of the input frequency at the output and Af2 through Afn are the RMS power in the

first n harmonic frequencies.

THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the

acquisition time plus the conversion time.

LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is

LSB = VA/ 2n(2)

where VAis the supply voltage for this product, and "n" is the resolution in bits, which is 10 for the ADC101C021.

MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is

1/2 of VA.

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Typical Performance Characteristics

fSCL = 400kHz, fSAMPLE = 22kSPS, fIN = 1kHz, VA= 5.0V, TA= +25°C, unless otherwise stated.

INL vs. Code - VA=3V DNL vs. Code - VA=3V

Figure 2. Figure 3.

INL vs. Code - VA=5V DNL vs. Code - VA=5V

Figure 4. Figure 5.

INL vs. Supply DNL vs. Supply

Figure 6. Figure 7.

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Typical Performance Characteristics (continued)

fSCL = 400kHz, fSAMPLE = 22kSPS, fIN = 1kHz, VA= 5.0V, TA= +25°C, unless otherwise stated.

ENOB vs. Supply SINAD vs. Supply

Figure 8. Figure 9.

FFT Plot - VA=3V FFT Plot - VA=3V

Figure 10. Figure 11.

Offset Error vs. Temperature Gain Error vs. Temperature

Figure 12. Figure 13.

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Typical Performance Characteristics (continued)

fSCL = 400kHz, fSAMPLE = 22kSPS, fIN = 1kHz, VA= 5.0V, TA= +25°C, unless otherwise stated.

Continuous Operation Supply Current vs. VAAutomatic Conversion Supply Current vs. VA

Figure 14. Figure 15.

Power Down (PD1) Supply Current vs. VA

Figure 16.

Product Folder Links: ADC101C021 ADC101C027

VIN

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

SW2

VA/2

CHARGE

REDISTRIBUTION

DAC

VIN

AGND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

SW2

VA/2

CHARGE

REDISTRIBUTION

DAC

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FUNCTIONAL DESCRIPTION

The ADC101C021 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Unless otherwise stated, references to the ADC101C021 in this section

will apply to both the ADC101C021 and the ADC101C027.

CONVERTER OPERATION

Simplified schematics of the ADC101C021 in both track and hold modes are shown in Figure 17 and Figure 18,

respectively. In Figure 17, the ADC101C021 is in track mode. SW1 connects the sampling capacitor to the

analog input channel and SW2 equalizes the comparator inputs. The ADC is in this state for approximately 0.4µs

at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when the

conversion result register is read and when the ADC is in automatic conversion mode. (see Section AUTOMATIC

CONVERSION MODE).

Figure 18 shows the ADC101C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2

unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract

fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the

comparator is balanced, the digital word supplied to the DAC is also the digital representation of the analog input

voltage. This digital word is stored in the conversion result register and read via the 2-wire interface.

In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result

is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of

the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that

the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum

conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,

as described in Section INTERNAL REGISTERS.

Figure 17. ADC101C021 in Track Mode

Figure 18. ADC101C021 in Hold Mode

ANALOG INPUT

An equivalent circuit for the input of the ADC101C021 is shown in Figure 19. The diodes provide ESD protection

for the analog input. The operating range for the analog input is 0 V to VA. Going beyond this range will cause

the ESD diodes to conduct and may result in erratic operation. For this reason, these diodes should NOT be

used to clamp the input signal.

Product Folder Links: ADC101C021 ADC101C027

0V +VA - 1.5 LSB

0.5 LSB ANALOG INPUT

1 LSB = VA/1024

ADC CODE

111...111

111...110

111...000

011...111

000...010

000...001

000...000

VIN

30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

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The capacitor C1 in Figure 19 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1

is the on resistance (RON) of the multiplexer and track / hold switch and is typically 500Ω. Capacitor C2 is the

ADC101C021 sampling capacitor and is typically 30 pF. The ADC101C021 will deliver best performance when

driven by a low-impedance source (less than 100Ω). This is especially important when using the ADC101C021 to

sample dynamic signals. A buffer amplifier may be necessary to limit source impedance. Use a precision op-amp

to maximize circuit performance. Also important when sampling dynamic signals is a band-pass or low-pass filter

to reduce noise at the input.

Figure 19. Equivalent Input Circuit

The analog input is sampled for eight internal clock cycles, or for typically 400 ns, after the fall of SDA for

acknowledgement. This time could be as long as about 530 ns. The sampling switch opens and the conversion

begins this time after the fall of ACK. This time are typical at room temperature and may vary with temperature.

ADC TRANSFER FUNCTION

The output format of the ADC101C021 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC101C021 is VA/ 1024. The ideal transfer characteristic is shown

in Figure 20. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,

or a voltage of VA/ 2048. Other code transitions occur at intervals of 1 LSB.

Figure 20. Ideal Transfer Characteristic

REFERENCE VOLTAGE

The ADC101C021 uses the supply (VA) as the reference, so VAmust be treated as a reference. The analog-to-

digital conversion will only be as precise as the reference (VA), so the supply voltage should be free of noise. The

reference should be driven by a low output impedance voltage source.

The Applications section provides recommended ways to provide the supply voltage appropriately. Refer to

Section TYPICAL APPLICATION CIRCUIT for details.

Product Folder Links: ADC101C021 ADC101C027

SDA

SCL

I2C Serial Interface

Conversion Result

Pointer = 00000000

Pointer

(selects

read from

or write to)

Pointer Address

Highest Conversion

Pointer = 00000111

Lowest Conversion

Pointer = 00000110

Configuration

Pointer = 00000010

Alert Status

Pointer = 00000001

Hysteresis

Pointer = 00000101

High Limit

Pointer = 00000100

Low Limit

Pointer = 00000011

Data

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POWER-ON RESET

An internal power-on reset (POR) occurs when the supply voltage transitions above the power-on reset

threshold. Each of the registers contains a defined value upon POR and this data remains there until any of the

following occurs:

• The first conversion is completed, causing the Conversion Result and Status registers to be updated.

• A different data word is written to a writable register.

• The ADC is powered down.

The internal registers will lose their contents if the supply voltage goes below 2.4V. Should this happen, it is

important that the VAsupply be lowered to a maximum of 200mV before the supply is raised again to properly

reset the device and ensure that the ADC performs as specified.

INTERNAL REGISTERS

The ADC101C021 has 8 internal data registers and one address pointer. The registers provide additional ADC

functions such as storing minimum and maximum conversion results, setting alert threshold levels, and storing

data to configure the operation of the device. Figure 21 shows all of the registers and their corresponding

address pointer values. All of the registers are read/write capable except the conversion result register, which is

read-only.

Figure 21. Register Structure

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Address Pointer Register

The address pointer determines which of the data registers is accessed by the I2C interface. The first data byte

of every write operation is stored in the address pointer register. This value selects the register that the following

data bytes will be written to or read from. Only the three LSBs of this register are variable. The other bits must

always be written to as zeros. After a power-on reset, the pointer register defaults to all zeros (conversion result

Default Value: 00h

P7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0 0 Register Select

P2 P1 P0 REGISTER

0 0 0 Conversion Result (read only)

0 0 1 Alert Status (read/write)

0 1 0 Configuration (read/write)

0 1 1 Low Limit (read/write)

1 0 0 High Limit (read/write)

1 0 1 Hysteresis (read/write)

1 1 0 Lowest Conversion (read/write)

1 1 1 Highest Conversion (read/write)

Conversion Result Register

This register holds the result of the most recent conversion. In the normal mode, a new conversion is started

whenever this register is read. The conversion result data is in straight binary format with the MSB at D11.

Pointer Address 00h (Read Only)

Default Value: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

Alert Flag Reserved Conversion Result [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

Conversion Result [5:0] Reserved

Bits Name Description

15 Alert Flag This bit indicates when an alert condition has occurred. When the Alert Bit Enable is set in the

Configuration Register, this bit will be high if either alert flag is set in the Alert Status Register.

Otherwise, this bit is a zero. The I2C controller will typically read the Alert Status register and other data

registers to determine the source of the alert.

14:12 Reserved Always reads zeros.

11:2 Conversion Result The Analog-to-Digital conversion result. The Conversion result data is a 10-bit data word in straight

binary format. The MSB is D11.

1:0 Reserved Always reads zeros.

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Alert Status Register

This register indicates if a high or a low threshold has been violated. The bits of this register are active high. That

is, a high indicates that the respective limit has been violated.

Pointer Address 01h (Read/Write)

Default Value: 00h

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Over Range Under Range

Alert Alert

Bits Name Description

7:2 Reserved Always reads zeros. Zeros must be written to these bits.

1 Over Range Bit is set to 1 when the measured voltage exceeds the VHIGH limit stored in the programmable VHIGH

Alert Flag limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes

a one to this bit. (2) The measured voltage decreases below the programmed VHIGH limit minus the

programmed VHYST value (See Figure 24) . The alert will only self-clear if the Alert Hold bit is cleared in

the Configuration register. If the Alert Hold bit is set, the only way to clear an over range alert is to write

a one to this bit.

0 Under Range Bit is set to 1 when the measured voltage falls below the VLOW limit stored in the programmable VLOW

Alert Flag limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes

a one to this bit. (2) The measured voltage increases above the programmed VLOW limit plus the

programmed VHYST value. The alert will only self-clear if the Alert Hold bit is cleared in the

Configuration register. If the Alert Hold bit is set, the only way to clear an under range alert is to write a

one to this bit.

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Configuration Register

Pointer Address 02h (Read/Write)

Default Value: 00h

D7 D6 D5 D4 D3 D2 D1 D0

Cycle Time [2:0] Alert Hold Alert Flag Enable Alert Pin Enable 0 Polarity

Cycle Time[2:0] Conversion Typical

Interval fconvert

D7 D6 D5 (ksps)

0 0 0 Mode Disabled 0

0 0 1 Tconvert x 32 27

0 1 0 Tconvert x 64 13.5

0 1 1 Tconvert x 128 6.7

1 0 0 Tconvert x 256 3.4

1 0 1 Tconvert x 512 1.7

1 1 0 Tconvert x 1024 0.9

1 1 1 Tconvert x 2048 0.4

Bits Name Description

7:5 Cycle Time Configures Automatic Conversion mode. When these bits are set to zeros, the automatic conversion

mode is disabled. This is the case at power-up.

When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion

mode. (See AUTOMATIC CONVERSION MODE). The Cycle Time table shows how different values

provide various conversion intervals.

4 Alert Hold 0: Alerts will self-clear when the measured voltage moves within the limits by more than the hysteresis

1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the alert

low flag in the Alert Status register.

3 Alert Flag Enable 0: Disables alert status bit [D15] in the Conversion Result register.

1: Enables alert status bit [D15] in the Conversion Result register.

2 Alert Pin Enable 0: Disables the ALERT output pin. The ALERT output will TRI-STATE when the pin is disabled.

1: Enables the ALERT output pin.

*This bit does not apply to the ADC101C027.

1 Reserved Always reads zeros. Zeros must be written to these bits.

0 Polarity This bit configures the active level polarity of the ALERT output pin.

0: Sets the ALERT pin to active low.

1: Sets the ALERT pin to active high.

*This bit does not apply to the ADC101C027.

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VLOW -- Alert Limit Register - Under Range

This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower

than this limit, a VLOW alert is generated.

Pointer Address 03h (Read/Write)

Default Value: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

Reserved VLOW Limit [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

VLOW Limit [5:0] Reserved

Bits Name Description

15:12 Reserved Always reads zeros. Zeros must be written to these bits.

11:2 VLOW Limit Sets the lower limit threshold used to determine the alert condition. If the conversion moves lower than

this limit, a VLOW alert is generated.

1:0 Reserved Always reads zeros. Zeros must be written to these bits.

VHIGH -- Alert Limit Register - Over Range

This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher

than this limit, a VHIGH alert is generated.

Pointer Address 04h (Read/Write)

Default Value: 0FFFh

D15 D14 D13 D12 D11 D10 D9 D8

Reserved VHIGH Limit [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

VHIGH Limit [5:0] Reserved

Bits Name Description

15:12 Reserved Always reads zeros. Zeros must be written to these bits.

11:2 VHIGH Limit Sets the upper limit threshold used to determine the alert condition. If the conversion moves higher

than this limit, a VHIGH alert is generated.

1:0 Reserved Always reads zeros. Zeros must be written to these bits.

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VHYST -- Alert Hysteresis Register

This register holds the hysteresis value used to determine the alert condition. After a VHIGH or VLOW alert occurs,

the conversion result must move within the VHIGH or VLOW limit by more than this value to clear the alert

condition. Note: If the Alert Hold bit is set in the configuration register, alert conditions will not self-clear.

Pointer Address 05h (Read/Write)

Default Value: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

Reserved Hysteresis [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

Hysteresis [5:0] Reserved

Bits Name Description

15:12 Reserved Always reads zeros. Zeros must be written to these bits.

11:2 Hysteresis Sets the hysteresis value used to determine the alert condition. D11 is MSB. After a VHIGH or VLOW

alert occurs, the conversion result must move within the VHIGH or VLOW limit by more than this value to

clear the alert condition.

Note: If the Alert Hold bit is set in the configuration register, alert conditions will not self-clear.

1:0 Reserved Always reads zeros. Zeros must be written to these bits.

VMIN -- Lowest Conversion Register

This register holds the Lowest Conversion result when in the automatic conversion mode. Each conversion result

is compared against the contents of this register. If the value is lower, it becomes the lowest conversion and

replaces the current value. If the value is higher, the register contents remain unchanged. The lowest conversion

value can be cleared at any time by writing 0FFFh to this register. The value of this register will update

automatically when the automatic conversion mode is enabled, but is NOT updated in the normal mode.

Pointer Address 06h (Read/Write)

Default Value: 0FFFh

D15 D14 D13 D12 D11 D10 D9 D8

Reserved Lowest Conversion [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

Lowest Conversion [5:0] Reserved

Bits Name Description

15:12 Reserved Always reads zeros. Zeros must be written to these bits.

11:2 Lowest Conversion Contains the Lowest Conversion result. D11 is MSB.

1:0 Reserved Always reads zeros. Zeros must be written to these bits.

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VMAX -- Highest Conversion Register

This register holds the Highest Conversion result when in the Automatic mode. Each conversion result is

compared against the contents of this register. If the value is higher, it replaces the previous value. If the value is

lower, the register contents remain unchanged. The highest conversion value can be cleared at any time by

writing 0000h to this register. The value of this register will update automatically when the automatic conversion

mode is enabled, but is NOT updated in the normal mode.

Pointer Address 07h (Read/Write)

Default Value: 0000h

D15 D14 D13 D12 D11 D10 D9 D8

Reserved Highest Conversion [9:6]

D7 D6 D5 D4 D3 D2 D1 D0

Highest Conversion [5:0] Reserved

Bits Name Description

15:12 Reserved Always reads zeros. Zeros must be written to these bits.

11:2 Highest Conversion Highest conversion result. D11 is MSB.

1:0 Reserved Always reads zeros. Zeros must be written to these bits.

SERIAL INTERFACE

The I2C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode

(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed

mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document.

The following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up

resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being

driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output

and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus

capacitance and operating speed. The ADC101C021 offers extended ESD tolerance (8kV HBM) for the I2C bus

pins (SCL & SDA) allowing extension of the bus across multiple boards without extra ESD protection.

Basic I2C Protocol

The I2C interface is bi-directional and allows multiple devices to operate on the same bus. The bus consists of

master devices and slave devices which can communicate back and forth over the I2C interface. Master devices

control the bus and are typically microcontrollers, FPGAs, DSPs, or other digital controllers. Slave devices are

controlled by a master and are typically peripheral devices such as the ADC101C021. To support multiple

devices on the same bus, each slave has a unique hardware address which is referred to as the "slave address."

To communicate with a particular device on the bus, the controller (master) sends the slave address and listens

for a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is

addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't

match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs

also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after

every data byte is successfully received. When the master is reading data, the master ACKs after every data

byte is received to let the slave know it wants to receive another data byte. When the master wants to stop

reading, it NACKs after the last data byte and creates a stop condition on the bus.

All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for

starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master

generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is

more complicated. Please refer to Section High-Speed (Hs) Mode for the full details of a Hs-mode Start

condition.

Product Folder Links: ADC101C021 ADC101C027

SCL

SDA

START or

REPEATED

START

STOP

1 2 6 7 891 2 89

MSB

7-bit Slave Address R/W

Direction

BitAcknowledge

from the Device

MSB

Data Byte

*Acknowledge

or Not-ACK

ACK N/ACK

Repeated for the Lower Data Byte

and Additional Data Transfers

LSB LSB

*Note: In continuous mode, this bit must be an ACK from

the data receiver. Immediately preceding a STOP

condition, this bit must be a NACK from the master.

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A Repeated Start is generated to address a different device or register, or to switch between read and write

modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the

Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 22. The bus

continues to operate in the same speed mode as before the Repeated Start condition.

All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop

condition occurs when SDA is pulled high while SCL is high. After a Stop condition, the bus remains idle until a

master generates another Start condition.

Please refer to the Philips I2C®Specification (Version 2.1 Jan, 2000) for a detailed description of the serial

interface.

Figure 22. Basic Operation.

Standard-Fast Mode

In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is

high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have

been transmitted by the master, SDA is released by the master and the ADC101C021 either ACKs or NACKs the

address. If the slave address matches, the ADC101C021 ACKs the master. If the address doesn't match, the

ADC101C021 NACKs the master.

For a write operation, the master follows the ACK by sending the 8-bit register address pointer to the ADC. Then

the ADC101C021 ACKs the transfer by driving SDA low. Next, the master sends the upper 8-bits to the

ADC101C021. Then the ADC101C021 ACKs the transfer by driving SDA low. For a single byte transfer, the

master should generate a stop condition at this point. For a 2-byte write operation, the lower 8-bits are sent by

the master. The ADC101C021 then ACKs the transfer, and the master either sends another pair of data bytes,

generates a Repeated Start condition to read or write another register, or generates a Stop condition to end

communication.

Aread operation can take place either of two ways:

If the address pointer is pre-set before the read operation, the desired register can be read immediately following

the slave address. In this case, the upper 8-bits of the register, set by the pre-set address pointer, are sent out

by the ADC. For a single byte read operation, the Master sends a NACK to the ADC and generates a Stop

condition to end communication after receiving 8-bits of data. For a 2-byte read operation, the Master continues

the transmission by sending an ACK to the ADC. Then the ADC sends out the lower 8-bits of the ADC register.

At this point, the master either sends an ACK to receive more data or, a NACK followed by a Stop or Repeated

Start. If the master sends an ACK, the ADC sends the next upper data byte, and the read cycle repeats.

If the ADC101C021 address pointer needs to be set, the master needs to write to the device and set the address

pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit,

the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 27).

Following this sequence, the ADC sends out the upper 8-bits of the register. For a single byte read operation, the

Master must then send a NACK to the ADC and generate a Stop condition to end communication. For a 2-Byte

write operation, the Master sends an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC

Repeated Start. If the master sends an ACK, the ADC sends another pair of data bytes, and the read cycle will

repeat. The number of data words that can be read is unlimited.

Product Folder Links: ADC101C021 ADC101C027

SCL

SDA

START

1 2 6 7 89

8-ELW0DVWHUFRGH³00001[[[´

Not-Acknowledge

from the Device

NACK

Standard-Fast Mode Hs-Mode

Repeated

START

1 2

MSB

7-bit Slave

Address

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High-Speed (Hs) Mode

For Hs-mode, the sequence of events to begin communication differs slightly from Standard-Fast mode.

Figure 23 describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master

generates a Start condition and sends the 8-bit Hs master code (00001XXX) to the ADC101C021. Next, the

ADC101C021 responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to

Hs-mode by increasing the bus speed and generating a second Repeated Start condition (driving SDA low while

SCL is pulled high). At this point, the master sends the slave address to the ADC101C021, and communication

continues as shown above in the "Basic Operation" Diagram (see Figure 22).

When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the

slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the

master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode

again before increasing the bus speed and switching to Hs-mode.

Figure 23. Beginning Hs-Mode Communication

I2C Slave (Hardware) Address

The ADC has a seven-bit hardware address which is also referred to as a slave address. For the VSSOP-8

version of the ADC101C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the

ADC101C027, the address is configured by the ADR0 address selection input. ADR0 and ADR1 can be

grounded, left floating, or tied to VA. If desired, ADR0 can be set to VA/2 rather than left floating. The state of

these inputs sets the hardware address that the ADC responds to on the I2C bus (see Table 3). For the SOT-6

version of the ADC101C021, the hardware address is not pin-configurable and is set to 1010100. The diagrams

in COMMUNICATING WITH THE ADC101C021 describe how the I2C controller should address the ADC via the

I2C interface.

Pin compatible alternatives that provide additional address options to the SOT-6 version of the ADC101C021 and

the ADC101C027 are available.

Table 3. Slave Addresses

ADC101C027 ADC101C021 ADC101C021

(SOT-6) (SOT-6) (VSSOP-8)

Slave Address

[A6 - A0] ADR0 ALERT ADR1 ADR0

1010000 Floating ----------------- Floating Floating

1010001 GND ----------------- Floating GND

1010010 VA----------------- Floating VA

1010100 ----------------- Single Address GND Floating

1010101 ----------------- ----------------- GND GND

1010110 ----------------- ----------------- GND VA

1011000 ----------------- ----------------- VAFloating

1011001 ----------------- ----------------- VAGND

1011010 ----------------- ----------------- VAVA

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TIME

VOLTAGE

Measured Voltage

VHIGH Limit

VHIGH - VHYST

ALERT pin

(Active Low)

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ALERT FUNCTION

The ALERT function is an "out-of-range" indicator. At the end of every conversion, the measured voltage is

compared to the values in the VHIGH and VLOW registers. If the measured voltage exceeds the value stored in

VHIGH or falls below the value stored in VLOW, an alert condition occurs. The Alert condition is indicated in up to

three places. First, the alert condition always causes either or both of the alert flags in the Alert Status register to

go high. If the measured voltage exceeds the VHIGH limit, the Over Range Alert Flag is set. If the measured

voltage falls below the VLOW limit, the Under Range Alert Flag is set. Second, if the Alert Flag Enable bit is set in

the Configuration register, the alert condition also sets the MSB of the Conversion Result register. Third, if the

Alert Pin Enable bit is set in the Configuration register, the ALERT output becomes active (see Figure 24). The

ALERT output (ADC101S021 only) can be configured as an active high or active low output via the Polarity bit in

the Configuration register. If the Polarity bit is cleared, the ALERT output is configured as active low. If the

Polarity bit is set, the ALERT output is configured as active high.

The Over Range Alert condition is cleared when one of the following two conditions is met:

1. The controller writes a one to the Over Range Alert Flag bit.

2. The measured voltage goes below the programmed VHIGH limit minus the programmed VHYST value and the

Alert Hold bit is cleared in the Configuration register. (see Figure 24). If the Alert Hold bit is set, the alert

condition persists and only clears when a one is written to the Over Range Alert Flag bit.

The Under Range Alert condition is cleared when one of the following two conditions is met:

1. The controller writes a one to the Under Range Alert Flag bit.

2. The measured voltage goes above the programmed VLOW limit plus the programmed VHYST value and the

Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the alert condition persists

and only clears when a one is written to the Under Range Alert Flag bit.

If the alert condition has been cleared by writing a one to the alert flag while the measured voltage still violates

the VHIGH or VLOW limits, an alert condition will occur again after the completion of the next conversion (see

Figure 25).

Alert conditions only occur if the input voltage exceeds the VHIGH limit or falls below the VLOW limit at the sample-

hold instant. The input voltage can exceed the VHIGH limit or fall below the VLOW limit briefly between conversions

without causing an alert condition.

Figure 24. Alert condition cleared when measured voltage crosses VHIGH - VHYST

Product Folder Links: ADC101C021 ADC101C027

TIME

VOLTAGE

VHIGH Limit

VHIGH - VHYST

ALERT pin

(Active Low)

Measured Voltage

Over Range Alert

)ODJVHWWR³1´

ADC101C021, ADC101C027

www.ti.com

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

Figure 25. Alert condition cleared by writing a "1" to the Alert Flag.

AUTOMATIC CONVERSION MODE

The automatic conversion mode configures the ADC to continually perform conversions without receiving "read"

instructions from the controller over the I2C interface. The mode is activated by writing a non-zero value into the

Cycle Time bits - D[7:5] - of the Configuration register (see Configuration Register). Once the ADC101C021

enters this mode, the internal oscillator is always enabled. The ADC's control logic samples the input at the

sample rate set by the cycle time bits. Although the conversion result is not transmitted by the 2-wire interface, it

is stored in the conversion result register and updates the various status registers of the device.

In automatic conversion mode, the out-of-range alert function is active and updates after every conversion. The

ADC can operate independently of the controller in automatic conversion mode. When the input signal goes "out-

of-range", an alert signal is sent to the controller. The controller can then read the status registers and determine

the source of the alert condition. Also, comparison and updating of the VMIN and VMAX registers occur after every

conversion in automatic conversion mode. The controller can occasionally read the VMIN and/or VMAX registers to

determine the sampled input extremes. These register values persist until the user resets the VMIN and VMAX

registers. These two features are useful in system monitoring, peak detection, and sensing applications.

COMMUNICATING WITH THE ADC101C021

The ADC101C021's data registers are selected by the address pointer (see Address Pointer Register). To

read/write a specific data register, the pointer must be set to that register's address. The pointer is always written

at the beginning of a write operation. When the pointer needs to be updated for a read cycle, a write operation

must precede the read operation to set the pointer address correctly. On the other hand, if the pointer is preset

correctly, a read operation can occur without writing the address pointer register. The following timing diagrams

describe the various read and write operations supported by the ADC.

Product Folder Links: ADC101C021 ADC101C027

1 9 1 9

Ack

ADC

Start by

Master

R/W Ack

ADC

Frame 1

Address Byte

from Master

Frame 2

Pointer Byte

from Master

0 0 0 0 P2 P1 P0

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

ACK

ADC

N/ACK*

Master

Stop

Master

1 9

D15 D14 D13 D12 D11 D10 D9 D8 ACK

Master

Frame 3

Address Byte

from Master

Frame 4

Data Byte from

ADC

Frame 5

Data Byte from

ADC

R/W

A2 A0A1

A3A4A5A6

Repeat Frames

4 & 5 for

Continuous Mode

*Note: In continuous mode, this bit must be an ACK. Immediately

preceding a STOP condition, this bit must be a NACK.

Repeat

Start by

Master

A2 A0A1A3A4A5A6

SCL

SDA 0

SCL

(continued)

SDA

(continued)

D7 D6 D5 D4 D3 D2 D1 D0

1 9 1 9

ACK

ADC

Start by

Master N/ACK*

Master

SCL

SDA Stop

Master

1 9

D15 D14 D13 D12 D11 D10 D9 D8 ACK

Master

Frame 1

Address Byte

from Master

Frame 2

Data Byte from

ADC

Frame 3

Data Byte from

ADC

R/W

A2 A0A1

A3A4A5A6

Repeat Frames

2 & 3 for

Continuous Mode

*Note: In continuous mode, this bit must be an ACK. Immediately

preceding a STOP condition, this bit must be a NACK.

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

www.ti.com

Reading from a 2-Byte ADC Register

The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC101C021

Figure 26. Typical Read from a 2-Byte ADC Register with Preset Pointer

Figure 27. Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register

Product Folder Links: ADC101C021 ADC101C027

1 9 1 9

Ack

ADC

Start by

Master

R/W Ack

ADC

Frame 1

Address Byte

from Master

Frame 2

Pointer Byte

from Master

0 0 0 0 P2 P1 P0

D7 D6 D5 D4 D3 D2 D1 D0

1 9

ACK

ADC

NACK

Master

Stop

Master

1 9

Frame 3

Address Byte

from Master

Frame 4

Data Byte from

ADC

R/W

A2 A0A1

A3A4A5A6

Repeat

Start by

Master

A2 A0A1A3A4A5A6

SCL

SDA 0

SCL

(continued)

SDA

(continued)

D7 D6 D5 D4 D3 D2 D1 D0

1 9

ACK

ADC

Start by

Master NACK

Master

SCL

SDA Stop

Master

1 9

Frame 1

Address Byte

from Master

Frame 2

Data Byte from

ADC

R/W

A2 A0A1

A3A4A5A6

ADC101C021, ADC101C027

www.ti.com

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

Reading from a 1-Byte ADC Register

The following diagrams indicate the sequence of actions required for a single Byte read from an ADC101C021

Figure 28. Typical Read from a 1-Byte ADC Register with Preset Pointer

Figure 29. Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register

Product Folder Links: ADC101C021 ADC101C027

1 9 1 9

Ack

ADC

Start by

Master

R/W Ack

ADC

Frame 1

Address Byte

from Master

Frame 2

Pointer Byte

from Master

0 0 0 0 P2 P1 P0

D7 D6 D5 D4 D3 D2 D1 D0

1 9

ACK

ADC

NACK

Master

Stop

Master

1 9

Frame 3

Data Byte

from Master

Frame 4

Data Byte

from Master

A2 A0A1A3A4A5A6

SCL

SDA 0

SCL

(continued)

SDA

(continued) D15 D14 D13 D12 D11 D10 D9 D8

1 9 1 9

Start by

Master

R/W

Frame 1

Address Byte

from Master

D7 D6 D5 D4 D3 D2 D1 D0

1 9

Frame 3

Data Byte

from Master

Stop by

Master

SCL

SDA

Frame 2

Pointer Byte

from Master

ACK

ADC

ACK

ADC

ACK

ADC

A2 A0A1

A3A4A5A6 0 0 0 0 P2 P1 P00

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

www.ti.com

Writing to an ADC Register

The following diagrams indicate the sequence of actions required for writing to an ADC101C021 Register.

Figure 30. Typical Write to a 1-Byte ADC Register

Figure 31. Typical Write to a 2-Byte ADC Register

Product Folder Links: ADC101C021 ADC101C027

1 9

ACK

ADC

Start by

Master

R/W

ACK

Master

Frame 1

Address Byte

from Master

D7 D6 D5 D4 D3 D2 D1 D0

1 9

NACK

Master

Stop

Master

1 9

D15 D14 D13 D12 D11 D10 D9 D8 ACK

Master

Frame 4

Upper Data Byte

from ADC

Frame 5

Lower Data Byte

from ADC

Repeat Frames

4 and 5 for

Continuous Mode

A2 A0A1A3A4A5A6

SCL

SDA

SCL

(continued)

SDA

(continued) D7 D6 D5 D4 D3 D2 D1 D0

1 9

D15 D14 D13 D12 D11 D10 D9 D8 ACK

Master

Frame 2

Upper Data Byte

from ADC

Frame 3

Lower Data Byte

from ADC

Interface Delay

tQuiet 8 1us

Interface Delay

tQuiet 8 1us

ADC101C021, ADC101C027

www.ti.com

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

QUIET INTERFACE MODE

To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved

INL and DNL performance in I2C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput

rate of 162ksps. Figure 32 describes how to read the conversion result register in this mode. Basically, the

Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes

that the address pointer register is set to its default value.

Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode

performance is unaffected by the Quiet Interface mode.

Figure 32. Reading in Quiet Interface Mode

TYPICAL APPLICATION CIRCUIT

A typical application circuit is shown in Figure 33. The analog supply is bypassed with a capacitor network

located close to the ADC101C021. The ADC uses the analog supply (VA) as its reference voltage, so it is very

important that VAbe kept as clean as possible. Due to the low power requirements of the ADC101C021, it is

possible to use a precision reference as a power supply.

The bus pull-up resistors (RP) should be powered by the controller's supply. It is important that the pull-up

resistors are pulled to the same voltage potential as VA. This will ensure that the logic levels of all devices on the

bus are compatible. If the controller's supply is noisy, an appropriate bypass capacitor should be added between

the controller's supply pin and the pull-up resistors. For Hs-mode applications, this bypass capacitance will

improve the accuracy of the ADC.

The value of the pull-up resistors (RP) depends upon the characteristics of each particular I2C bus. The I2C

specification describes how to choose an appropriate value. As a general rule-of-thumb, we suggest using a 1kΩ

resistor for Hs-mode bus configurations and a 5kΩresistor for Standard or Fast Mode bus configurations.

Depending upon the bus capacitance, these values may or may not be sufficient to meet the timing requirements

of the I2C bus specification. Please see the I2C specification for further information.

Product Folder Links: ADC101C021 ADC101C027

VIN

SCL

SDA

ADDR

ADC101C027

0.1 PF

GND

4.7 PF

INPUT

Unregulated

Supply

LMP7731

LM4132

4.7 PF

VIN

SCL

SDA

ADC101C021

0.1 PF

GND

4.7 PF

22:

INPUT

470 pF

ALERT

5 k:RPRP

Regulated Supply

VDD

Controller

SCL

SDA

INTERRUPT

I2C BUS ...

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

www.ti.com

Figure 33. Typical Application Circuit

BUFFERED INPUT

A buffered input application circuit is shown in Figure 34. The analog input is buffered by a National

Semiconductor LMP7731. The non-inverting amplifier configuration provides a buffered gain stage for a single

ended source. This application circuit is good for single-ended sensor interface. The input must have a DC bias

level that keeps the ADC input signal from swinging below GND or above the supply (+5V in this case).

The LM4132, with its 0.05% accuracy over temperature, is an excellent choice as a reference source for the

ADC101C021.

Figure 34. Buffered Input Circuit

INTELLIGENT BATTERY MONITOR

The ADC101C021 is easily used as an intelligent battery monitor. The simple circuit shown in Figure 35, uses

the ADC101C021, the LP2980 fixed reference, and a resistor divider to implement an intelligent battery monitor

with a window supervisory feature. The window supervisory feature is implemented by the "out of range" alert

function. When the battery is recharging, the Over Range Alert will indicate that the charging cycle is complete

(see Figure 36). When the battery is nearing depletion, the Under Range Alert will indicate that the battery is low

(see Figure 37).

Product Folder Links: ADC101C021 ADC101C027

TIME

VOLTAGE

Measured

Battery

Voltage

VLOW Limit

ALERT pin

(Active Low)

DISCHARGE CYCLE

TIME

VOLTAGE

Measured

Battery

Voltage

VHigh Limit

ALERT pin

(Active Low)

RECHARGE CYCLE

VIN SCL

GND

ADC101C021

REF

[LP2980-2.8] R

120 nF

20 kÖ

SDA

ALERT

Low

Battery

Indicator

VBATT

To Controller...

20 kÖ

ADC101C021, ADC101C027

www.ti.com

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

Figure 35. Intelligent Battery Monitor Circuit

Figure 36. Recharge Cycle

Figure 37. Discharge Cycle

In addition to the window supervisory feature, the ADC101C021 will allow the controller to read the battery

voltage at any time during operation.

The accurate voltage reading and the alert feature will allow a controller to improve the efficiency of a battery-

powered device. During the discharge cycle, the controller can switch to a low-battery mode, safely suspend

operation, or report a precise battery level to the user. During the recharge cycle, the controller can implement an

intelligent recharge cycle, decreasing the charge rate when the battery charge nears capacity.

Trickle Charge Controller

While a battery is discharging, the ADC101C021 can be used to control a trickle charge to keep the battery near

full capacity (see Figure 38). When the alert output is active, the battery will recharge. An intelligent recharge

cycle will prevent over-charging and damaging the battery. With a trickle charge, the battery powered device can

be disconnected from the charger at any time with a full charge.

Product Folder Links: ADC101C021 ADC101C027

TIME

VOLTAGE

Measured

Battery Voltage

VLOW Limit

ALERT pin

(Active Low)

VLOW+VHYST

ADC101C021, ADC101C027

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

www.ti.com

Figure 38. Trickle Charge

LAYOUT, GROUNDING, AND BYPASSING

For best accuracy and minimum noise, the printed circuit board containing the ADC101C021 should have

separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.

Both of these planes should be located on the same board layer. A single, solid ground plane is preferred if

digital return current does not flow through the analog ground area. Frequently a single ground plane design will

utilize a "fencing" technique to prevent the mixing of analog and digital ground currents. Separate ground planes

should only be utilized when the fencing technique is inadequate. The separate ground planes must be

connected in one place, preferably near the ADC121C021. Special care is required to guarantee that signals do

not pass over power plane boundaries. Return currents must always have a continuous return path below their

traces.

The ADC101C021 power supply should be bypassed with a 4.7µF and a 0.1µF capacitor as close as possible to

the device with the 0.1µF right at the device supply pin. The 4.7µF capacitor should be a tantalum type and the

0.1µF capacitor should be a low ESL type. The power supply for the ADC101C021 should only be used for

analog circuits.

Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the

board. The clock and data lines should have controlled impedances.

Product Folder Links: ADC101C021 ADC101C027

ADC101C021, ADC101C027

www.ti.com

SNAS446D –FEBRUARY 2008–REVISED FEBRUARY 2013

REVISION HISTORY

Changes from Revision C (February 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 34

Product Folder Links: ADC101C021 ADC101C027

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC101C021CIMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X33C

ADC101C021CIMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X33C

ADC101C021CIMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM X38C

ADC101C027CIMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X32C

ADC101C027CIMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X32C

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC101C021CIMK/NOPB SOT-

23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

ADC101C021CIMKX/NOP

BSOT-

23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

ADC101C021CIMM/NOP

BVSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC101C027CIMK/NOPB SOT-

23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

ADC101C027CIMKX/NOP

BSOT-

23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC101C021CIMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0

ADC101C021CIMKX/NOP

BSOT-23-THIN DDC 6 3000 210.0 185.0 35.0

ADC101C021CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

ADC101C027CIMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0

ADC101C027CIMKX/NOP

BSOT-23-THIN DDC 6 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

0.20

0.12 TYP 0.25

3.05

2.55

4X 0.95

1.100

0.847

0.1

0.0 TYP

6X 0.5

0.3

0.6

0.3 TYP

1.9

0 -8 TYP

3.05

2.75

1.75

1.45

SOT - 1.1 max heightDDC0006A

SOT

4214841/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-193.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

6X (1.1)

6X (0.6)

(2.7)

4X (0.95)

(R0.05) TYP

4214841/B 11/2020

SOT - 1.1 max heightDDC0006A

SOT

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN

SCALE:15X

SYMM

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDERMASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.7)

4X(0.95)

6X (1.1)

6X (0.6)

(R0.05) TYP

SOT - 1.1 max heightDDC0006A

SOT

4214841/B 11/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

SYMM

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