1 www.semtech.com
SC2595
Integrated Linear DDR
Termination Regulator
POWER MANAGEMENT
September 24, 2009
Typical Application Circuit
The SC2595 is an integrated linear DDR termination
device, which provides a complete solution for DDR
termination designs; while meeting the JEDEC require-
ments of SSTL-2 specifications for DDR-SDRAM termi-
nation.
The SC2595 can source and sink 1.5A current at the
output VTT while maintaining excellent load regulation.
VTT is designed to track the VREF voltage with a tight
tolerance over the entire current range while preventing
shoot through on the output stage.
A VSENSE pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage.
The SC2595 incorporates a disable function built into
the AVCC pin to tri-state the output during Suspend To
Ram (STR) states.
(Multiple patents pending.)
DDR memory termination
High speed data line termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
Regulates while sourcing or sinking 1.5A
AVCC range is from 2.5V to 5V
Reference output
Minimum number of external components
Accurate internal voltage divider
SOIC8-EDP package.Pb-free,Halogen free, and RoHS/
WEEE compliant
Description Features
Applications
SC2595
NC
1
GND
2
VSENSE
3
VREF
4VDDQ 5
AVCC 6
PVCC 7
VTT 8VTT
VDD
VREF
2©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
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(TJ = -40oC to +150oC). Unless otherwise specified, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
Electrical Characteristics
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
Note:Note:
Note:Note:
Note:
(1) For Load Regulation, use a 10ms current pulse width when measuring VTT.
Operating Range
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3©2009 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2595
Pin Configuration Ordering Information
Notes:
(1) Only available in tape and reel packaging. A reel contains
2500 devices for SOIC8-EDP package.
(2) Pb-free,Halogen free, and RoHS and WEEE compliant.
Part Number Package Temp. Range (TA)
SC2595STRT(1)(2) SOIC8-EDP -40 to +105OC
SC2595EVB Evaluation Board
1
2
3
4
VTT
NC
5
6
7
8
PVCCGND
AVCCVSENSE
VDDQVREF
TOP VIEW
(SOIC8-EDP)
4©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
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Pin Descriptions
5©2009 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2595
Block Diagram
OUT
+
-
GND
VDDQ
VREF
VSENSE
UVLO
+
-
PVCC AVCC
VTT
NC
Driver
Circu it
OUT
Notes:Notes:
Notes:Notes:
Notes:
(1) Can be used for vias.
(2) Power up of AVCC, PVCC and VDDQ supplies.
(a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply.
(b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should
lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously.
(c) If the AVCC, PVCC and VDDQ supply pins are connected in a way such that, AVCC, PVCC supplies precedes VDDQ supply;
then VTT output precedes VDDQ. This can cause the SDRAM device to latch-up, which may cause permanent
damage to the SDRAM.
6©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
OverviewOverview
OverviewOverview
Overview
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfers speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V; the power dissipation is smaller than
SDRAM. For above reasons, it is very popular and widely
used in M/B, N/B, Video-cards, CD ROM drives, Disk
drives.
Regarding the DDR power management solution, there
are two topologies can be selected for system design-
ers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and the
board space needed is bigger. Another solution is linear
mode regulator, which costs less, and needs the less
board space. For two DIMM motherboards, system de-
signers usually choose the linear mode for DDR power
management solution.
Applications
TT
TT
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Two different application circuits are shown below in Fig-
ure 1 to Figure 2. Each circuit is designed for specific
condition. More details are described below. See Note
1. Below for recommended power up sequencing.
Application_1: StandarApplication_1: Standar
Application_1: StandarApplication_1: Standar
Application_1: Standard SSd SS
d SSd SS
d SSTLTL
TLTL
TL-2 Application-2 Application
-2 Application-2 Application
-2 Application
The AVCC pins, the PVCC pin, and the VDDQ pin can be tied
together for SSTL-2 application. It only needs a 2.5V
power rail for normal operation. System designer can
save the PCB space and reduce the cost. Please refer
to figures 3 to 4 for test waveforms.
Figure 1: Standard SSTL-2 application
Application Information
Application_2: Lower Power Loss ConfigurationApplication_2: Lower Power Loss Configuration
Application_2: Lower Power Loss ConfigurationApplication_2: Lower Power Loss Configuration
Application_2: Lower Power Loss Configuration
ff
ff
for SSor SS
or SSor SS
or SSTLTL
TLTL
TL-2-2
-2-2
-2
If power loss is a major concern, separated the PVCC form
the AVCC and the VDDQ will be a good choice. The PVCC can
operate at lower voltage (1.8V to 2.5V). If 2.5V voltage
is applied on AVCC and the VDDQ, but the source current is
lower due to the lower operating voltage applied on the
PVCC. Please find the relative test result in Figures 5, 11
and 12.
Figure 2: Lower power loss for SSTL-2 application
Notes:Notes:
Notes:Notes:
Notes:
(1) Power up of AVCC, PVCC and VDDQ supplies.
(a) The preferred mode of operation is when the
AVCC, PVCC and VDDQ pins are tied together to a
single supply.
(b) If and when AVCC, PVCC pins are tied to a supply
separate to that of the VDDQ supply pin; then
the VDDQ supply should lead AVCC, PVCC supply or
the VDDQ supply and the AVCC, PVCC supply should
rise simultaneously.
(c) If the AVCC, PVCC and VDDQ supply pins are con
nected in a way such that, AVCC, PVCC supplies
precedes VDDQ supply; then VTT output precedes
VDDQ. This can cause the SDRAM device to latch-
up, which may cause permanent damage to the
SDRAM.
Cin2
1uF
Cout1
220uF
VDD
Cin1
68uF
Cout2
10uF
SC2595
NC
1
GND
2
VSENSE
3
VREF
4VDDQ 5
AVCC 6
PVCC 7
VTT 8VTT
Cref
10nF
Csence
2.2uF
2.5V
1.25V
R1
5.1
R2
R10uF
Cin2
1.25V
Csense
2.2uF 1uF
Cin2
Vin
2.5V
Cref
10nF
VTT
Cout1
220uF
SC2595
NC
1
GND
2
VSENSE
3
VREF
4VDDQ 5
AVCC 6
PVCC 7
VTT 8
Cddq
1uF
VDD
1.8V to 2.5V
Cin1
68uF
7©2009 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2595
Layout guidelinesLayout guidelines
Layout guidelinesLayout guidelines
Layout guidelines
1)The SC2595 has a SOIC8-EDP package. It can improve
the thermal impedance (θJC) significantly. A suitable ther-
mal pad should be added when PCB layout. Some ther-
mal vias are required to connect the thermal pad to the
PCB ground layer. This will improve the thermal perfor-
mance .
2)To increase the noise immunity, a ceramic capacitor of
10nf to 100nf is required to decouple the VREF pin with
the shortest connection trace, also A 10nF to 100nF
ceramic capacitor close to the VSENSE pin is required to
avoid oscillation during transient condition.
3)To reduce the noise on the input power rail for stan-
dard SSTL-2 application, a 68μF low ESR capacitor and
a 1μF ceramic capacitor have to be used on the input
power rail with shortest possible connection.
4)For lower power loss SSTL-2 application, a 220μF AL.
capacitor (ESR should be lower than 250m ohm) and a
10μF ceramic has to be added on the PVCC pin and a 1μF
ceramic capacitor +5.1 ohm filter has to be added on
the VDDQ pin with shortest possible connection.
5)VTT output copper plane should be as large as possible.
6)VSENSE trace should be as short as possible.
Application Information (Cont.)
8©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
Test Waveforms
Typical Characteristics
AVc c vs IQ
0
50
100
150
200
250
300
350
400
450
500
550
600
2.53.03.54.04.55.05.56.0
AVcc(V)
Quiescen t cu r r ent(uA)
VDDQ
=2.5V
VDDQ
=1.8V
AVCC=VDDQ=2.5V
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
1.81.9 2 2.12.22.32.42.5
PVCC(V)
OUTPUT CURRENT(A
)
MAX
SOURCE
CURREN
T
Figure 3 Figure 4
Figure 5 Figure 6
VTT
VREF
Test condition: Avcc=PVcc=VDDQ=2.5V,V TT=1.25V
Cout1=220uF, Cout2=10uF, Sink 2A.
VDDQ
AVcc
PVcc
Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V
Cout1=220uF, Cout2=10uF, Source 2A.
VDDQ
AVcc
PVcc
VTT
VREF
9©2009 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2595
Typical Characteristics (Cont.)
Q uiescen t Curr ent(AVCC = 2. 5V)
200
300
400
500
600
700
800
020406080100120140
Temperature (℃)
Current(uA)
2.5V
1.8V
Temp vs UVLO
1.90
1.91
1.92
1.93
1.94
1.95
1.96
1.97
1.98
1.99
2.00
20 30 40 50 60 70 80 90 100 110
Temperature(℃)
Voltage(V)
UVLO
(Typical)
VDDQ=PVCC=AVCC=2.5V
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
0 100 200 300 400 500 600 700 800 900
IREF(uA)
VREF(V)
V REF_max v s IREF(V DDQ=2.5V)
1.210
1.215
1.220
1.225
1.230
1.235
1.240
1.245
1.250
0 100 200 300 400 500 600 700 800 900
IREF(uA)
VREF(V)
-40℃
0℃
25℃
75℃
150℃
Figure 7 Figure 8
Figure 9 Figure 10
10©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
Typical Characteristics (Cont.)
VDDQ=2.5V
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
AVCC=PVCC(V)
Current(A)
MAX
SOURCE
CURRENT
VDDQ=1.8V
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
AVCC=PVCC(V)
Current(A)
MAX
SOURCE
CURRENT
AVCC=PVCC=VDDQ=2.5V
0
20
40
60
80
100
120
140
0.0 0.5 1.0 1.5 2.0 2.5
DC CURRENT (A)
Temperature(℃)
SOURCE
SINK
Figure 11 Figure 12
Figure 13
11©2009 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC2595
Outline Drawing - SOIC8-EDP
12©2009 Semtech Corp. www.semtech.com
SC2595
PRELIMINARYPOWER MANAGEMENT
Land Pattern - SOIC8-EDP
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Contact Information
